[PoC] Reduce impact `riscv_vector.h` when testing

[rogfer01]

Summary

Not to be commited.

This patch is a proof of concept of a way to reduce the impact of the size of riscv_vector.h when testing.

[khchen]

I think using this proxy header for testing seems good.

IMO, maybe we still need to find a way to reduce the compilation time for better user experience.

[asb]

In D100529#2690729, @khchen wrote:

I think using this proxy header for testing seems good.

IMO, maybe we still need to find a way to reduce the compilation time for better user experience.

Somewhat outside the scope of this review, but noting here for posterity seeing as we discussed it in the RISC-V sync-up today:

• It may be worth looking at the related discussion about parsing OpenCL headers (the thread moved on to discussing how the same problem applies to x86 intrinsics)
• Kito pointed out that for SVE, GCC implemented something like the approach by by providing #pragma GCC aarch64 "arm_sve.h" which is used as the body of arm_sve.h

clang/lib/Headers/CMakeLists.txt

function(clang_generate_header td_option td_file out_file)
   SOURCE ${CLANG_SOURCE_DIR}/include/clang/Basic/${td_file})
 
   copy_header_to_output_dir(${CMAKE_CURRENT_BINARY_DIR} ${out_file})
   set(out_files ${out_files} PARENT_SCOPE)
   list(APPEND generated_files "${CMAKE_CURRENT_BINARY_DIR}/${out_file}")
   set(generated_files ${generated_files} PARENT_SCOPE)
 endfunction(clang_generate_header)
 
+# Like clang_generate_header but does not add it to generated_files because
+# we do not want to install it.
+# FIXME: Factor this in a common function for both clang_generate_*header.
+function(clang_generate_testing_header td_option td_file out_file)
+  clang_tablegen(${out_file} ${td_option}
+  -I ${CLANG_SOURCE_DIR}/include/clang/Basic/
+  SOURCE ${CLANG_SOURCE_DIR}/include/clang/Basic/${td_file})
+
+  copy_header_to_output_dir(${CMAKE_CURRENT_BINARY_DIR} ${out_file})
+  set(out_files ${out_files} PARENT_SCOPE)
+endfunction(clang_generate_testing_header)
 
 # Copy header files from the source directory to the build directory
 foreach( f ${files} ${cuda_wrapper_files} ${ppc_wrapper_files} ${openmp_wrapper_files})
   copy_header_to_output_dir(${CMAKE_CURRENT_SOURCE_DIR} ${f})
 endforeach( f )
 
 # Generate header files and copy them to the build directory
 # Generate arm_neon.h
 clang_generate_header(-gen-arm-neon arm_neon.td arm_neon.h)
 # Generate arm_fp16.h
 clang_generate_header(-gen-arm-fp16 arm_fp16.td arm_fp16.h)
 # Generate arm_sve.h
 clang_generate_header(-gen-arm-sve-header arm_sve.td arm_sve.h)
 # Generate arm_bf16.h
 clang_generate_header(-gen-arm-bf16 arm_bf16.td arm_bf16.h)
 # Generate arm_mve.h
 clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
 # Generate arm_cde.h
 clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h)
 # Generate riscv_vector.h
 clang_generate_header(-gen-riscv-vector-header riscv_vector.td riscv_vector.h)
+# Generate testing header riscv_vector_testing.h
+clang_generate_testing_header(-gen-riscv-vector-testing-header riscv_vector.td
+                              riscv_vector_testing.h)
 
 add_custom_target(clang-resource-headers ALL DEPENDS ${out_files})
 set_target_properties(clang-resource-headers PROPERTIES
   FOLDER "Misc"
   RUNTIME_OUTPUT_DIRECTORY "${output_dir}")
 
 set(header_install_dir lib${LLVM_LIBDIR_SUFFIX}/clang/${CLANG_VERSION}/include)
 

clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
 // RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
 // RUN:   -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \
 // RUN:   -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
 
 // ASM-NOT: warning
-#include <riscv_vector.h>
+#define RVV_TEST_vadd
+#define RVV_TEST_vadd_mask
+#include <riscv_vector_testing.h>
 
 // CHECK-RV32-LABEL: @test_vadd_vv_i8mf8(
 // CHECK-RV32-NEXT:  entry:
 // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i32(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i32 [[VL:%.*]])
 // CHECK-RV32-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
 //
 // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(
 // CHECK-RV64-NEXT:  entry:

clang/utils/TableGen/RISCVVEmitter.cpp

private:
   RVVTypePtr OutputType; // Builtin output type
   RVVTypes InputTypes;   // Builtin input types
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector<int64_t> IntrinsicTypes;
   // C/C++ intrinsic operand order is different to builtin operand order. Record
   // the mapping of InputTypes index.
   SmallVector<unsigned> CTypeOrder;
+  bool TestingHeader = false;
   uint8_t RISCVExtensions = 0;
 
 public:
   RVVIntrinsic(StringRef Name, StringRef Suffix, StringRef MangledName,
                StringRef IRName, bool HasSideEffects, bool IsMask,
                bool HasMaskedOffOperand, bool HasVL, bool HasNoMaskedOverloaded,
                bool HasAutoDef, StringRef ManualCodegen, const RVVTypes &Types,
                const std::vector<int64_t> &IntrinsicTypes,
-               const std::vector<int64_t> &PermuteOperands);
+               const std::vector<int64_t> &PermuteOperands,
+               bool TestingHeader);
   ~RVVIntrinsic() = default;
 
   StringRef getName() const { return Name; }
   StringRef getMangledName() const { return MangledName; }
   bool hasSideEffects() const { return HasSideEffects; }
   bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
   bool hasVL() const { return HasVL; }
   bool hasNoMaskedOverloaded() const { return HasNoMaskedOverloaded; }
public:
   // Emit the code block for switch body in EmitRISCVBuiltinExpr, it should
   // init the RVVIntrinsic ID and IntrinsicTypes.
   void emitCodeGenSwitchBody(raw_ostream &o) const;
 
   // Emit the macros for mapping C/C++ intrinsic function to builtin functions.
   void emitIntrinsicMacro(raw_ostream &o) const;
 
   // Emit the mangled function definition.
-  void emitMangledFuncDef(raw_ostream &o) const;
+  void emitMangledFuncDef(raw_ostream &o, bool Overloaded) const;
+
+  // Emit marks used to limit the size of the header at testing time.
+  void emitTestingMarkStart(raw_ostream &o) const;
+  void emitTestingMarkEnd(raw_ostream &o) const;
 };
 
 class RVVEmitter {
 private:
   RecordKeeper &Records;
+  bool TestingHeader;
   std::string HeaderCode;
   // Concat BasicType, LMUL and Proto as key
   StringMap<RVVType> LegalTypes;
   StringSet<> IllegalTypes;
 
 public:
-  RVVEmitter(RecordKeeper &R) : Records(R) {}
+  RVVEmitter(RecordKeeper &R, bool TestingHeader = false)
+      : Records(R), TestingHeader(TestingHeader) {}
 
   /// Emit riscv_vector.h
   void createHeader(raw_ostream &o);
 
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.

 //===----------------------------------------------------------------------===//
 RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
                            StringRef NewMangledName, StringRef IRName,
                            bool HasSideEffects, bool IsMask,
                            bool HasMaskedOffOperand, bool HasVL,
                            bool HasNoMaskedOverloaded, bool HasAutoDef,
                            StringRef ManualCodegen, const RVVTypes &OutInTypes,
                            const std::vector<int64_t> &NewIntrinsicTypes,
-                           const std::vector<int64_t> &PermuteOperands)
+                           const std::vector<int64_t> &PermuteOperands,
+                           bool TestingHeader)
     : IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask),
       HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL),
       HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef),
-      ManualCodegen(ManualCodegen.str()) {
+      ManualCodegen(ManualCodegen.str()), TestingHeader(TestingHeader)  {
 
   // Init Name and MangledName
   Name = NewName.str();
   if (NewMangledName.empty())
     MangledName = NewName.split("_").first.str();
   else
     MangledName = NewMangledName.str();
   if (!Suffix.empty())
     Name += "_" + Suffix.str();
   if (IsMask) {
void RVVIntrinsic::emitCodeGenSwitchBody(raw_ostream &OS) const {
   // VL could be i64 or i32, need to encode it in IntrinsicTypes. VL is
   // always last operand.
   if (hasVL())
     OS << ", Ops[" << getNumOperand() - 1 << "]->getType()";
   OS << "};\n";
   OS << "  break;\n";
 }
 
+void RVVIntrinsic::emitTestingMarkStart(raw_ostream &OS) const {
+  if (TestingHeader) {
+    OS << "#if defined(RVV_TEST_" << IRName << ")\n";
+  }
+}
+
+void RVVIntrinsic::emitTestingMarkEnd(raw_ostream &OS) const {
+  if (TestingHeader) {
+    OS << "#endif // RVV_TEST_" << IRName << "\n";
+  }
+}
+
 void RVVIntrinsic::emitIntrinsicMacro(raw_ostream &OS) const {
+  emitTestingMarkStart(OS);
   OS << "#define " << getName() << "(";
   if (getNumOperand() > 0) {
     ListSeparator LS;
     for (const auto &I : CTypeOrder)
       OS << LS << "op" << I;
   }
   OS << ") \\\n";
   OS << "__builtin_rvv_" << getName() << "(";
   if (getNumOperand() > 0) {
     ListSeparator LS;
     for (unsigned i = 0; i < InputTypes.size(); ++i)
       OS << LS << "(" << InputTypes[i]->getTypeStr() << ")(op" << i << ")";
   }
   OS << ")\n";
+  emitTestingMarkEnd(OS);
+
 }
 
-void RVVIntrinsic::emitMangledFuncDef(raw_ostream &OS) const {
+void RVVIntrinsic::emitMangledFuncDef(raw_ostream &OS, bool Overloaded) const {
+  emitTestingMarkStart(OS);
+  if (Overloaded)
+    OS << "__rvv_overloaded ";
   OS << OutputType->getTypeStr() << " " << getMangledName() << "(";
   // Emit function arguments
   if (getNumOperand() > 0) {
     ListSeparator LS;
     for (unsigned i = 0; i < CTypeOrder.size(); ++i)
       OS << LS << InputTypes[CTypeOrder[i]]->getTypeStr() << " op" << i;
   }
   OS << "){\n";
   OS << "  return " << getName() << "(";
   // Emit parameter variables
   if (getNumOperand() > 0) {
     ListSeparator LS;
     for (unsigned i = 0; i < CTypeOrder.size(); ++i)
       OS << LS << "op" << i;
   }
   OS << ");\n";
-  OS << "}\n\n";
+  OS << "}\n";
+  emitTestingMarkEnd(OS);
+  OS << "\n";
 }
 
 //===----------------------------------------------------------------------===//
 // RVVEmitter implementation
 //===----------------------------------------------------------------------===//
 void RVVEmitter::createHeader(raw_ostream &OS) {
 
   OS << "/*===---- riscv_vector.h - RISC-V V-extension RVVIntrinsics "
void RVVEmitter::createHeader(raw_ostream &OS) {
 
   // Print Overloaded APIs
   OS << "#define __rvv_overloaded static inline "
         "__attribute__((__always_inline__, __nodebug__, __overloadable__))\n";
 
   emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
     if (!Inst.isMask() && !Inst.hasNoMaskedOverloaded())
       return;
-    OS << "__rvv_overloaded ";
-    Inst.emitMangledFuncDef(OS);
+    Inst.emitMangledFuncDef(OS, /* Overloaded = */ true);
   });
 
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
   OS << "#endif // __riscv_vector\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }
 
for (char I : TypeRange) {
           continue;
 
         auto SuffixStr = getSuffixStr(I, Log2LMUL, SuffixProto);
         // Create a non-mask intrinsic
         Out.push_back(std::make_unique<RVVIntrinsic>(
             Name, SuffixStr, MangledName, IRName, HasSideEffects,
             /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
             HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, Types.getValue(),
-            IntrinsicTypes, PermuteOperands));
+            IntrinsicTypes, PermuteOperands, TestingHeader));
         if (HasMask) {
           // Create a mask intrinsic
           Optional<RVVTypes> MaskTypes =
               computeTypes(I, Log2LMUL, ProtoMaskSeq);
           Out.push_back(std::make_unique<RVVIntrinsic>(
               Name, SuffixStr, MangledName, IRNameMask, HasSideEffects,
               /*IsMask=*/true, HasMaskedOffOperand, HasVL,
               HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask,
-              MaskTypes.getValue(), IntrinsicTypes, PermuteOperands));
+              MaskTypes.getValue(), IntrinsicTypes, PermuteOperands,
+              TestingHeader));
         }
       } // end for Log2LMULList
     }   // end for TypeRange
   }
 }
 
 Optional<RVVTypes>
 RVVEmitter::computeTypes(BasicType BT, int Log2LMUL,
bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
   return true;
 }
 
 namespace clang {
 void EmitRVVHeader(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createHeader(OS);
 }
 
+void EmitRVVTestingHeader(RecordKeeper &Records, raw_ostream &OS) {
+  RVVEmitter(Records, /*TestingHeader=*/ true).createHeader(OS);
+}
+
 void EmitRVVBuiltins(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createBuiltins(OS);
 }
 
 void EmitRVVBuiltinCG(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createCodeGen(OS);
 }
 
 } // End namespace clang

clang/utils/TableGen/TableGen.cpp

enum ActionType {
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
   GenArmCdeBuiltinCG,
   GenArmCdeBuiltinAliases,
   GenRISCVVectorHeader,
+  GenRISCVVectorTestingHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
   GenDataCollectors,
   GenTestPragmaAttributeSupportedAttributes
 };
cl::values(
         clEnumValN(GenArmCdeBuiltinSema, "gen-arm-cde-builtin-sema",
                    "Generate ARM CDE builtin sema checks for clang"),
         clEnumValN(GenArmCdeBuiltinCG, "gen-arm-cde-builtin-codegen",
                    "Generate ARM CDE builtin code-generator for clang"),
         clEnumValN(GenArmCdeBuiltinAliases, "gen-arm-cde-builtin-aliases",
                    "Generate list of valid ARM CDE builtin aliases for clang"),
         clEnumValN(GenRISCVVectorHeader, "gen-riscv-vector-header",
                    "Generate riscv_vector.h for clang"),
+        clEnumValN(GenRISCVVectorTestingHeader,
+                   "gen-riscv-vector-testing-header",
+                   "Generate riscv_vector_testing.h for testing clang"),
         clEnumValN(GenRISCVVectorBuiltins, "gen-riscv-vector-builtins",
                    "Generate riscv_vector_builtins.inc for clang"),
         clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
                    "Generate riscv_vector_builtin_cg.inc for clang"),
         clEnumValN(GenAttrDocs, "gen-attr-docs",
                    "Generate attribute documentation"),
         clEnumValN(GenDiagDocs, "gen-diag-docs",
                    "Generate diagnostic documentation"),
case GenArmCdeBuiltinCG:
     EmitCdeBuiltinCG(Records, OS);
     break;
   case GenArmCdeBuiltinAliases:
     EmitCdeBuiltinAliases(Records, OS);
     break;
   case GenRISCVVectorHeader:
     EmitRVVHeader(Records, OS);
     break;
+  case GenRISCVVectorTestingHeader:
+    EmitRVVTestingHeader(Records, OS);
+    break;
   case GenRISCVVectorBuiltins:
     EmitRVVBuiltins(Records, OS);
     break;
   case GenRISCVVectorBuiltinCG:
     EmitRVVBuiltinCG(Records, OS);
     break;
   case GenAttrDocs:
     EmitClangAttrDocs(Records, OS);

clang/utils/TableGen/TableGenBackends.h

 
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinAliases(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVTestingHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinAliases(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);