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[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

Authored by craig.topper on Tue, Apr 13, 4:17 PM.



This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

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craig.topper created this revision.Tue, Apr 13, 4:17 PM
craig.topper requested review of this revision.Tue, Apr 13, 4:17 PM
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frasercrmck accepted this revision.Thu, Apr 15, 2:02 AM

Seems like a decent cleanup to me.


So this was a 6-bit field even though the instruction only takes 4/5 bits through shfl_uimm?

This revision is now accepted and ready to land.Thu, Apr 15, 2:02 AM
craig.topper added inline comments.Thu, Apr 15, 11:10 AM

Yeah. Maybe it was trying to cover for RV128 because that's how the spec is written. But the other shifts just put a 0 where the extra bit of shift amount goes so if it was it wasn't consistent.