[AIX][TLS] Add support for TLSGD relocations to XCOFF objects

[NeHuang]

Summary

This patch adds support for TLSGD relocations to XCOFF objects:

• Add branch absolute reloction R_RBA, R_TLS relocation for the variable offset for the tlsgd model and R_TLSM for the region handle for the tlsgd model
• Properly set the relocation fixed values for R_TLS and R_TLSM
• Emit the TCEntry with the variant kind in the XCOFFStreamer

[DiggerLin]

llvm/lib/MC/MCELFStreamer.cpp

462 ↗

(On Diff #336502)

the patch is for aix , why there is changed on the MCELFStreamer.cpp ?

[NeHuang]

Address the review comments to remove unnecessary changes for ELF.

[sfertile]

Patch looks pretty good. IIUC we were not printing the '@gd' specifier before because it is assumed by default by the system assembler. Now that we are adding object file support we can no longer rely of the system assembler to assume the specifier based on the storage mapping class ,and need to add the new variant kinds so we create the correct relocations, which has the side effect of also changing the asm we emit. I know I am being pedantic, but I think we should land that part of the change and the update to the asm test in an initial patch even though the object writing is the motivation for adding it.

llvm/lib/Target/PowerPC/PPC.h

132

Can we keep using the MO_TLSGD_FLAG for this, and differentiate based on checking that the system is AIX?

[nemanjai]

In D100214#2701875, @sfertile wrote:

Patch looks pretty good. IIUC we were not printing the '@gd' specifier before because it is assumed by default by the system assembler. Now that we are adding object file support we can no longer rely of the system assembler to assume the specifier based on the storage mapping class ,and need to add the new variant kinds so we create the correct relocations, which has the side effect of also changing the asm we emit. I know I am being pedantic, but I think we should land that part of the change and the update to the asm test in an initial patch even though the object writing is the motivation for adding it.

I agree, lets split out the ASM portion from the object code portion.

[NeHuang]

Address review comments to

• Split into two patches: ASM portion: https://reviews.llvm.org/D100956 Object portion: this patch
• Keep using MO_TLSGD_FLAG for the variable offset of AIX TLS GD model, added MO_TLSGDM_FLAG for the region handle of AIX TLS GD model. Changes in https://reviews.llvm.org/D100956

[sfertile]

llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll

527

I don't know if we have decided on any formatting guidelines for these types of tests so that we have a consistent feel across all the tests in the back end, but if we have let me know and we can ignore this comment.

I think for this output here, the only important part is the instruction, while the instructions that have relocations the important part also includes the instructions address. From that I think should have lit checks along the lines of the following:

DIS:              virt-addr (idx: N)    Label:
DIS-NEXT:                                  Instr operands
...
DIS-NEXT:    virt-addr:  {{.*}}     Instr operands
DIS-NEXT:    virt-addr: Reloc (idx: M) Sym_Name
...

where we include the virtual address on labels, instructions that are referenced by relocations, and the relocations themselves. In the instructions that are referenced by relocations we need to add a regex to consume the raw data, but in the other instructions we just ignore everything preceding the instruction mnemonic.

576

When we get to the data section, whats important has flipped and the virtual address and the contents of memory is important, while the text that comes after the memory contents typically isn't important (in fact its typically misleading 😆) and so I think we should drop the text following the raw data.

A minor nit: FWIW I think we should try to align the contents of the checks also. eg:

DIS:            00000090 (idx: 11) storesTIInit[DS]:
DIS-NEXT:               90: 00 00 00 00
DIS-NEXT: 00000090: R_POS  (idx: 5) .storesTIInit
...

[NeHuang]

Addressed review comments

• Check the important contents in the test case
• Use regex to check the instructions referened by reloctions
• Fix the alignment

[sfertile]

Thanks for the updates Victor, LGTM.

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_DTPREL_HI,   // symbol@got@dtprel@h
     VK_PPC_GOT_DTPREL_HA,   // symbol@got@dtprel@ha
     VK_PPC_TLS,             // symbol@tls
     VK_PPC_GOT_TLSGD,       // symbol@got@tlsgd
     VK_PPC_GOT_TLSGD_LO,    // symbol@got@tlsgd@l
     VK_PPC_GOT_TLSGD_HI,    // symbol@got@tlsgd@h
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
+    VK_PPC_AIX_TLSGD,       // symbol@gd
+    VK_PPC_AIX_TLSGDM,      // symbol@m
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
     VK_PPC_GOT_TLSGD_PCREL, // symbol@got@tlsgd@pcrel
     VK_PPC_GOT_TLSLD_PCREL, // symbol@got@tlsld@pcrel
     VK_PPC_GOT_TPREL_PCREL, // symbol@got@tprel@pcrel

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_DTPREL_HI: return "got@dtprel@h";
   case VK_PPC_GOT_DTPREL_HA: return "got@dtprel@ha";
   case VK_PPC_TLS: return "tls";
   case VK_PPC_GOT_TLSGD: return "got@tlsgd";
   case VK_PPC_GOT_TLSGD_LO: return "got@tlsgd@l";
   case VK_PPC_GOT_TLSGD_HI: return "got@tlsgd@h";
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
+  case VK_PPC_AIX_TLSGD:
+    return "gd";
+  case VK_PPC_AIX_TLSGDM:
+    return "m";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
   case VK_PPC_GOT_TLSGD_PCREL:
     return "got@tlsgd@pcrel";

llvm/lib/MC/XCOFFObjectWriter.cpp

void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm,
   std::tie(Type, SignAndSize) =
       TargetObjectWriter->getRelocTypeAndSignSize(Target, Fixup, IsPCRel);
 
   const MCSectionXCOFF *SymASec = getContainingCsect(cast<MCSymbolXCOFF>(SymA));
   assert(SectionMap.find(SymASec) != SectionMap.end() &&
          "Expected containing csect to exist in map.");
 
   const uint32_t Index = getIndex(SymA, SymASec);
-  if (Type == XCOFF::RelocationType::R_POS)
+  if (Type == XCOFF::RelocationType::R_POS ||
+      Type == XCOFF::RelocationType::R_TLS)
     // The FixedValue should be symbol's virtual address in this object file
     // plus any constant value that we might get.
     FixedValue = getVirtualAddress(SymA, SymASec) + Target.getConstant();
+  else if (Type == XCOFF::RelocationType::R_TLSM)
+    // The FixedValue should always be zero since the region handle is only
+    // known at load time.
+    FixedValue = 0;
   else if (Type == XCOFF::RelocationType::R_TOC ||
            Type == XCOFF::RelocationType::R_TOCL) {
     // The FixedValue should be the TOC entry offset from the TOC-base plus any
     // constant offset value.
     const int64_t TOCEntryOffset = SectionMap[SymASec]->Address -
                                    TOCCsects.front().Address +
                                    Target.getConstant();
     if (Type == XCOFF::RelocationType::R_TOC && !isInt<16>(TOCEntryOffset))

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
       : PPCTargetStreamer(S), OS(OS) {}
 
   void emitTCEntry(const MCSymbol &S,
                    MCSymbolRefExpr::VariantKind Kind) override {
     if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(&S)) {
       MCSymbolXCOFF *TCSym =
           cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
               ->getQualNameSymbol();
-      // If the variant kind is TLSGD the entry represents the region handle for
-      // the symbol, we prefix the name with a dot and we add the @m
-      // relocation specifier.
-      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD)
-        OS << "\t.tc ." << TCSym->getName() << "," << XSym->getName() << "@m\n";
+      // If the variant kind is VK_PPC_AIX_TLSGDM/VK_PPC_AIX_TLSGD the entry
+      // represents the region handle/variable offset for the symbol, we add
+      // the relocation specifier @m/@gd.
+      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM ||
+          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD)
+        OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
+           << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
       else
         OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
 
       if (TCSym->hasRename())
         Streamer.emitXCOFFRenameDirective(TCSym, TCSym->getSymbolTableName());
       return;
     }
 

 public:
   PPCTargetXCOFFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
 
   void emitTCEntry(const MCSymbol &S,
                    MCSymbolRefExpr::VariantKind Kind) override {
     const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
     const unsigned PointerSize = MAI->getCodePointerSize();
     Streamer.emitValueToAlignment(PointerSize);
-    Streamer.emitSymbolValue(&S, PointerSize);
+    Streamer.emitValue(MCSymbolRefExpr::create(&S, Kind, Streamer.getContext()),
+                       PointerSize);
   }
 
   void emitMachine(StringRef CPU) override {
     llvm_unreachable("Machine pseudo-ops are invalid for XCOFF.");
   }
 
   void emitAbiVersion(int AbiVersion) override {
     llvm_unreachable("ABI-version pseudo-ops are invalid for XCOFF.");

llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

case PPC::fixup_ppc_half16: {
     case MCSymbolRefExpr::VK_PPC_L:
       return {XCOFF::RelocationType::R_TOCL, SignAndSizeForHalf16};
     }
   } break;
   case PPC::fixup_ppc_br24:
     // Branches are 4 byte aligned, so the 24 bits we encode in
     // the instruction actually represents a 26 bit offset.
     return {XCOFF::RelocationType::R_RBR, EncodedSignednessIndicator | 25};
+  case PPC::fixup_ppc_br24abs:
+    return {XCOFF::RelocationType::R_RBA, EncodedSignednessIndicator | 25};
   case FK_Data_4:
+    switch (Modifier) {
+    default:
+      report_fatal_error("Unsupported modifier");
+    case MCSymbolRefExpr::VK_PPC_AIX_TLSGD:
+      return {XCOFF::RelocationType::R_TLS, EncodedSignednessIndicator | 31};
+    case MCSymbolRefExpr::VK_PPC_AIX_TLSGDM:
+      return {XCOFF::RelocationType::R_TLSM, EncodedSignednessIndicator | 31};
+    case MCSymbolRefExpr::VK_None:
       return {XCOFF::RelocationType::R_POS, EncodedSignednessIndicator | 31};
     }
   }
+}

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Initial Exec model.
     MO_TPREL_FLAG = 64,
 
     /// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Local Dynamic model.
     MO_TLSLD_FLAG = 128,
 
+    /// MO_AIX_TLSGD_FLAG - If this bit is set the symbol reference is relative
+    /// to the variable offset of AIX TLS General Dynamic model.
+    MO_AIX_TLSGD_FLAG = 256,
+
+    /// MO_AIX_TLSGDM_FLAG - If this bit is set the symbol reference is relative
+    /// to the region handle of AIX TLS General Dynamic model.
+    MO_AIX_TLSGDM_FLAG = 512,
+
     /// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tlsgd@pcrel.
     /// Fix up is VK_PPC_GOT_TLSGD_PCREL
     MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
 
     /// MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tlsld@pcrel.
     /// Fix up is VK_PPC_GOT_TLSLD_PCREL

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

if (Subtarget->isAIXABI()) {
     // should already be in R3.
     // For TLSGD, which currently is the only supported access model, we only
     // need to generate an absolute branch to .__tls_get_addr.
     Register VarOffsetReg = Subtarget->isPPC64() ? PPC::X4 : PPC::R4;
     (void)VarOffsetReg;
     assert(MI->getOperand(2).isReg() &&
            MI->getOperand(2).getReg() == VarOffsetReg &&
            "GETtls[ld]ADDR[32] must read GPR4");
-    MCSymbol *TlsGetAddrA = OutContext.getOrCreateSymbol(Name);
+    MCSymbol *TlsGetAddrA =
+        OutContext
+            .getXCOFFSection(
+                Name, SectionKind::getText(),
+                XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+            ->getQualNameSymbol();
     const MCExpr *TlsRef = MCSymbolRefExpr::create(
         TlsGetAddrA, MCSymbolRefExpr::VK_None, OutContext);
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BLA).addExpr(TlsRef));
     return;
   }
 
   if (Subtarget->is32BitELFABI() && isPositionIndependent())
     Kind = MCSymbolRefExpr::VK_PLT;
auto getTOCEntryLoadingExprForXCOFF =
 
     if (EntryDistanceFromTOCBase > PositiveTOCRange)
       return getTOCRelocAdjustedExprForXCOFF(Expr, EntryDistanceFromTOCBase);
 
     return Expr;
   };
   auto GetVKForMO = [&](const MachineOperand &MO) {
     // For GD TLS access on AIX, we have two TOC entries for the symbol (one for
-    // the offset and the other for the region handle). They are differentiated
-    // by the presence of the PPCII::MO_TLSGD_FLAG.
-    if (IsAIX && (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG))
-      return MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD;
+    // the variable offset and the other for the region handle). They are
+    // differentiated by MO_AIX_TLSGD_FLAG and MO_AIX_TLSGDM_FLAG.
+    if (MO.getTargetFlags() & PPCII::MO_AIX_TLSGDM_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
+    if (MO.getTargetFlags() & PPCII::MO_AIX_TLSGD_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
     return MCSymbolRefExpr::VariantKind::VK_None;
   };
 
   // Lower multi-instruction pseudo operations.
   switch (MI->getOpcode()) {
   default: break;
   case TargetOpcode::DBG_VALUE:
     llvm_unreachable("Should be handled target independently");
void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
 
   // Switch to section to emit TOC base.
   OutStreamer->SwitchSection(getObjFileLowering().getTOCBaseSection());
 
   PPCTargetStreamer *TS =
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
 
   for (auto &I : TOC) {
-    // Setup the csect for the current TC entry.
-    MCSectionXCOFF *TCEntry = cast<MCSectionXCOFF>(
+    MCSectionXCOFF *TCEntry;
+    // Setup the csect for the current TC entry. If the variant kind is
+    // VK_PPC_AIX_TLSGDM the entry represents the region handle, we create a
+    // new symbol to prefix the name with a dot.
+    if (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM) {
+      SmallString<128> Name;
+      StringRef Prefix = ".";
+      Name += Prefix;
+      Name += I.first.first->getName();
+      MCSymbol *S = OutContext.getOrCreateSymbol(Name);
+      TCEntry = cast<MCSectionXCOFF>(
+          getObjFileLowering().getSectionForTOCEntry(S, TM));
+    } else {
+      TCEntry = cast<MCSectionXCOFF>(
           getObjFileLowering().getSectionForTOCEntry(I.first.first, TM));
+    }
     OutStreamer->SwitchSection(TCEntry);
 
     OutStreamer->emitLabel(I.second);
     if (TS != nullptr)
       TS->emitTCEntry(*I.first.first, I.first.second);
   }
 }
 

 void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default:
     break;
   case PPC::GETtlsADDR64AIX:
   case PPC::GETtlsADDR32AIX: {
     // The reference to .__tls_get_addr is unknown to the assembler
     // so we need to emit an external symbol reference.
-    MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(".__tls_get_addr");
+    MCSymbol *TlsGetAddr =
+        OutContext
+            .getXCOFFSection(
+                ".__tls_get_addr", SectionKind::getText(),
+                XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+            ->getQualNameSymbol();
     ExtSymSDNodeSymbols.insert(TlsGetAddr);
     break;
   }
   case PPC::BL8:
   case PPC::BL:
   case PPC::BL8_NOP:
   case PPC::BL_NOP: {
     const MachineOperand &MO = MI->getOperand(0);

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   SDLoc dl(GA);
   const GlobalValue *GV = GA->getGlobal();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
   // The general-dynamic model is the only access model supported for now, so
   // all the GlobalTLSAddress nodes are lowered with this model.
   // We need to generate two TOC entries, one for the variable offset, one for
   // the region handle. The global address for the TOC entry of the region
-  // handle is created with the MO_TLSGD_FLAG flag so we can easily identify
-  // this entry and add the right relocation.
-  SDValue VariableOffsetTGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
+  // handle is created with the MO_AIX_TLSGDM_FLAG flag and the global address
+  // for the TOC entry of the variable offset is created with MO_AIX_TLSGD_FLAG.
+  SDValue VariableOffsetTGA =
+      DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_AIX_TLSGD_FLAG);
   SDValue RegionHandleTGA =
-      DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
+      DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_AIX_TLSGDM_FLAG);
   SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
   SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
   return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
                      RegionHandle);
 }
 
 SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
                                                       SelectionDAG &DAG) const {

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
       {MO_GOT_FLAG, "ppc-got"},
       {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
       {MO_TLSGD_FLAG, "ppc-tlsgd"},
       {MO_TLSLD_FLAG, "ppc-tlsld"},
       {MO_TPREL_FLAG, "ppc-tprel"},
+      {MO_AIX_TLSGD_FLAG, "ppc-aix-gd"},
+      {MO_AIX_TLSGDM_FLAG, "ppc-aix-m"},
       {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
       {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
       {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas

llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll

 }
 
 ; TOC entry checks
 
 ; SMALL32-LABEL:  .toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:   .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:   .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:   .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL:  .toc
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:   .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:   .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:   .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:   .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:   .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll

 }
 
 ; TOC entry checks
 
 ; SMALL32-LABEL: .toc
 ; SMALL32-LABEL: L..C0:
 ; SMALL32-NEXT:  .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL: L..C1:
-; SMALL32-NEXT:  .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:  .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL: L..C2:
 ; SMALL32-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL: L..C3:
-; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL: L..C4:
 ; SMALL32-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL: L..C5:
-; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL: L..C6:
 ; SMALL32-NEXT:  .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL32-LABEL: L..C7:
-; SMALL32-NEXT:  .tc TWUninit[TC],TWUninit[TL]
+; SMALL32-NEXT:  .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL32-LABEL: L..C8:
 ; SMALL32-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL: .toc
 ; LARGE32-LABEL: L..C0:
 ; LARGE32-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL: L..C1:
-; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL: L..C2:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL: L..C3:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL: L..C4:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL: L..C5:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL: L..C6:
 ; LARGE32-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE32-LABEL: L..C7:
-; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE32-LABEL: L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:   .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:   .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]
+; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:   .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll

 }
 
 ; TOC entry checks
 
 ; SMALL32-LABEL:  .toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL:  .toc
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
+; RUN: llvm-readobj -t %t.o | FileCheck --check-prefix=SYM %s
+; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
+
+@GInit = global double 1.000000e+00, align 8
+@TIInit = internal thread_local global i64 1, align 8
+@TWInit = weak thread_local global double 1.000000e+00, align 8
+
+; Function Attrs: nofree norecurse nounwind willreturn writeonly
+define void @storesTIInit(i64 %Val) #0 {
+entry:
+  store i64 %Val, i64* @TIInit, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind readonly willreturn
+define double @loadsTWInit() #1 {
+entry:
+  %0 = load double, double* @TWInit, align 8
+  %1 = load double, double* @GInit, align 8
+  %add = fadd double %0, %1
+  ret double %add
+}
+
+; RELOC:      File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o
+; RELOC-NEXT: Format: aixcoff-rs6000
+; RELOC-NEXT: Arch: powerpc
+; RELOC-NEXT: AddressSize: 32bit
+; RELOC-NEXT: Relocations [
+; RELOC-NEXT:   Section (index: 1) .text {
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x16
+; RELOC-NEXT:     Symbol: .TIInit (17)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x1A
+; RELOC-NEXT:     Symbol: TIInit (19)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x1E
+; RELOC-NEXT:     Symbol: .TIInit (17)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x22
+; RELOC-NEXT:     Symbol: TIInit (19)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x24
+; RELOC-NEXT:     Symbol: .__tls_get_addr (1)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 26
+; RELOC-NEXT:     Type: R_RBA (0x18)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x4E
+; RELOC-NEXT:     Symbol: .TWInit (21)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x52
+; RELOC-NEXT:     Symbol: TWInit (23)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x56
+; RELOC-NEXT:     Symbol: .TWInit (21)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x5A
+; RELOC-NEXT:     Symbol: TWInit (23)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x5C
+; RELOC-NEXT:     Symbol: .__tls_get_addr (1)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 26
+; RELOC-NEXT:     Type: R_RBA (0x18)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x66
+; RELOC-NEXT:     Symbol: GInit (25)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x6A
+; RELOC-NEXT:     Symbol: GInit (25)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT: }
+; RELOC-NEXT: Section (index: 2) .data {
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x90
+; RELOC-NEXT:   Symbol: .storesTIInit (5)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x94
+; RELOC-NEXT:   Symbol: TOC (15)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x9C
+; RELOC-NEXT:   Symbol: .loadsTWInit (7)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xA0
+; RELOC-NEXT:   Symbol: TOC (15)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xA8
+; RELOC-NEXT:   Symbol: TIInit (27)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLSM (0x24)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xAC
+; RELOC-NEXT:   Symbol: TIInit (27)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLS (0x20)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xB0
+; RELOC-NEXT:   Symbol: TWInit (29)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLSM (0x24)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xB4
+; RELOC-NEXT:   Symbol: TWInit (29)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLS (0x20)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0xB8
+; RELOC-NEXT:   Symbol: GInit (9)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: }
+; RELOC-NEXT: ]
+
+; SYM:      File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o
+; SYM-NEXT: Format: aixcoff-rs6000
+; SYM-NEXT: Arch: powerpc
+; SYM-NEXT: AddressSize: 32bit
+; SYM-NEXT: Symbols [
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 0
+; SYM-NEXT:     Name: .file
+; SYM-NEXT:     Value (SymbolTableIndex): 0x0
+; SYM-NEXT:     Section: N_DEBUG
+; SYM-NEXT:     Source Language ID: TB_C (0x0)
+; SYM-NEXT:     CPU Version ID: 0x0
+; SYM-NEXT:     StorageClass: C_FILE (0x67)
+; SYM-NEXT:     NumberOfAuxEntries: 0
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 1
+; SYM-NEXT:     Name: .__tls_get_addr
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: N_UNDEF
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 2
+; SYM-NEXT:       SectionLen: 0
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_ER (0x0)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 3
+; SYM-NEXT:     Name: .text
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 4
+; SYM-NEXT:       SectionLen: 132
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 4
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 5
+; SYM-NEXT:     Name: .storesTIInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 6
+; SYM-NEXT:       ContainingCsectSymbolIndex: 3
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 7
+; SYM-NEXT:     Name: .loadsTWInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x40
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 8
+; SYM-NEXT:       ContainingCsectSymbolIndex: 3
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 9
+; SYM-NEXT:     Name: GInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x88
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 10
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_RW (0x5)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 11
+; SYM-NEXT:     Name: storesTIInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x90
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 12
+; SYM-NEXT:       SectionLen: 12
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 13
+; SYM-NEXT:     Name: loadsTWInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x9C
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 14
+; SYM-NEXT:       SectionLen: 12
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 15
+; SYM-NEXT:     Name: TOC
+; SYM-NEXT:     Value (RelocatableAddress): 0xA8
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 16
+; SYM-NEXT:       SectionLen: 0
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC0 (0xF)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 17
+; SYM-NEXT:     Name: .TIInit
+; SYM-NEXT:     Value (RelocatableAddress): 0xA8
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 18
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 19
+; SYM-NEXT:     Name: TIInit
+; SYM-NEXT:     Value (RelocatableAddress): 0xAC
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 20
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 21
+; SYM-NEXT:     Name: .TWInit
+; SYM-NEXT:     Value (RelocatableAddress): 0xB0
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 22
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 23
+; SYM-NEXT:     Name: TWInit
+; SYM-NEXT:     Value (RelocatableAddress): 0xB4
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 24
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 25
+; SYM-NEXT:     Name: GInit
+; SYM-NEXT:     Value (RelocatableAddress): 0xB8
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 26
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 27
+; SYM-NEXT:     Name: TIInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 28
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 29
+; SYM-NEXT:     Name: TWInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x8
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_WEAKEXT (0x6F)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 30
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT: ]
+
+; DIS:      {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o: file format aixcoff-rs6000
+; DIS:      Disassembly of section .text:
+; DIS:      00000000 (idx: 5) .storesTIInit:
+; DIS-NEXT:        0: 7c 08 02 a6   mflr 0
+; DIS-NEXT:        4: 90 01 00 08   stw 0, 8(1)
+; DIS-NEXT:        8: 94 21 ff e0   stwu 1, -32(1)
+; DIS-NEXT:        c: 7c 86 23 78   mr  6, 4
+; DIS-NEXT:       10: 7c 67 1b 78   mr  7, 3
+; DIS-NEXT:       14: 3c 62 00 00   addis 3, 2, 0
+; DIS-NEXT:       00000016:  R_TOCU (idx: 17) .TIInit[TE]
+; DIS-NEXT:       18: 3c 82 00 00   addis 4, 2, 0
+; DIS-NEXT:       0000001a:  R_TOCU (idx: 19) TIInit[TE]
+; DIS-NEXT:       1c: 80 63 00 00   lwz 3, 0(3)
+; DIS-NEXT:       0000001e:  R_TOCL (idx: 17) .TIInit[TE]
+; DIS-NEXT:       20: 80 84 00 04   lwz 4, 4(4)
+; DIS-NEXT:       00000022:  R_TOCL (idx: 19) TIInit[TE]
+; DIS-NEXT:       24: 48 00 00 03   bla 0
+; DIS-NEXT:       00000024:  R_RBA  (idx: 1) .__tls_get_addr[PR]
+; DIS-NEXT:       28: 90 c3 00 04   stw 6, 4(3)
+; DIS-NEXT:       2c: 90 e3 00 00   stw 7, 0(3)
+; DIS-NEXT:       30: 38 21 00 20   addi 1, 1, 32
+; DIS-NEXT:       34: 80 01 00 08   lwz 0, 8(1)
+; DIS-NEXT:       38: 7c 08 03 a6   mtlr 0
+; DIS-NEXT:       3c: 4e 80 00 20   blr
+; DIS:      00000040 (idx: 7) .loadsTWInit:
+; DIS-NEXT:       40: 7c 08 02 a6   mflr 0
+; DIS-NEXT:       44: 90 01 00 08   stw 0, 8(1)
+; DIS-NEXT:       48: 94 21 ff e0   stwu 1, -32(1)
+; DIS-NEXT:       4c: 3c 62 00 00   addis 3, 2, 0
+; DIS-NEXT:       0000004e:  R_TOCU (idx: 21) .TWInit[TE]
+; DIS-NEXT:       50: 3c 82 00 00   addis 4, 2, 0
+; DIS-NEXT:       00000052:  R_TOCU (idx: 23) TWInit[TE]
+; DIS-NEXT:       54: 80 63 00 08   lwz 3, 8(3)
+; DIS-NEXT:       00000056:  R_TOCL (idx: 21) .TWInit[TE]
+; DIS-NEXT:       58: 80 84 00 0c   lwz 4, 12(4)
+; DIS-NEXT:       0000005a:  R_TOCL (idx: 23) TWInit[TE]
+; DIS-NEXT:       5c: 48 00 00 03   bla 0
+; DIS-NEXT:       0000005c:  R_RBA  (idx: 1) .__tls_get_addr[PR]
+; DIS-NEXT:       60: c8 03 00 00   lfd 0, 0(3)
+; DIS-NEXT:       64: 3c 62 00 00   addis 3, 2, 0
+; DIS-NEXT:       00000066:  R_TOCU (idx: 25) GInit[TE]
+; DIS-NEXT:       68: 80 63 00 10   lwz 3, 16(3)
+; DIS-NEXT:       0000006a:  R_TOCL (idx: 25) GInit[TE]
+; DIS-NEXT:       6c: c8 23 00 00   lfd 1, 0(3)
+; DIS-NEXT:       70: fc 20 08 2a   fadd 1, 0, 1
+; DIS-NEXT:       74: 38 21 00 20   addi 1, 1, 32
+; DIS-NEXT:       78: 80 01 00 08   lwz 0, 8(1)
+; DIS-NEXT:       7c: 7c 08 03 a6   mtlr 0
+; DIS-NEXT:       80: 4e 80 00 20   blr
+
+; DIS:      Disassembly of section .data:
+; DIS:      00000088 (idx: 9) GInit[RW]:
+; DIS-NEXT:       88: 3f f0 00 00   addis 31, 16, 0
+; DIS-NEXT:       8c: 00 00 00 00   <unknown>
+; DIS:      00000090 (idx: 11) storesTIInit[DS]:
+; DIS-NEXT:       90: 00 00 00 00   <unknown>
+; DIS-NEXT:       00000090:  R_POS  (idx: 5) .storesTIInit
+; DIS-NEXT:       94: 00 00 00 a8   <unknown>
+; DIS-NEXT:       00000094:  R_POS  (idx: 15) TOC[TC0]
+; DIS-NEXT:       98: 00 00 00 00   <unknown>
+; DIS:      0000009c (idx: 13) loadsTWInit[DS]:
+; DIS-NEXT:       9c: 00 00 00 40   <unknown>
+; DIS-NEXT:       0000009c:  R_POS  (idx: 7) .loadsTWInit
+; DIS-NEXT:       a0: 00 00 00 a8   <unknown>
+; DIS-NEXT:       000000a0:  R_POS  (idx: 15) TOC[TC0]
+; DIS-NEXT:       a4: 00 00 00 00   <unknown>
+; DIS:      000000a8 (idx: 17) .TIInit[TE]:
+; DIS-NEXT:       a8: 00 00 00 00   <unknown>
+; DIS-NEXT:       000000a8:  R_TLSM (idx: 27) TIInit[TL]
+; DIS:      000000ac (idx: 19) TIInit[TE]:
+; DIS-NEXT:       ac: 00 00 00 00   <unknown>
+; DIS-NEXT:       000000ac:  R_TLS  (idx: 27) TIInit[TL]
+; DIS:      000000b0 (idx: 21) .TWInit[TE]:
+; DIS-NEXT:       b0: 00 00 00 00   <unknown>
+; DIS-NEXT:       000000b0:  R_TLSM (idx: 29) TWInit[TL]
+; DIS:      000000b4 (idx: 23) TWInit[TE]:
+; DIS-NEXT:       b4: 00 00 00 08   <unknown>
+; DIS-NEXT:       000000b4:  R_TLS  (idx: 29) TWInit[TL]
+; DIS:      000000b8 (idx: 25) GInit[TE]:
+; DIS-NEXT:       b8: 00 00 00 88   <unknown>
+; DIS-NEXT:       000000b8:  R_POS  (idx: 9) GInit[RW]
+
+; DIS:      Disassembly of section .tdata:
+; DIS:      00000000 (idx: 27) TIInit[TL]:
+; DIS-NEXT:        0: 00 00 00 00   <unknown>
+; DIS-NEXT:        4: 00 00 00 01   <unknown>
+; DIS:      00000008 (idx: 29) TWInit[TL]:
+; DIS-NEXT:        8: 3f f0 00 00   addis 31, 16, 0
+; DIS-NEXT:        c: 00 00 00 00   <unknown>
+
+attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
+attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
+; RUN: llvm-readobj -t %t.o | FileCheck --check-prefix=SYM %s
+; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
+
+@const_ivar = constant i32 6, align 4
+@GInit = global i32 1, align 4
+@TGInit = thread_local global i32 1, align 4
+@TIUninit = internal thread_local global i32 0, align 4
+
+; Function Attrs: nofree norecurse nounwind willreturn writeonly
+define void @storesTIUninit(i32 %Val) #0 {
+entry:
+  store i32 %Val, i32* @TIUninit, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind readonly willreturn
+define i32 @loadsTGInit() #1 {
+entry:
+  %0 = load i32, i32* @TGInit, align 4
+  %1 = load i32, i32* @GInit, align 4
+  %add = add nsw i32 %1, %0
+  ret i32 %add
+}
+
+; RELOC:      File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o
+; RELOC-NEXT: Format: aixcoff-rs6000
+; RELOC-NEXT: Arch: powerpc
+; RELOC-NEXT: AddressSize: 32bit
+; RELOC-NEXT: Relocations [
+; RELOC-NEXT:   Section (index: 1) .text {
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x12
+; RELOC-NEXT:     Symbol: .TIUninit (23)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOC (0x3)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x16
+; RELOC-NEXT:     Symbol: TIUninit (25)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOC (0x3)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x18
+; RELOC-NEXT:     Symbol: .__tls_get_addr (1)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 26
+; RELOC-NEXT:     Type: R_RBA (0x18)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x3E
+; RELOC-NEXT:     Symbol: .TGInit (27)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOC (0x3)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x42
+; RELOC-NEXT:     Symbol: TGInit (29)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOC (0x3)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x44
+; RELOC-NEXT:     Symbol: .__tls_get_addr (1)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 26
+; RELOC-NEXT:     Type: R_RBA (0x18)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x4A
+; RELOC-NEXT:     Symbol: GInit (31)
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOC (0x3)
+; RELOC-NEXT:   }
+; RELOC-NEXT: }
+; RELOC-NEXT: Section (index: 2) .data {
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x70
+; RELOC-NEXT:   Symbol: .storesTIUninit (5)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x74
+; RELOC-NEXT:   Symbol: TOC (21)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x7C
+; RELOC-NEXT:   Symbol: .loadsTGInit (7)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x80
+; RELOC-NEXT:   Symbol: TOC (21)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x88
+; RELOC-NEXT:   Symbol: TIUninit (37)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLSM (0x24)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x8C
+; RELOC-NEXT:   Symbol: TIUninit (37)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLS (0x20)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x90
+; RELOC-NEXT:   Symbol: TGInit (35)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLSM (0x24)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x94
+; RELOC-NEXT:   Symbol: TGInit (35)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_TLS (0x20)
+; RELOC-NEXT: }
+; RELOC-NEXT: Relocation {
+; RELOC-NEXT:   Virtual Address: 0x98
+; RELOC-NEXT:   Symbol: GInit (15)
+; RELOC-NEXT:   IsSigned: No
+; RELOC-NEXT:   FixupBitValue: 0
+; RELOC-NEXT:   Length: 32
+; RELOC-NEXT:   Type: R_POS (0x0)
+; RELOC-NEXT: }
+; RELOC-NEXT: }
+; RELOC-NEXT: ]
+
+; SYM:      File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o
+; SYM-NEXT: Format: aixcoff-rs6000
+; SYM-NEXT: Arch: powerpc
+; SYM-NEXT: AddressSize: 32bit
+; SYM-NEXT: Symbols [
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 0
+; SYM-NEXT:     Name: .file
+; SYM-NEXT:     Value (SymbolTableIndex): 0x0
+; SYM-NEXT:     Section: N_DEBUG
+; SYM-NEXT:     Source Language ID: TB_C (0x0)
+; SYM-NEXT:     CPU Version ID: 0x0
+; SYM-NEXT:     StorageClass: C_FILE (0x67)
+; SYM-NEXT:     NumberOfAuxEntries: 0
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 1
+; SYM-NEXT:     Name: .__tls_get_addr
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: N_UNDEF
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 2
+; SYM-NEXT:       SectionLen: 0
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_ER (0x0)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 3
+; SYM-NEXT:     Name: .text
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 4
+; SYM-NEXT:       SectionLen: 104
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 4
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 5
+; SYM-NEXT:     Name: .storesTIUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 6
+; SYM-NEXT:       ContainingCsectSymbolIndex: 3
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 7
+; SYM-NEXT:     Name: .loadsTGInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x30
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 8
+; SYM-NEXT:       ContainingCsectSymbolIndex: 3
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 9
+; SYM-NEXT:     Name: .rodata
+; SYM-NEXT:     Value (RelocatableAddress): 0x68
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 10
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_RO (0x1)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 11
+; SYM-NEXT:     Name: const_ivar
+; SYM-NEXT:     Value (RelocatableAddress): 0x68
+; SYM-NEXT:     Section: .text
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 12
+; SYM-NEXT:       ContainingCsectSymbolIndex: 9
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_RO (0x1)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 13
+; SYM-NEXT:     Name: .data
+; SYM-NEXT:     Value (RelocatableAddress): 0x6C
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 14
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_RW (0x5)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 15
+; SYM-NEXT:     Name: GInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x6C
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 16
+; SYM-NEXT:       ContainingCsectSymbolIndex: 13
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_RW (0x5)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 17
+; SYM-NEXT:     Name: storesTIUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x70
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 18
+; SYM-NEXT:       SectionLen: 12
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 19
+; SYM-NEXT:     Name: loadsTGInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x7C
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 20
+; SYM-NEXT:       SectionLen: 12
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_DS (0xA)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 21
+; SYM-NEXT:     Name: TOC
+; SYM-NEXT:     Value (RelocatableAddress): 0x88
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 22
+; SYM-NEXT:       SectionLen: 0
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC0 (0xF)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 23
+; SYM-NEXT:     Name: .TIUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x88
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 24
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 25
+; SYM-NEXT:     Name: TIUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x8C
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 26
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 27
+; SYM-NEXT:     Name: .TGInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x90
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 28
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 29
+; SYM-NEXT:     Name: TGInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x94
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 30
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 31
+; SYM-NEXT:     Name: GInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x98
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 32
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 33
+; SYM-NEXT:     Name: .tdata
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 34
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 35
+; SYM-NEXT:     Name: TGInit
+; SYM-NEXT:     Value (RelocatableAddress): 0x0
+; SYM-NEXT:     Section: .tdata
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_EXT (0x2)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 36
+; SYM-NEXT:       ContainingCsectSymbolIndex: 33
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 0
+; SYM-NEXT:       SymbolType: XTY_LD (0x2)
+; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT:   Symbol {
+; SYM-NEXT:     Index: 37
+; SYM-NEXT:     Name: TIUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x4
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 38
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM-NEXT: ]
+
+; DIS:      {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000
+; DIS:      Disassembly of section .text:
+; DIS:      00000000 (idx: 5) .storesTIUninit:
+; DIS-NEXT:        0: 7c 08 02 a6   mflr 0
+; DIS-NEXT:        4: 90 01 00 08   stw 0, 8(1)
+; DIS-NEXT:        8: 94 21 ff e0   stwu 1, -32(1)
+; DIS-NEXT:        c: 7c 66 1b 78   mr  6, 3
+; DIS-NEXT:       10: 80 62 00 00   lwz 3, 0(2)
+; DIS-NEXT:       00000012:  R_TOC  (idx: 23) .TIUninit[TC]
+; DIS-NEXT:       14: 80 82 00 04   lwz 4, 4(2)
+; DIS-NEXT:       00000016:  R_TOC  (idx: 25) TIUninit[TC]
+; DIS-NEXT:       18: 48 00 00 03   bla 0
+; DIS-NEXT:       00000018:  R_RBA  (idx: 1) .__tls_get_addr[PR]
+; DIS-NEXT:       1c: 90 c3 00 00   stw 6, 0(3)
+; DIS-NEXT:       20: 38 21 00 20   addi 1, 1, 32
+; DIS-NEXT:       24: 80 01 00 08   lwz 0, 8(1)
+; DIS-NEXT:       28: 7c 08 03 a6   mtlr 0
+; DIS-NEXT:       2c: 4e 80 00 20   blr
+; DIS:      00000030 (idx: 7) .loadsTGInit:
+; DIS-NEXT:       30: 7c 08 02 a6   mflr 0
+; DIS-NEXT:       34: 90 01 00 08   stw 0, 8(1)
+; DIS-NEXT:       38: 94 21 ff e0   stwu 1, -32(1)
+; DIS-NEXT:       3c: 80 62 00 08   lwz 3, 8(2)
+; DIS-NEXT:       0000003e:  R_TOC  (idx: 27) .TGInit[TC]
+; DIS-NEXT:       40: 80 82 00 0c   lwz 4, 12(2)
+; DIS-NEXT:       00000042:  R_TOC  (idx: 29) TGInit[TC]
+; DIS-NEXT:       44: 48 00 00 03   bla 0
+; DIS-NEXT:       00000044:  R_RBA  (idx: 1) .__tls_get_addr[PR]
+; DIS-NEXT:       48: 80 82 00 10   lwz 4, 16(2)
+; DIS-NEXT:       0000004a:  R_TOC  (idx: 31) GInit[TC]
+; DIS-NEXT:       4c: 80 63 00 00   lwz 3, 0(3)
+; DIS-NEXT:       50: 80 84 00 00   lwz 4, 0(4)
+; DIS-NEXT:       54: 7c 64 1a 14   add 3, 4, 3
+; DIS-NEXT:       58: 38 21 00 20   addi 1, 1, 32
+; DIS-NEXT:       5c: 80 01 00 08   lwz 0, 8(1)
+; DIS-NEXT:       60: 7c 08 03 a6   mtlr 0
+; DIS-NEXT:       64: 4e 80 00 20   blr
+; DIS:      00000068 (idx: 11) const_ivar:
+; DIS-NEXT:       68: 00 00 00 06   <unknown>
+
+; DIS:      Disassembly of section .data:
+; DIS:      0000006c (idx: 15) GInit:
+; DIS-NEXT:       6c: 00 00 00 01   <unknown>
+; DIS:      00000070 (idx: 17) storesTIUninit[DS]:
+; DIS-NEXT:       70: 00 00 00 00   <unknown>
+; DIS-NEXT:       00000070:  R_POS  (idx: 5) .storesTIUninit
+; DIS-NEXT:       74: 00 00 00 88   <unknown>
+; DIS-NEXT:       00000074:  R_POS  (idx: 21) TOC[TC0]
+; DIS-NEXT:       78: 00 00 00 00   <unknown>
+; DIS:      0000007c (idx: 19) loadsTGInit[DS]:
+; DIS-NEXT:       7c: 00 00 00 30   <unknown>
+; DIS-NEXT:       0000007c:  R_POS  (idx: 7) .loadsTGInit
+; DIS-NEXT:       80: 00 00 00 88   <unknown>
+; DIS-NEXT:       00000080:  R_POS  (idx: 21) TOC[TC0]
+; DIS-NEXT:       84: 00 00 00 00   <unknown>
+; DIS:      00000088 (idx: 23) .TIUninit[TC]:
+; DIS-NEXT:       88: 00 00 00 00   <unknown>
+; DIS-NEXT:       00000088:  R_TLSM (idx: 37) TIUninit[UL]
+; DIS:      0000008c (idx: 25) TIUninit[TC]:
+; DIS-NEXT:       8c: 00 00 00 04   <unknown>
+; DIS-NEXT:       0000008c:  R_TLS  (idx: 37) TIUninit[UL]
+; DIS:      00000090 (idx: 27) .TGInit[TC]:
+; DIS-NEXT:       90: 00 00 00 00   <unknown>
+; DIS-NEXT:       00000090:  R_TLSM (idx: 35) TGInit
+; DIS:      00000094 (idx: 29) TGInit[TC]:
+; DIS-NEXT:       94: 00 00 00 00   <unknown>
+; DIS-NEXT:       00000094:  R_TLS  (idx: 35) TGInit
+; DIS:      00000098 (idx: 31) GInit[TC]:
+; DIS-NEXT:       98: 00 00 00 6c   <unknown>
+; DIS-NEXT:       00000098:  R_POS  (idx: 15) GInit
+
+; DIS:      Disassembly of section .tdata:
+; DIS:      00000000 (idx: 35) TGInit:
+; DIS-NEXT:        0: 00 00 00 01   <unknown>
+
+; DIS:      Disassembly of section .tbss:
+; DIS:      00000004 (idx: 37) TIUninit[UL]:
+; DIS-NEXT: ...
+
+attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
+attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }