[AIX][TLS] Add ASM portion changes to support TLSGD relocations to XCOFF objects

[NeHuang]

Summary

This patch adds ASM portion changes to support TLSGD relocations to XCOFF objects:

• Add new variantKinds for the symbol's variable offset and region handle
• Print the proper relocation specifier @gd in the asm streamer when emitting the TC Entry for the variable offset for the symbol
• Fix the switch section failure between the TC Entry of variable offset and region handle
• Put .__tls_get_addr symbol in the ProgramCodeSects with XTY_ER property

[sfertile]

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

150

Real minot nit: I think it might be a bit clearer to break this comment into 2 separate sentences, one for the region handle and its variant-kind/relocation-specifier and one for the variable offset and its variant-kind/relocation-specifier.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

538–539

Its kind of odd to create this symbol just to end up creating the proper symbol for AIX later in the AIX specific handling. In the existing code its a little sloppy but the second call to OutContext.getOrCreateSymbol(Name); at least looks up the same symbol created here. When we create the csect and get its qualname symbol, is that the same MCSymbol as created on this line?

My suggestion is we move creating this symbol down to just after the AIX specific code returns (and if we end up creating the helper function for creating the qual-name symbol for .__tls_get_addr then the name shouldn't be need here either and can also be moved).

569

We have this same block of code twice in this file (here and line 2320), maybe is it worthwhile to move it to a descriptively named helper function?

[sfertile]

llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll

29

This emission of the call instructions to tls_get_addr change because we now create the csect and use the qual-name symbol instead of creating just the external symbol, but we have no test changes that show this behaviour change. We can either update these tests to show the change, or recommit a smaller more focused lit test and show the change with that.

[NeHuang]

Address review comment to

• Create a helper function createMCSymbolForTlsGetAddr and merge unnecessary code
• Split the comments in PPCMCTargetDesc.cpp
• Update the existing test cases to reflect the changes when emitting tls_get_addr

[sfertile]

One minor nit but otherwise LGTM.

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

528

Real minor nit: Its probably better the keep the helper as AIX only and then we don't need to worry about the boolean argument.

[NeHuang]

• Addressed review comment to create the MCsymbol for AIX only in the helper function.
• Rebased the patch with ToT.

llvm/include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_PPC_GOT_DTPREL_HI,   // symbol@got@dtprel@h
     VK_PPC_GOT_DTPREL_HA,   // symbol@got@dtprel@ha
     VK_PPC_TLS,             // symbol@tls
     VK_PPC_GOT_TLSGD,       // symbol@got@tlsgd
     VK_PPC_GOT_TLSGD_LO,    // symbol@got@tlsgd@l
     VK_PPC_GOT_TLSGD_HI,    // symbol@got@tlsgd@h
     VK_PPC_GOT_TLSGD_HA,    // symbol@got@tlsgd@ha
     VK_PPC_TLSGD,           // symbol@tlsgd
+    VK_PPC_AIX_TLSGD,       // symbol@gd
+    VK_PPC_AIX_TLSGDM,      // symbol@m
     VK_PPC_GOT_TLSLD,       // symbol@got@tlsld
     VK_PPC_GOT_TLSLD_LO,    // symbol@got@tlsld@l
     VK_PPC_GOT_TLSLD_HI,    // symbol@got@tlsld@h
     VK_PPC_GOT_TLSLD_HA,    // symbol@got@tlsld@ha
     VK_PPC_GOT_PCREL,       // symbol@got@pcrel
     VK_PPC_GOT_TLSGD_PCREL, // symbol@got@tlsgd@pcrel
     VK_PPC_GOT_TLSLD_PCREL, // symbol@got@tlsld@pcrel
     VK_PPC_GOT_TPREL_PCREL, // symbol@got@tprel@pcrel

llvm/lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_PPC_GOT_DTPREL_HI: return "got@dtprel@h";
   case VK_PPC_GOT_DTPREL_HA: return "got@dtprel@ha";
   case VK_PPC_TLS: return "tls";
   case VK_PPC_GOT_TLSGD: return "got@tlsgd";
   case VK_PPC_GOT_TLSGD_LO: return "got@tlsgd@l";
   case VK_PPC_GOT_TLSGD_HI: return "got@tlsgd@h";
   case VK_PPC_GOT_TLSGD_HA: return "got@tlsgd@ha";
   case VK_PPC_TLSGD: return "tlsgd";
+  case VK_PPC_AIX_TLSGD:
+    return "gd";
+  case VK_PPC_AIX_TLSGDM:
+    return "m";
   case VK_PPC_GOT_TLSLD: return "got@tlsld";
   case VK_PPC_GOT_TLSLD_LO: return "got@tlsld@l";
   case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";
   case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";
   case VK_PPC_GOT_PCREL:
     return "got@pcrel";
   case VK_PPC_GOT_TLSGD_PCREL:
     return "got@tlsgd@pcrel";

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
       : PPCTargetStreamer(S), OS(OS) {}
 
   void emitTCEntry(const MCSymbol &S,
                    MCSymbolRefExpr::VariantKind Kind) override {
     if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(&S)) {
       MCSymbolXCOFF *TCSym =
           cast<MCSectionXCOFF>(Streamer.getCurrentSectionOnly())
               ->getQualNameSymbol();
-      // If the variant kind is TLSGD the entry represents the region handle for
-      // the symbol, we prefix the name with a dot and we add the @m
-      // relocation specifier.
-      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD)
-        OS << "\t.tc ." << TCSym->getName() << "," << XSym->getName() << "@m\n";
+      // If the variant kind is VK_PPC_AIX_TLSGDM the entry represents the
+      // region handle for the symbol, we add the relocation specifier @m.
+      // If the variant kind is VK_PPC_AIX_TLSGD the entry represents the
+      // variable offset for the symbol, we add the relocation specifier @gd.
+      if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
+          Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM)
+        OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
+           << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
       else
         OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
 
       if (TCSym->hasRename())
         Streamer.emitXCOFFRenameDirective(TCSym, TCSym->getSymbolTableName());
       return;
     }
 

llvm/lib/Target/PowerPC/PPC.h

enum TOF {
     /// produce the relocation @got@pcrel. Fixup is VK_PPC_GOT_PCREL.
     MO_GOT_FLAG = 8,
 
     // MO_PCREL_OPT_FLAG - If this bit is set the operand is part of a
     // PC Relative linker optimization.
     MO_PCREL_OPT_FLAG = 16,
 
     /// MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to
-    /// TLS General Dynamic model.
+    /// TLS General Dynamic model for Linux and the variable offset of TLS
+    /// General Dynamic model for AIX.
     MO_TLSGD_FLAG = 32,
 
     /// MO_TPREL_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Initial Exec model.
     MO_TPREL_FLAG = 64,
 
     /// MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to
     /// TLS Local Dynamic model.
     MO_TLSLD_FLAG = 128,
 
+    /// MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative
+    /// to the region handle of TLS General Dynamic model for AIX.
+    MO_TLSGDM_FLAG = 256,
+
     /// MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tlsgd@pcrel.
     /// Fix up is VK_PPC_GOT_TLSGD_PCREL
     MO_GOT_TLSGD_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG | MO_TLSGD_FLAG,
 
     /// MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set
     /// they should produce the relocation @got@tlsld@pcrel.
     /// Fix up is VK_PPC_GOT_TLSLD_PCREL

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

void PPCAsmPrinter::LowerPATCHPOINT(StackMaps &SM, const MachineInstr &MI) {
   assert(NumBytes >= EncodedBytes &&
          "Patchpoint can't request size less than the length of a call.");
   assert((NumBytes - EncodedBytes) % 4 == 0 &&
          "Invalid number of NOP bytes requested!");
   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP));
 }
 
+/// This helper function creates the TlsGetAddr MCSymbol for AIX. We will
+/// create the csect and use the qual-name symbol instead of creating just the
+/// external symbol.
+static MCSymbol *createMCSymbolForTlsGetAddr(MCContext &Ctx) {
+  return Ctx
+      .getXCOFFSection(".__tls_get_addr", SectionKind::getText(),
+                       XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER))
+      ->getQualNameSymbol();
+}
+
 /// EmitTlsCall -- Given a GETtls[ld]ADDR[32] instruction, print a
 /// call to __tls_get_addr to the current output stream.
 void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
                                 MCSymbolRefExpr::VariantKind VK) {
-  StringRef Name = Subtarget->isAIXABI() ? ".__tls_get_addr" : "__tls_get_addr";
-  MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(Name);
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
   unsigned Opcode = PPC::BL8_NOP_TLS;
 
   assert(MI->getNumOperands() >= 3 && "Expecting at least 3 operands from MI");
   if (MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
       MI->getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSLD_PCREL_FLAG) {
     Kind = MCSymbolRefExpr::VK_PPC_NOTOC;
     Opcode = PPC::BL8_NOTOC_TLS;
   }
if (Subtarget->isAIXABI()) {
     // should already be in R3.
     // For TLSGD, which currently is the only supported access model, we only
     // need to generate an absolute branch to .__tls_get_addr.
     Register VarOffsetReg = Subtarget->isPPC64() ? PPC::X4 : PPC::R4;
     (void)VarOffsetReg;
     assert(MI->getOperand(2).isReg() &&
            MI->getOperand(2).getReg() == VarOffsetReg &&
            "GETtls[ld]ADDR[32] must read GPR4");
-    MCSymbol *TlsGetAddrA = OutContext.getOrCreateSymbol(Name);
+    MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext);
     const MCExpr *TlsRef = MCSymbolRefExpr::create(
-        TlsGetAddrA, MCSymbolRefExpr::VK_None, OutContext);
+        TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
     EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::BLA).addExpr(TlsRef));
     return;
   }
 
+  MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol("__tls_get_addr");
+
   if (Subtarget->is32BitELFABI() && isPositionIndependent())
     Kind = MCSymbolRefExpr::VK_PLT;
 
   const MCExpr *TlsRef =
     MCSymbolRefExpr::create(TlsGetAddr, Kind, OutContext);
 
   // Add 32768 offset to the symbol so we follow up the latest GOT/PLT ABI.
   if (Kind == MCSymbolRefExpr::VK_PLT && Subtarget->isSecurePlt() &&
auto getTOCEntryLoadingExprForXCOFF =
 
     if (EntryDistanceFromTOCBase > PositiveTOCRange)
       return getTOCRelocAdjustedExprForXCOFF(Expr, EntryDistanceFromTOCBase);
 
     return Expr;
   };
   auto GetVKForMO = [&](const MachineOperand &MO) {
     // For GD TLS access on AIX, we have two TOC entries for the symbol (one for
-    // the offset and the other for the region handle). They are differentiated
-    // by the presence of the PPCII::MO_TLSGD_FLAG.
-    if (IsAIX && (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG))
-      return MCSymbolRefExpr::VariantKind::VK_PPC_TLSGD;
+    // the variable offset and the other for the region handle). They are
+    // differentiated by MO_TLSGD_FLAG and MO_TLSGDM_FLAG.
+    if (MO.getTargetFlags() & PPCII::MO_TLSGDM_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM;
+    if (MO.getTargetFlags() & PPCII::MO_TLSGD_FLAG)
+      return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD;
     return MCSymbolRefExpr::VariantKind::VK_None;
   };
 
   // Lower multi-instruction pseudo operations.
   switch (MI->getOpcode()) {
   default: break;
   case TargetOpcode::DBG_VALUE:
     llvm_unreachable("Should be handled target independently");
void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) {
 
   // Switch to section to emit TOC base.
   OutStreamer->SwitchSection(getObjFileLowering().getTOCBaseSection());
 
   PPCTargetStreamer *TS =
       static_cast<PPCTargetStreamer *>(OutStreamer->getTargetStreamer());
 
   for (auto &I : TOC) {
-    // Setup the csect for the current TC entry.
-    MCSectionXCOFF *TCEntry = cast<MCSectionXCOFF>(
+    MCSectionXCOFF *TCEntry;
+    // Setup the csect for the current TC entry. If the variant kind is
+    // VK_PPC_AIX_TLSGDM the entry represents the region handle, we create a
+    // new symbol to prefix the name with a dot.
+    if (I.first.second == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM) {
+      SmallString<128> Name;
+      StringRef Prefix = ".";
+      Name += Prefix;
+      Name += I.first.first->getName();
+      MCSymbol *S = OutContext.getOrCreateSymbol(Name);
+      TCEntry = cast<MCSectionXCOFF>(
+          getObjFileLowering().getSectionForTOCEntry(S, TM));
+    } else {
+      TCEntry = cast<MCSectionXCOFF>(
           getObjFileLowering().getSectionForTOCEntry(I.first.first, TM));
+    }
     OutStreamer->SwitchSection(TCEntry);
 
     OutStreamer->emitLabel(I.second);
     if (TS != nullptr)
       TS->emitTCEntry(*I.first.first, I.first.second);
   }
 }
 

 void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default:
     break;
   case PPC::GETtlsADDR64AIX:
   case PPC::GETtlsADDR32AIX: {
     // The reference to .__tls_get_addr is unknown to the assembler
     // so we need to emit an external symbol reference.
-    MCSymbol *TlsGetAddr = OutContext.getOrCreateSymbol(".__tls_get_addr");
+    MCSymbol *TlsGetAddr = createMCSymbolForTlsGetAddr(OutContext);
     ExtSymSDNodeSymbols.insert(TlsGetAddr);
     break;
   }
   case PPC::BL8:
   case PPC::BL:
   case PPC::BL8_NOP:
   case PPC::BL_NOP: {
     const MachineOperand &MO = MI->getOperand(0);

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   SDLoc dl(GA);
   const GlobalValue *GV = GA->getGlobal();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
   // The general-dynamic model is the only access model supported for now, so
   // all the GlobalTLSAddress nodes are lowered with this model.
   // We need to generate two TOC entries, one for the variable offset, one for
   // the region handle. The global address for the TOC entry of the region
-  // handle is created with the MO_TLSGD_FLAG flag so we can easily identify
-  // this entry and add the right relocation.
-  SDValue VariableOffsetTGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
-  SDValue RegionHandleTGA =
+  // handle is created with the MO_TLSGDM_FLAG flag and the global address
+  // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
+  SDValue VariableOffsetTGA =
       DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
+  SDValue RegionHandleTGA =
+      DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
   SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
   SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
   return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
                      RegionHandle);
 }
 
 SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
                                                       SelectionDAG &DAG) const {

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

static const std::pair<unsigned, const char *> TargetFlags[] = {
       {MO_PLT, "ppc-plt"},
       {MO_PIC_FLAG, "ppc-pic"},
       {MO_PCREL_FLAG, "ppc-pcrel"},
       {MO_GOT_FLAG, "ppc-got"},
       {MO_PCREL_OPT_FLAG, "ppc-opt-pcrel"},
       {MO_TLSGD_FLAG, "ppc-tlsgd"},
       {MO_TLSLD_FLAG, "ppc-tlsld"},
       {MO_TPREL_FLAG, "ppc-tprel"},
+      {MO_TLSGDM_FLAG, "ppc-tlsgdm"},
       {MO_GOT_TLSGD_PCREL_FLAG, "ppc-got-tlsgd-pcrel"},
       {MO_GOT_TLSLD_PCREL_FLAG, "ppc-got-tlsld-pcrel"},
       {MO_GOT_TPREL_PCREL_FLAG, "ppc-got-tprel-pcrel"}};
   return makeArrayRef(TargetFlags);
 }
 
 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
 // The VSX versions have the advantage of a full 64-register target whereas

llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll

 define void @storesTGUninit(double %Val) #0 {
 ; SMALL32-LABEL: storesTGUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTGUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTGUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTGUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store double %Val, double* @TGUninit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTGInit(double %Val) #0 {
 ; SMALL32-LABEL: storesTGInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store double %Val, double* @TGInit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTIInit(double %Val) #0 {
 ; SMALL32-LABEL: storesTIInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTIInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTIInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTIInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store double %Val, double* @TIInit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTWInit(double %Val) #0 {
 ; SMALL32-LABEL: storesTWInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stfd 1, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTWInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stfd 1, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTWInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stfd 1, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTWInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stfd 1, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store double %Val, double* @TWInit, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly willreturn
 define double @loadsTGUninit() #1 {
 ; SMALL32-LABEL: loadsTGUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
 ; SMALL32-NEXT:    fadd 1, 0, 1
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTGUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8@l(3)
 ; LARGE32-NEXT:    lfd 1, 0(3)
 ; LARGE32-NEXT:    fadd 1, 0, 1
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTGUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
 ; SMALL64-NEXT:    fadd 1, 0, 1
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTGUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8@l(4)
 ; LARGE64-NEXT:    lfd 1, 0(3)
 ; LARGE64-NEXT:    fadd 1, 0, 1
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define double @loadsTGInit() #1 {
 ; SMALL32-LABEL: loadsTGInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
 ; SMALL32-NEXT:    fadd 1, 0, 1
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8@l(3)
 ; LARGE32-NEXT:    lfd 1, 0(3)
 ; LARGE32-NEXT:    fadd 1, 0, 1
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
 ; SMALL64-NEXT:    fadd 1, 0, 1
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8@l(4)
 ; LARGE64-NEXT:    lfd 1, 0(3)
 ; LARGE64-NEXT:    fadd 1, 0, 1
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define double @loadsTIInit() #1 {
 ; SMALL32-LABEL: loadsTIInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
 ; SMALL32-NEXT:    fadd 1, 0, 1
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTIInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8@l(3)
 ; LARGE32-NEXT:    lfd 1, 0(3)
 ; LARGE32-NEXT:    fadd 1, 0, 1
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTIInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
 ; SMALL64-NEXT:    fadd 1, 0, 1
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTIInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8@l(4)
 ; LARGE64-NEXT:    lfd 1, 0(3)
 ; LARGE64-NEXT:    fadd 1, 0, 1
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define double @loadsTWInit() #1 {
 ; SMALL32-LABEL: loadsTWInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lfd 0, 0(3)
 ; SMALL32-NEXT:    lfd 1, 0(4)
 ; SMALL32-NEXT:    fadd 1, 0, 1
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTWInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lfd 0, 0(3)
 ; LARGE32-NEXT:    addis 3, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C8@l(3)
 ; LARGE32-NEXT:    lfd 1, 0(3)
 ; LARGE32-NEXT:    fadd 1, 0, 1
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTWInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lfd 0, 0(3)
 ; SMALL64-NEXT:    lfd 1, 0(4)
 ; SMALL64-NEXT:    fadd 1, 0, 1
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTWInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lfd 0, 0(3)
 ; LARGE64-NEXT:    ld 3, L..C8@l(4)
 ; LARGE64-NEXT:    lfd 1, 0(3)
 ; LARGE64-NEXT:    fadd 1, 0, 1
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   %0 = load double, double* @TWInit, align 8
   %1 = load double, double* @GInit, align 8
   %add = fadd double %0, %1
   ret double %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL:  .toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:   .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:   .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:   .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:   .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:   .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL:  .toc
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:   .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:   .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:   .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:   .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:   .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:   .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:   .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:   .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:   .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:  .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll

 ; SMALL32-LABEL: storesTGUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTGUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 3
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTGUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTGUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i32 %Val, i32* @TGUninit, align 4
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTGInit(i32 %Val) #0 {
 ; SMALL32-LABEL: storesTGInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 3
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i32 %Val, i32* @TGInit, align 4
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTIUninit(i32 %Val) #0 {
 ; SMALL32-LABEL: storesTIUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTIUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 3
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTIUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTIUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i32 %Val, i32* @TIUninit, align 4
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTWUninit(i32 %Val) #0 {
 ; SMALL32-LABEL: storesTWUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 3
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTWUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 3
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTWUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    stw 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTWUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    stw 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i32 %Val, i32* @TWUninit, align 4
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly willreturn
 define i32 @loadsTGUninit() #1 {
 ; SMALL32-LABEL: loadsTGUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
 ; SMALL32-NEXT:    add 3, 4, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTGUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8@l(4)
 ; LARGE32-NEXT:    lwz 4, 0(4)
 ; LARGE32-NEXT:    add 3, 4, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTGUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTGUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    lwz 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i32 @loadsTGInit() #1 {
 ; SMALL32-LABEL: loadsTGInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
 ; SMALL32-NEXT:    add 3, 4, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8@l(4)
 ; LARGE32-NEXT:    lwz 4, 0(4)
 ; LARGE32-NEXT:    add 3, 4, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    lwz 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i32 @loadsTIUninit() #1 {
 ; SMALL32-LABEL: loadsTIUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
 ; SMALL32-NEXT:    add 3, 4, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTIUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8@l(4)
 ; LARGE32-NEXT:    lwz 4, 0(4)
 ; LARGE32-NEXT:    add 3, 4, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTIUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTIUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    lwz 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i32 @loadsTWUninit() #1 {
 ; SMALL32-LABEL: loadsTWUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 4, 0(4)
 ; SMALL32-NEXT:    add 3, 4, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTWUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 4, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 4, L..C8@l(4)
 ; LARGE32-NEXT:    lwz 4, 0(4)
 ; LARGE32-NEXT:    add 3, 4, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTWUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    lwz 3, 0(3)
 ; SMALL64-NEXT:    lwz 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTWUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    lwz 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    lwz 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   %0 = load i32, i32* @TWUninit, align 4
   %1 = load i32, i32* @GInit, align 4
   %add = add nsw i32 %1, %0
   ret i32 %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL: .toc
 ; SMALL32-LABEL: L..C0:
 ; SMALL32-NEXT:  .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL32-LABEL: L..C1:
-; SMALL32-NEXT:  .tc TGUninit[TC],TGUninit[TL]
+; SMALL32-NEXT:  .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL32-LABEL: L..C2:
 ; SMALL32-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL: L..C3:
-; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL: L..C4:
 ; SMALL32-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL: L..C5:
-; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL: L..C6:
 ; SMALL32-NEXT:  .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL32-LABEL: L..C7:
-; SMALL32-NEXT:  .tc TWUninit[TC],TWUninit[TL]
+; SMALL32-NEXT:  .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL32-LABEL: L..C8:
 ; SMALL32-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL: .toc
 ; LARGE32-LABEL: L..C0:
 ; LARGE32-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE32-LABEL: L..C1:
-; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE32-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE32-LABEL: L..C2:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL: L..C3:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL: L..C4:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL: L..C5:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL: L..C6:
 ; LARGE32-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE32-LABEL: L..C7:
-; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE32-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE32-LABEL: L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:   .tc .TGUninit[TC],TGUninit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]
+; SMALL64-NEXT:   .tc TGUninit[TC],TGUninit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:   .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:   .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:   .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:   .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:   .tc .TWUninit[TC],TWUninit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]
+; SMALL64-NEXT:   .tc TWUninit[TC],TWUninit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:   .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGUninit[TE],TGUninit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]
+; LARGE64-NEXT:  .tc TGUninit[TE],TGUninit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWUninit[TE],TWUninit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]
+; LARGE64-NEXT:  .tc TWUninit[TE],TWUninit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }

llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll

 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 4
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 4
 ; LARGE32-NEXT:    mr 7, 3
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i64 %Val, i64* @TGInit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTIUninit(i64 %Val) #0 {
 ; SMALL32-LABEL: storesTIUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 4
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTIUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 4
 ; LARGE32-NEXT:    mr 7, 3
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTIUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTIUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i64 %Val, i64* @TIUninit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTIInit(i64 %Val) #0 {
 ; SMALL32-LABEL: storesTIInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 4
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTIInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 4
 ; LARGE32-NEXT:    mr 7, 3
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTIInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTIInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i64 %Val, i64* @TIInit, align 8
   ret void
 }
 
 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
 define void @storesTWInit(i64 %Val) #0 {
 ; SMALL32-LABEL: storesTWInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    mr 6, 4
 ; SMALL32-NEXT:    mr 7, 3
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    stw 6, 4(3)
 ; SMALL32-NEXT:    stw 7, 0(3)
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: storesTWInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    mr 6, 4
 ; LARGE32-NEXT:    mr 7, 3
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    stw 6, 4(3)
 ; LARGE32-NEXT:    stw 7, 0(3)
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: storesTWInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    mr 6, 3
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    std 6, 0(3)
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: storesTWInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    mr 6, 3
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    std 6, 0(3)
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   store i64 %Val, i64* @TWInit, align 8
   ret void
 }
 
 ; Function Attrs: norecurse nounwind readonly willreturn
 define i64 @loadsTGInit() #1 {
 ; SMALL32-LABEL: loadsTGInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C0(2)
 ; SMALL32-NEXT:    lwz 4, L..C1(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 7, 0(4)
 ; SMALL32-NEXT:    addc 4, 6, 5
 ; SMALL32-NEXT:    adde 3, 7, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTGInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C0@u(2)
 ; LARGE32-NEXT:    addis 4, L..C1@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C0@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C1@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 5, L..C8@l(5)
 ; LARGE32-NEXT:    lwz 6, 4(5)
 ; LARGE32-NEXT:    lwz 5, 0(5)
 ; LARGE32-NEXT:    addc 4, 6, 4
 ; LARGE32-NEXT:    adde 3, 5, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTGInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C0(2)
 ; SMALL64-NEXT:    ld 4, L..C1(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTGInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C0@u(2)
 ; LARGE64-NEXT:    addis 4, L..C1@u(2)
 ; LARGE64-NEXT:    ld 3, L..C0@l(3)
 ; LARGE64-NEXT:    ld 4, L..C1@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    ld 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i64 @loadsTIUninit() #1 {
 ; SMALL32-LABEL: loadsTIUninit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C2(2)
 ; SMALL32-NEXT:    lwz 4, L..C3(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 7, 0(4)
 ; SMALL32-NEXT:    addc 4, 6, 5
 ; SMALL32-NEXT:    adde 3, 7, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTIUninit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C2@u(2)
 ; LARGE32-NEXT:    addis 4, L..C3@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C2@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C3@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 5, L..C8@l(5)
 ; LARGE32-NEXT:    lwz 6, 4(5)
 ; LARGE32-NEXT:    lwz 5, 0(5)
 ; LARGE32-NEXT:    addc 4, 6, 4
 ; LARGE32-NEXT:    adde 3, 5, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTIUninit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C2(2)
 ; SMALL64-NEXT:    ld 4, L..C3(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTIUninit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C2@u(2)
 ; LARGE64-NEXT:    addis 4, L..C3@u(2)
 ; LARGE64-NEXT:    ld 3, L..C2@l(3)
 ; LARGE64-NEXT:    ld 4, L..C3@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    ld 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i64 @loadsTIInit() #1 {
 ; SMALL32-LABEL: loadsTIInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C4(2)
 ; SMALL32-NEXT:    lwz 4, L..C5(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 7, 0(4)
 ; SMALL32-NEXT:    addc 4, 6, 5
 ; SMALL32-NEXT:    adde 3, 7, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTIInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C4@u(2)
 ; LARGE32-NEXT:    addis 4, L..C5@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C4@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C5@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 5, L..C8@l(5)
 ; LARGE32-NEXT:    lwz 6, 4(5)
 ; LARGE32-NEXT:    lwz 5, 0(5)
 ; LARGE32-NEXT:    addc 4, 6, 4
 ; LARGE32-NEXT:    adde 3, 5, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTIInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C4(2)
 ; SMALL64-NEXT:    ld 4, L..C5(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTIInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C4@u(2)
 ; LARGE64-NEXT:    addis 4, L..C5@u(2)
 ; LARGE64-NEXT:    ld 3, L..C4@l(3)
 ; LARGE64-NEXT:    ld 4, L..C5@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    ld 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0

 define i64 @loadsTWInit() #1 {
 ; SMALL32-LABEL: loadsTWInit:
 ; SMALL32:       # %bb.0: # %entry
 ; SMALL32-NEXT:    mflr 0
 ; SMALL32-NEXT:    stw 0, 8(1)
 ; SMALL32-NEXT:    stwu 1, -32(1)
 ; SMALL32-NEXT:    lwz 3, L..C6(2)
 ; SMALL32-NEXT:    lwz 4, L..C7(2)
-; SMALL32-NEXT:    bla .__tls_get_addr
+; SMALL32-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL32-NEXT:    lwz 4, L..C8(2)
 ; SMALL32-NEXT:    lwz 5, 4(3)
 ; SMALL32-NEXT:    lwz 6, 4(4)
 ; SMALL32-NEXT:    lwz 3, 0(3)
 ; SMALL32-NEXT:    lwz 7, 0(4)
 ; SMALL32-NEXT:    addc 4, 6, 5
 ; SMALL32-NEXT:    adde 3, 7, 3
 ; SMALL32-NEXT:    addi 1, 1, 32
 ; SMALL32-NEXT:    lwz 0, 8(1)
 ; SMALL32-NEXT:    mtlr 0
 ; SMALL32-NEXT:    blr
 ;
 ; LARGE32-LABEL: loadsTWInit:
 ; LARGE32:       # %bb.0: # %entry
 ; LARGE32-NEXT:    mflr 0
 ; LARGE32-NEXT:    stw 0, 8(1)
 ; LARGE32-NEXT:    stwu 1, -32(1)
 ; LARGE32-NEXT:    addis 3, L..C6@u(2)
 ; LARGE32-NEXT:    addis 4, L..C7@u(2)
 ; LARGE32-NEXT:    lwz 3, L..C6@l(3)
 ; LARGE32-NEXT:    lwz 4, L..C7@l(4)
-; LARGE32-NEXT:    bla .__tls_get_addr
+; LARGE32-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE32-NEXT:    lwz 4, 4(3)
 ; LARGE32-NEXT:    lwz 3, 0(3)
 ; LARGE32-NEXT:    addis 5, L..C8@u(2)
 ; LARGE32-NEXT:    lwz 5, L..C8@l(5)
 ; LARGE32-NEXT:    lwz 6, 4(5)
 ; LARGE32-NEXT:    lwz 5, 0(5)
 ; LARGE32-NEXT:    addc 4, 6, 4
 ; LARGE32-NEXT:    adde 3, 5, 3
 ; LARGE32-NEXT:    addi 1, 1, 32
 ; LARGE32-NEXT:    lwz 0, 8(1)
 ; LARGE32-NEXT:    mtlr 0
 ; LARGE32-NEXT:    blr
 ;
 ; SMALL64-LABEL: loadsTWInit:
 ; SMALL64:       # %bb.0: # %entry
 ; SMALL64-NEXT:    mflr 0
 ; SMALL64-NEXT:    std 0, 16(1)
 ; SMALL64-NEXT:    stdu 1, -48(1)
 ; SMALL64-NEXT:    ld 3, L..C6(2)
 ; SMALL64-NEXT:    ld 4, L..C7(2)
-; SMALL64-NEXT:    bla .__tls_get_addr
+; SMALL64-NEXT:    bla .__tls_get_addr[PR]
 ; SMALL64-NEXT:    ld 4, L..C8(2)
 ; SMALL64-NEXT:    ld 3, 0(3)
 ; SMALL64-NEXT:    ld 4, 0(4)
 ; SMALL64-NEXT:    add 3, 4, 3
 ; SMALL64-NEXT:    addi 1, 1, 48
 ; SMALL64-NEXT:    ld 0, 16(1)
 ; SMALL64-NEXT:    mtlr 0
 ; SMALL64-NEXT:    blr
 ;
 ; LARGE64-LABEL: loadsTWInit:
 ; LARGE64:       # %bb.0: # %entry
 ; LARGE64-NEXT:    mflr 0
 ; LARGE64-NEXT:    std 0, 16(1)
 ; LARGE64-NEXT:    stdu 1, -48(1)
 ; LARGE64-NEXT:    addis 3, L..C6@u(2)
 ; LARGE64-NEXT:    addis 4, L..C7@u(2)
 ; LARGE64-NEXT:    ld 3, L..C6@l(3)
 ; LARGE64-NEXT:    ld 4, L..C7@l(4)
-; LARGE64-NEXT:    bla .__tls_get_addr
+; LARGE64-NEXT:    bla .__tls_get_addr[PR]
 ; LARGE64-NEXT:    addis 4, L..C8@u(2)
 ; LARGE64-NEXT:    ld 3, 0(3)
 ; LARGE64-NEXT:    ld 4, L..C8@l(4)
 ; LARGE64-NEXT:    ld 4, 0(4)
 ; LARGE64-NEXT:    add 3, 4, 3
 ; LARGE64-NEXT:    addi 1, 1, 48
 ; LARGE64-NEXT:    ld 0, 16(1)
 ; LARGE64-NEXT:    mtlr 0
 ; LARGE64-NEXT:    blr
 entry:
   %0 = load i64, i64* @TWInit, align 8
   %1 = load i64, i64* @GInit, align 8
   %add = add nsw i64 %1, %0
   ret i64 %add
 }
 
+; External symbol reference checks for .__tls_get_addr
+
+; SMALL32: .extern .__tls_get_addr[PR]
+; SMALL64: .extern .__tls_get_addr[PR]
+; LARGE32: .extern .__tls_get_addr[PR]
+; LARGE64: .extern .__tls_get_addr[PR]
+
 ; TOC entry checks
 
 ; SMALL32-LABEL:  .toc
 ; SMALL32-LABEL:  L..C0:
 ; SMALL32-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL32-LABEL:  L..C1:
-; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL32-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL32-LABEL:  L..C2:
 ; SMALL32-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL32-LABEL:  L..C3:
-; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL32-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL32-LABEL:  L..C4:
 ; SMALL32-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL32-LABEL:  L..C5:
-; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL32-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL32-LABEL:  L..C6:
 ; SMALL32-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL32-LABEL:  L..C7:
-; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL32-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL32-LABEL:  L..C8:
 ; SMALL32-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE32-LABEL:  .toc
 ; LARGE32-LABEL:  L..C0:
 ; LARGE32-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE32-LABEL:  L..C1:
-; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE32-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE32-LABEL:  L..C2:
 ; LARGE32-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE32-LABEL:  L..C3:
-; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE32-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE32-LABEL:  L..C4:
 ; LARGE32-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE32-LABEL:  L..C5:
-; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE32-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE32-LABEL:  L..C6:
 ; LARGE32-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE32-LABEL:  L..C7:
-; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE32-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE32-LABEL:  L..C8:
 ; LARGE32-NEXT:  .tc GInit[TE],GInit[RW]
 
 ; SMALL64-LABEL:  .toc
 ; SMALL64-LABEL:  L..C0:
 ; SMALL64-NEXT:  .tc .TGInit[TC],TGInit[TL]@m
 ; SMALL64-LABEL:  L..C1:
-; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]
+; SMALL64-NEXT:  .tc TGInit[TC],TGInit[TL]@gd
 ; SMALL64-LABEL:  L..C2:
 ; SMALL64-NEXT:  .tc .TIUninit[TC],TIUninit[UL]@m
 ; SMALL64-LABEL:  L..C3:
-; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]
+; SMALL64-NEXT:  .tc TIUninit[TC],TIUninit[UL]@gd
 ; SMALL64-LABEL:  L..C4:
 ; SMALL64-NEXT:  .tc .TIInit[TC],TIInit[TL]@m
 ; SMALL64-LABEL:  L..C5:
-; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]
+; SMALL64-NEXT:  .tc TIInit[TC],TIInit[TL]@gd
 ; SMALL64-LABEL:  L..C6:
 ; SMALL64-NEXT:  .tc .TWInit[TC],TWInit[TL]@m
 ; SMALL64-LABEL:  L..C7:
-; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]
+; SMALL64-NEXT:  .tc TWInit[TC],TWInit[TL]@gd
 ; SMALL64-LABEL:  L..C8:
 ; SMALL64-NEXT:  .tc GInit[TC],GInit[RW]
 
 ; LARGE64-LABEL:  .toc
 ; LARGE64-LABEL:  L..C0:
 ; LARGE64-NEXT:  .tc .TGInit[TE],TGInit[TL]@m
 ; LARGE64-LABEL:  L..C1:
-; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]
+; LARGE64-NEXT:  .tc TGInit[TE],TGInit[TL]@gd
 ; LARGE64-LABEL:  L..C2:
 ; LARGE64-NEXT:  .tc .TIUninit[TE],TIUninit[UL]@m
 ; LARGE64-LABEL:  L..C3:
-; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]
+; LARGE64-NEXT:  .tc TIUninit[TE],TIUninit[UL]@gd
 ; LARGE64-LABEL:  L..C4:
 ; LARGE64-NEXT:  .tc .TIInit[TE],TIInit[TL]@m
 ; LARGE64-LABEL:  L..C5:
-; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]
+; LARGE64-NEXT:  .tc TIInit[TE],TIInit[TL]@gd
 ; LARGE64-LABEL:  L..C6:
 ; LARGE64-NEXT:  .tc .TWInit[TE],TWInit[TL]@m
 ; LARGE64-LABEL:  L..C7:
-; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]
+; LARGE64-NEXT:  .tc TWInit[TE],TWInit[TL]@gd
 ; LARGE64-LABEL:  L..C8:
 ; LARGE64-NEXT:  .tc GInit[TE],GInit[RW]
 
 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }
 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-rop-protection,-spe,-vsx" }