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Differential D100123

[AMDGPU] Add TransVALU to gfx10
ClosedPublic

Authored by sebastian-ne on Apr 8 2021, 9:09 AM.

Details

Reviewers
arsenm
rampitec
foad
kerbowa
andreadb
Commits
rG4897effb1415: [AMDGPU] Add TransVALU to gfx10
Summary

Instructions on the transcendental unit are executed in parallel to the
normal VALU, so add this as an extra resource.

This doesn't seem to have any effect, but it should be more correct.

Diff Detail

Event Timeline

sebastian-ne created this revision.Apr 8 2021, 9:09 AM
Herald added a reviewer: andreadb. · View Herald TranscriptApr 8 2021, 9:09 AM
Herald added subscribers: gbedwell, hiraditya, t-tye and 6 others. · View Herald Transcript
sebastian-ne requested review of this revision.Apr 8 2021, 9:09 AM
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foad added a comment.Apr 8 2021, 9:23 AM

I have no objection to this as a first step in the right direction, but I think it should have no effect at all at the moment. The schedmodel already knows that we can only issue one instruction per cycle, and this patch does not affect that. It only becomes interesting when you model the fact that issuing a trans instruction consumes the trans ALU for (say) 4 cycles, so that on the following 3 cycles you could issue a normal VALU instruction but *not* another trans instruction.

Harbormaster completed remote builds in B97763: Diff 336144.Apr 8 2021, 10:50 AM
rampitec accepted this revision.Apr 8 2021, 12:06 PM

LGTM. What about other models?

This revision is now accepted and ready to land.Apr 8 2021, 12:06 PM
sebastian-ne added a comment.Apr 20 2021, 6:34 AM

What about other models?

The parallel execution is only a thing on gfx10+.

Closed by commit rG4897effb1415: [AMDGPU] Add TransVALU to gfx10 (authored by sebastian-ne). · Explain WhyApr 20 2021, 6:34 AM
This revision was automatically updated to reflect the committed changes.
sebastian-ne added a commit: rG4897effb1415: [AMDGPU] Add TransVALU to gfx10.
foad mentioned this in D157709: [AMDGPU] Add TransVALU to GFX11 scheduling model.Aug 11 2023, 5:49 AM
foad mentioned this in rG948b2625b641: [AMDGPU] Add TransVALU to GFX11 scheduling model.Aug 14 2023, 3:25 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
7 lines
test/
tools/
llvm-mca/
AMDGPU/
17 lines
67 lines
88 lines

Diff 336144

llvm/lib/Target/AMDGPU/SISchedule.td

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Linesdef HWSALU : ProcResource<1> {
let BufferSize = 1; let BufferSize = 1;
} }
def HWVMEM : ProcResource<1> { def HWVMEM : ProcResource<1> {
let BufferSize = 15; // Taken from S_WAITCNT let BufferSize = 15; // Taken from S_WAITCNT
} }
def HWVALU : ProcResource<1> { def HWVALU : ProcResource<1> {
let BufferSize = 1; let BufferSize = 1;
} }
def HWTransVALU : ProcResource<1> { // Transcendental VALU
let BufferSize = 1;
}
def HWRC : ProcResource<1> { // Register destination cache def HWRC : ProcResource<1> { // Register destination cache
let BufferSize = 1; let BufferSize = 1;
} }
def HWXDL : ProcResource<1> { // MFMA CU def HWXDL : ProcResource<1> { // MFMA CU
let BufferSize = 0; let BufferSize = 0;
} }
class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources, class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
let SchedModel = GFX10SpeedModel in { let SchedModel = GFX10SpeedModel in {
// The latency values are 1 / (operations / cycle). // The latency values are 1 / (operations / cycle).
// Add 1 stall cycle for VGPR read. // Add 1 stall cycle for VGPR read.
def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>; def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>; def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;
def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>; def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;
def : HWWriteRes<WriteTrans32, [HWVALU, HWRC], 10>; def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 10>;
def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>; def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;
def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>; def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>; def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>; def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>; def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>;
def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>; def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>;
def : HWWriteRes<WriteTrans64, [HWVALU, HWRC], 24>; def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 24>;
def : HWWriteRes<WriteBranch, [HWBranch], 32>; def : HWWriteRes<WriteBranch, [HWBranch], 32>;
def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>; def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;
def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>; def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>; def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;
def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>; def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>; def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;
def : HWWriteRes<WriteBarrier, [HWBranch], 2000>; def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;
def : InstRW<[WriteCopy], (instrs COPY)>; def : InstRW<[WriteCopy], (instrs COPY)>;
} // End SchedModel = GFX10SpeedModel } // End SchedModel = GFX10SpeedModel

llvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s

Show All 28 Lines
# CHECK-NEXT: 1 5 1.00 U v_add_f32_e32 v2, v1, v0 # CHECK-NEXT: 1 5 1.00 U v_add_f32_e32 v2, v1, v0
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - HWBranch # CHECK-NEXT: [0] - HWBranch
# CHECK-NEXT: [1] - HWExport # CHECK-NEXT: [1] - HWExport
# CHECK-NEXT: [2] - HWLGKM # CHECK-NEXT: [2] - HWLGKM
# CHECK-NEXT: [3] - HWRC # CHECK-NEXT: [3] - HWRC
# CHECK-NEXT: [4] - HWSALU # CHECK-NEXT: [4] - HWSALU
# CHECK-NEXT: [5] - HWVALU # CHECK-NEXT: [5] - HWTransVALU
# CHECK-NEXT: [6] - HWVMEM # CHECK-NEXT: [6] - HWVALU
# CHECK-NEXT: [7] - HWVMEM
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - - 3.00 - 3.00 - # CHECK-NEXT: - - - 3.00 - - 3.00 -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - 1.00 - 1.00 - v_add_f32_e32 v0, v0, v0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_add_f32_e32 v0, v0, v0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_add_f32_e32 v1, v1, v1 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_add_f32_e32 v1, v1, v1
# CHECK-NEXT: - - - 1.00 - 1.00 - v_add_f32_e32 v2, v1, v0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_add_f32_e32 v2, v1, v0
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeeE .. v_add_f32_e32 v0, v0, v0 # CHECK: [0,0] DeeeeE .. v_add_f32_e32 v0, v0, v0
# CHECK-NEXT: [0,1] .DeeeeE .. v_add_f32_e32 v1, v1, v1 # CHECK-NEXT: [0,1] .DeeeeE .. v_add_f32_e32 v1, v1, v1
# CHECK-NEXT: [0,2] . .DeeeeE v_add_f32_e32 v2, v1, v0 # CHECK-NEXT: [0,2] . .DeeeeE v_add_f32_e32 v2, v1, v0
Show All 12 Lines

llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - HWBranch # CHECK-NEXT: [0] - HWBranch
# CHECK-NEXT: [1] - HWExport # CHECK-NEXT: [1] - HWExport
# CHECK-NEXT: [2] - HWLGKM # CHECK-NEXT: [2] - HWLGKM
# CHECK-NEXT: [3] - HWRC # CHECK-NEXT: [3] - HWRC
# CHECK-NEXT: [4] - HWSALU # CHECK-NEXT: [4] - HWSALU
# CHECK-NEXT: [5] - HWVALU # CHECK-NEXT: [5] - HWTransVALU
# CHECK-NEXT: [6] - HWVMEM # CHECK-NEXT: [6] - HWVALU
# CHECK-NEXT: [7] - HWVMEM
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - - 29.00 1.00 28.00 - # CHECK-NEXT: - - - 29.00 1.00 3.00 28.00 -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_i32_f64_e32 v0, v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_i32_e32 v[2:3], v2 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f32_f64_e32 v4, v[4:5] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_f32_e32 v[6:7], v6 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_u32_f64_e32 v8, v[8:9] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_u32_e32 v[10:11], v10 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: - - - 1.00 - 1.00 - v_frexp_exp_i32_f64_e32 v0, v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_frexp_mant_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_fract_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_trunc_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_ceil_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rndne_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_floor_f64_e32 v[6:7], v[6:7] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_floor_f64_e32 v[6:7], v[6:7]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_add_f64 v[2:3], v[2:3], v[2:3] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_add_f64 v[2:3], v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_mul_f64 v[4:5], v[4:5], v[4:5] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_mul_f64 v[4:5], v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_min_f64 v[6:7], v[6:7], v[6:7] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_min_f64 v[6:7], v[6:7], v[6:7]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_max_f64 v[8:9], v[8:9], v[8:9] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_max_f64 v[8:9], v[8:9], v[8:9]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_ldexp_f64 v[2:3], v[2:3], v0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_ldexp_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: - - - 2.00 1.00 1.00 - v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1] # CHECK-NEXT: - - - 2.00 1.00 - 1.00 - v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_trig_preop_f64 v[2:3], v[2:3], v0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cmp_class_f64_e64 vcc_lo, v[2:3], s0 # CHECK-NEXT: - - - 1.00 - - 1.00 - v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rcp_f64_e32 v[0:1], v[0:1] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rsq_f64_e32 v[2:3], v[2:3] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5] # CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 0 # CHECK-NEXT: 0123456789 0123456789 0123456789 0
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 # CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1] # CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2 # CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeE . . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5] # CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeE. . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5]
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s
v_log_f32 v0, v0
v_rcp_f32 v0, v0
v_rsq_f32 v1, v1
v_sqrt_f32 v2, v0
v_rcp_f64 v[0:1], v[0:1]
v_rsq_f64 v[1:2], v[1:2]
v_sqrt_f64 v[2:3], v[0:1]
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 7
# CHECK-NEXT: Total Cycles: 94
# CHECK-NEXT: Total uOps: 7
# CHECK: Dispatch Width: 1
# CHECK-NEXT: uOps Per Cycle: 0.07
# CHECK-NEXT: IPC: 0.07
# CHECK-NEXT: Block RThroughput: 7.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 10 1.00 U v_log_f32_e32 v0, v0
# CHECK-NEXT: 1 10 1.00 U v_rcp_f32_e32 v0, v0
# CHECK-NEXT: 1 10 1.00 U v_rsq_f32_e32 v1, v1
# CHECK-NEXT: 1 10 1.00 U v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: 1 24 1.00 U v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 1 24 1.00 U v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Resources:
# CHECK-NEXT: [0] - HWBranch
# CHECK-NEXT: [1] - HWExport
# CHECK-NEXT: [2] - HWLGKM
# CHECK-NEXT: [3] - HWRC
# CHECK-NEXT: [4] - HWSALU
# CHECK-NEXT: [5] - HWTransVALU
# CHECK-NEXT: [6] - HWVALU
# CHECK-NEXT: [7] - HWVMEM
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - - 7.00 - 7.00 3.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_log_f32_e32 v0, v0
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rcp_f32_e32 v0, v0
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_rsq_f32_e32 v1, v1
# CHECK-NEXT: - - - 1.00 - 1.00 - - v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: - - - 1.00 - 1.00 1.00 - v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeeeeeeeeE . . . . . . . . . . . . v_log_f32_e32 v0, v0
# CHECK-NEXT: [0,1] . . DeeeeeeeeeE . . . . . . . . . . v_rcp_f32_e32 v0, v0
# CHECK-NEXT: [0,2] . . .DeeeeeeeeeE . . . . . . . . . . v_rsq_f32_e32 v1, v1
# CHECK-NEXT: [0,3] . . . . DeeeeeeeeeE . . . . . . . . v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: [0,4] . . . . .DeeeeeeeeeeeeeeeeeeeeeeeE . . . . . v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: [0,5] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeE v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_log_f32_e32 v0, v0
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_rcp_f32_e32 v0, v0
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 v_rsq_f32_e32 v1, v1
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_sqrt_f32_e32 v2, v0
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_rsq_f64_e32 v[1:2], v[1:2]
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 v_sqrt_f64_e32 v[2:3], v[0:1]
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>