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[RISCV] Implement vlsseg intrinsics.
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Authored by HsiangKai on Jan 15 2021, 3:52 AM.

Details

Summary

Define vlsseg intrinsics and pseudo instructions. Lower vlsseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

Diff Detail

Event Timeline

HsiangKai created this revision.Jan 15 2021, 3:52 AM
HsiangKai requested review of this revision.Jan 15 2021, 3:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 3:52 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added inline comments.Jan 15 2021, 5:01 PM
llvm/include/llvm/IR/IntrinsicsRISCV.td
513

maskedof->maskedoff

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
1023

Needs to be rebase to use HasVLOp

HsiangKai updated this revision to Diff 317290.Jan 18 2021, 1:59 AM

Add test cases for floating point types.

craig.topper added inline comments.Jan 19 2021, 10:12 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
152–153

IsStride->IsStrided

llvm/test/CodeGen/RISCV/rvv/vlsseg.ll
1 ↗(On Diff #317290)

rv32?

HsiangKai updated this revision to Diff 317747.Jan 19 2021, 6:41 PM
  • Add test cases for rv32.
  • Fix typo.
HsiangKai marked an inline comment as done.Jan 19 2021, 6:41 PM
HsiangKai updated this revision to Diff 317754.Jan 19 2021, 7:10 PM

clang format.

craig.topper accepted this revision.Jan 20 2021, 10:27 AM

LGTM

llvm/include/llvm/IR/IntrinsicsRISCV.td
505

stride -> strided

This revision is now accepted and ready to land.Jan 20 2021, 10:27 AM
This revision was landed with ongoing or failed builds.Jan 20 2021, 7:53 PM
This revision was automatically updated to reflect the committed changes.