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[RISCV] Implement vlseg intrinsics.
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Authored by HsiangKai on Jan 7 2021, 4:48 AM.

Details

Summary

For Zvlsseg, we need continuous vector registers for the values. We need
to define new register classes for the different combinations of (number
of fields and LMUL). For example,

when the number of fields(NF) = 3, LMUL = 2, the values will be assigned to
(V0M2, V2M2, V4M2), (V2M2, V4M2, V6M2), (V4M2, V6M2, V8M2), ...

We define the vlseg intrinsics with multiple outputs. There is no way to
describe the codegen patterns with multiple outputs in the tablegen files.
We do the codegen in RISCVISelDAGToDAG and use EXTRACT_SUBREG to extract
the values of output.

The multiple scalable vector values will be put into a struct. This
patch is depended on the support for scalable vector struct.

Diff Detail

Event Timeline

HsiangKai created this revision.Jan 7 2021, 4:48 AM
HsiangKai requested review of this revision.Jan 7 2021, 4:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 7 2021, 4:48 AM
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khchen added a subscriber: khchen.Jan 9 2021, 8:37 AM
HsiangKai updated this revision to Diff 316650.Jan 14 2021, 7:05 AM
HsiangKai updated this revision to Diff 317288.Jan 18 2021, 1:57 AM

Add test cases for floating point types.

craig.topper added inline comments.Jan 18 2021, 11:29 PM
llvm/include/llvm/IR/IntrinsicsRISCV.td
495

maskedof->maskedoff

craig.topper added inline comments.Jan 18 2021, 11:38 PM
llvm/test/CodeGen/RISCV/rvv/vlseg.ll
1 ↗(On Diff #317288)

rv32 tests?

HsiangKai updated this revision to Diff 317743.Jan 19 2021, 6:31 PM

Add test cases for rv32.

HsiangKai marked an inline comment as done.Jan 19 2021, 6:34 PM
craig.topper accepted this revision.Jan 19 2021, 8:37 PM

LGTM to me with that one comment.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
2739

Can we drop this Pseudo Instruction comment block?

This revision is now accepted and ready to land.Jan 19 2021, 8:37 PM
This revision was landed with ongoing or failed builds.Jan 19 2021, 10:26 PM
This revision was automatically updated to reflect the committed changes.
rogfer01 added inline comments.Fri, Feb 5, 2:37 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
994

Hi Kai, sorry for digging up this now: it didn't occur to me before.

I understand GetVRegNoV0 receives as RetClass a tuple register class. However GetVRegNoV0 does not seem to handle these register classes and returns the same register class it was given. So I think we could end doing a register allocation like this

vsetvli a1, a1, e32,m2,ta,mu
vlseg2e32.v v0, (a0), v0.t

which I would say is invalid.

What do you think? Thanks!

HsiangKai added inline comments.Tue, Feb 9, 1:13 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
994

Thanks.

You are right. GetVRegNoV0 does not handle tuple register classes. It will be wrong if we reuse v0 in masked segment load/store instructions. Maybe we need to create tuple register classes without v0.