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[RISCV] Implement vsseg intrinsics.
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Authored by HsiangKai on Jan 14 2021, 7:09 AM.

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Summary

Define vsseg intrinsics and pseudo instructions. Lower vsseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

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Event Timeline

HsiangKai created this revision.Jan 14 2021, 7:09 AM
HsiangKai requested review of this revision.Jan 14 2021, 7:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2021, 7:09 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added inline comments.Jan 15 2021, 5:05 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
926

Needs to be rebased

HsiangKai updated this revision to Diff 317289.Jan 18 2021, 1:58 AM

Add test cases for floating point types.

craig.topper added inline comments.Jan 18 2021, 11:45 PM
llvm/test/CodeGen/RISCV/rvv/vsseg.ll
2

rv32?

HsiangKai updated this revision to Diff 317745.Jan 19 2021, 6:35 PM

Add test cases for rv32.

This revision is now accepted and ready to land.Jan 20 2021, 10:22 AM
This revision was landed with ongoing or failed builds.Jan 20 2021, 7:53 PM
This revision was automatically updated to reflect the committed changes.