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[test, ARM] Fix use of var defined in CHECK-NOT
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Authored by thopre on Mar 30 2021, 7:56 AM.

Details

Summary

tries to check for the

absence of a sequence of instructions with several CHECK-NOT with

one of

those directives using a variable defined in another.

LLVM test CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll tries to
check for the absence of a sequence of instructions with several
CHECK-NOT with one of those directives using a variable defined in
another. However, CHECK-NOT are checked independently so that is using
a variable defined in a pattern that should not occur in the input. The
bug was then copied over in
Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector-inseltpoison.ll

This commit removes the definition and uses of variable to check each
line independently, making the check stronger than the current one.

Diff Detail

Event Timeline

thopre created this revision.Mar 30 2021, 7:56 AM
thopre requested review of this revision.Mar 30 2021, 7:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2021, 7:56 AM
dmgreen accepted this revision.Mar 30 2021, 8:10 AM

Sounds good.

This revision is now accepted and ready to land.Mar 30 2021, 8:10 AM
This revision was landed with ongoing or failed builds.Mar 30 2021, 8:28 AM
This revision was automatically updated to reflect the committed changes.