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Differential D99570

[AMDGPU] Remove outdated TODOs. NFC
ClosedPublic

Authored by sebastian-ne on Mar 30 2021, 2:16 AM.

Details

Reviewers
arsenm
kerbowa
foad
Commits
rG1c3b74f0ab6d: [AMDGPU] Remove outdated TODOs. NFC
Summary

spillSGPRToVGPR is already respected in these places since D95768.

Diff Detail

Event Timeline

sebastian-ne created this revision.Mar 30 2021, 2:16 AM
Herald added subscribers: hiraditya, t-tye, tpr and 5 others. · View Herald TranscriptMar 30 2021, 2:16 AM
sebastian-ne requested review of this revision.Mar 30 2021, 2:16 AM
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Harbormaster completed remote builds in B96269: Diff 334085.Mar 30 2021, 3:51 AM
foad accepted this revision.Mar 30 2021, 5:16 AM
foad added a subscriber: foad.

Seems obviously fine to me.

This revision is now accepted and ready to land.Mar 30 2021, 5:16 AM
Closed by commit rG1c3b74f0ab6d: [AMDGPU] Remove outdated TODOs. NFC (authored by sebastian-ne). · Explain WhyMar 30 2021, 6:19 AM
This revision was automatically updated to reflect the committed changes.
sebastian-ne added a commit: rG1c3b74f0ab6d: [AMDGPU] Remove outdated TODOs. NFC.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines

Diff 334085

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Show First 20 Lines • Show All 945 Lines • ▼ Show 20 Lines if (FPSaveIndex && !spilledToMemory(MF, *FPSaveIndex)) {
assert(!MFI.isDeadObjectIndex(FramePtrFI)); assert(!MFI.isDeadObjectIndex(FramePtrFI));
assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill); assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill);
ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill = ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
FuncInfo->getSGPRToVGPRSpills(FramePtrFI); FuncInfo->getSGPRToVGPRSpills(FramePtrFI);
assert(Spill.size() == 1); assert(Spill.size() == 1);
// Save FP before setting it up. // Save FP before setting it up.
// FIXME: This should respect spillSGPRToVGPR;
BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR)
.addReg(FramePtrReg) .addReg(FramePtrReg)
.addImm(Spill[0].Lane) .addImm(Spill[0].Lane)
.addReg(Spill[0].VGPR, RegState::Undef); .addReg(Spill[0].VGPR, RegState::Undef);
} }
// In this case, spill the BP to a reserved VGPR. // In this case, spill the BP to a reserved VGPR.
if (BPSaveIndex && !spilledToMemory(MF, *BPSaveIndex)) { if (BPSaveIndex && !spilledToMemory(MF, *BPSaveIndex)) {
const int BasePtrFI = *BPSaveIndex; const int BasePtrFI = *BPSaveIndex;
assert(!MFI.isDeadObjectIndex(BasePtrFI)); assert(!MFI.isDeadObjectIndex(BasePtrFI));
assert(MFI.getStackID(BasePtrFI) == TargetStackID::SGPRSpill); assert(MFI.getStackID(BasePtrFI) == TargetStackID::SGPRSpill);
ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill = ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
FuncInfo->getSGPRToVGPRSpills(BasePtrFI); FuncInfo->getSGPRToVGPRSpills(BasePtrFI);
assert(Spill.size() == 1); assert(Spill.size() == 1);
// Save BP before setting it up. // Save BP before setting it up.
// FIXME: This should respect spillSGPRToVGPR;
BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR)
.addReg(BasePtrReg) .addReg(BasePtrReg)
.addImm(Spill[0].Lane) .addImm(Spill[0].Lane)
.addReg(Spill[0].VGPR, RegState::Undef); .addReg(Spill[0].VGPR, RegState::Undef);
} }
// Emit the copy if we need an FP, and are using a free SGPR to save it. // Emit the copy if we need an FP, and are using a free SGPR to save it.
if (FuncInfo->SGPRForFPSaveRestoreCopy) { if (FuncInfo->SGPRForFPSaveRestoreCopy) {
▲ Show 20 Lines • Show All 496 Lines • Show Last 20 Lines