[SROA] Speculate around PHIs: allow load to be in a unique-successor unique-predecessor block

[lebedev.ri]

Summary

There's 2009-02-20-InstCombine-SROA.ll InstCombine test that uses SROA,
and it breaks if i change InstCombine to split up inttoptr into bitcast(inttoptr).
The cause is, if we have a PHI and a load of that PHI, InstCombine may sink the load
into unique successor block. And isSafePHIToSpeculate() bails out on that.

So extend isSafePHIToSpeculate() to support traversing through such blocks.

[nikic]

If there is only one successor, and the one successor has only one predecessor, wouldn't these blocks be merged by SimplifyCFG? I'm not sure 2009-02-20-InstCombine-SROA.ll is really testing something meaningful because the specific -instcombine -sroa pass combination shouldn't occur in the wild. The primary SROA passes run before InstCombine, and the secondary post-unroll pass has so many other passes scheduled in between that reasoning about this in terms of just -instcombine -sroa is not very helpful.

I'm not really opposed to this change, but I'm also not sure it's necessary. Maybe in this case simply deleting the test case is the right thing to do?

[spatel]

In D99118#2642802, @nikic wrote:

I'm not really opposed to this change, but I'm also not sure it's necessary. Maybe in this case simply deleting the test case is the right thing to do?

Another option: salvage the intent and move the test to PhaseOrdering as a -O1 test?

[rampitec]

llvm/lib/Transforms/Scalar/SROA.cpp

1209

Typo: blocl.

[lebedev.ri]

Fix typo.

In D99118#2644501, @spatel wrote:

In D99118#2642802, @nikic wrote:

I'm not really opposed to this change, but I'm also not sure it's necessary. Maybe in this case simply deleting the test case is the right thing to do?

Another option: salvage the intent and move the test to PhaseOrdering as a -O1 test?

Sure, i can do that.

llvm/lib/Transforms/Scalar/SROA.cpp

 /// Transforms/Util/Local.h
 static bool isSafePHIToSpeculate(PHINode &PN) {
   const DataLayout &DL = PN.getModule()->getDataLayout();
 
   // For now, we can only do this promotion if the load is in the same block
   // as the PHI, and if there are no stores between the phi and load.
   // TODO: Allow recursive phi users.
   // TODO: Allow stores.
-  BasicBlock *BB = PN.getParent();
   Align MaxAlign;
   uint64_t APWidth = DL.getIndexTypeSizeInBits(PN.getType());
   APInt MaxSize(APWidth, 0);
   bool HaveLoad = false;
   for (User *U : PN.users()) {
     LoadInst *LI = dyn_cast<LoadInst>(U);
     if (!LI || !LI->isSimple())
       return false;
 
-    // For now we only allow loads in the same block as the PHI.  This is
-    // a common case that happens when instcombine merges two loads through
-    // a PHI.
-    if (LI->getParent() != BB)
+    // For now we only allow loads either in the same block, or (recursively) a
+    // single successor of the block (that has a single predecessor block), as
+    // the PHI. This is a common case that happens when instcombine merges two
+    // loads through a PHI, and potentially sinks the load. Ensure that there
+    // are no instructions between the PHI and the load that could store.
+    BasicBlock *BB = PN.getParent();
+    for (BasicBlock::iterator BBI(PN);; ++BBI) {
+      if (BBI == BB->end()) {
+        BasicBlock *UniqueSucc = BB->getUniqueSuccessor();
+        if (!UniqueSucc || UniqueSucc->getUniquePredecessor() != BB)
           return false;
-
-    // Ensure that there are no instructions between the PHI and the load that
-    // could store.
-    for (BasicBlock::iterator BBI(PN); &*BBI != LI; ++BBI)
+        BB = UniqueSucc;
+        BBI = BB->begin();
+      }
+      if (BBI == BasicBlock::iterator(LI))
+        break;
       if (BBI->mayWriteToMemory())
         return false;
+    }
 
     uint64_t Size = DL.getTypeStoreSize(LI->getType()).getFixedSize();
     MaxAlign = std::max(MaxAlign, LI->getAlign());
     MaxSize = MaxSize.ult(Size) ? APInt(APWidth, Size) : MaxSize;
     HaveLoad = true;
   }
 
   if (!HaveLoad)

llvm/test/Transforms/SROA/2009-02-20-InstCombine-SROA.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -sroa -S | FileCheck %s
 
 ; rdar://6417724
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.6"
 
 %"struct.std::vector<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >" }
 %"struct.std::_Vector_base<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" }
 %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" = type { i32*, i32*, i32* }
 
 define i32* @_Z3fooRSt6vectorIiSaIiEE(%"struct.std::vector<int,std::allocator<int> >"* %X) {
 ; CHECK-LABEL: @_Z3fooRSt6vectorIiSaIiEE(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0:%.*]] = alloca i32*, align 8
-; CHECK-NEXT:    [[__LAST_ADDR_I_I_SROA_0:%.*]] = alloca i32*, align 8
 ; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* [[X:%.*]], i32 0, i32 0, i32 0, i32 1
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* [[X]], i32 0, i32 0, i32 0, i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4
-; CHECK-NEXT:    store i32* [[TMP3]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    store i32* [[TMP1]], i32** [[__LAST_ADDR_I_I_SROA_0]], align 8
 ; CHECK-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP1]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = ptrtoint i32* [[TMP3]] to i32
 ; CHECK-NEXT:    [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = ashr i32 [[TMP6]], 4
 ; CHECK-NEXT:    br label [[BB12_I_I:%.*]]
 ; CHECK:       bb.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_13:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_13]], align 4
+; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0:%.*]], align 4
 ; CHECK-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 42
 ; CHECK-NEXT:    br i1 [[TMP9]], label [[BB1_I_I:%.*]], label [[BB2_I_I:%.*]]
 ; CHECK:       bb1.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT:%.*]]
 ; CHECK:       bb2.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_14:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_14]], i32 1
-; CHECK-NEXT:    store i32* [[TMP10]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0]], i32 1
 ; CHECK-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 42
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[BB4_I_I:%.*]], label [[BB5_I_I:%.*]]
 ; CHECK:       bb4.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb5.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_15:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_15]], i32 1
-; CHECK-NEXT:    store i32* [[TMP13]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i32, i32* [[TMP10]], i32 1
 ; CHECK-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
 ; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 42
 ; CHECK-NEXT:    br i1 [[TMP15]], label [[BB7_I_I:%.*]], label [[BB8_I_I:%.*]]
 ; CHECK:       bb7.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb8.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_16:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_16]], i32 1
-; CHECK-NEXT:    store i32* [[TMP16]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i32, i32* [[TMP13]], i32 1
 ; CHECK-NEXT:    [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
 ; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 42
 ; CHECK-NEXT:    br i1 [[TMP18]], label [[BB10_I_I:%.*]], label [[BB11_I_I:%.*]]
 ; CHECK:       bb10.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb11.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_17:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_17]], i32 1
-; CHECK-NEXT:    store i32* [[TMP19]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr i32, i32* [[TMP16]], i32 1
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[__TRIP_COUNT_0_I_I:%.*]], -1
 ; CHECK-NEXT:    br label [[BB12_I_I]]
 ; CHECK:       bb12.i.i:
-; CHECK-NEXT:    [[__TRIP_COUNT_0_I_I]] = phi i32 [ [[TMP7]], [[ENTRY:%.*]] ], [ [[TMP20]], [[BB11_I_I]] ]
+; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0]] = phi i32* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[TMP19]], [[BB11_I_I]] ]
+; CHECK-NEXT:    [[__TRIP_COUNT_0_I_I]] = phi i32 [ [[TMP7]], [[ENTRY]] ], [ [[TMP20]], [[BB11_I_I]] ]
 ; CHECK-NEXT:    [[TMP21:%.*]] = icmp sgt i32 [[__TRIP_COUNT_0_I_I]], 0
 ; CHECK-NEXT:    br i1 [[TMP21]], label [[BB_I_I:%.*]], label [[BB13_I_I:%.*]]
 ; CHECK:       bb13.i.i:
-; CHECK-NEXT:    [[__LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0_:%.*]] = load i32*, i32** [[__LAST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP22:%.*]] = ptrtoint i32* [[__LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0___LAST_ADDR_I_I_SROA_0_0_]] to i32
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP23:%.*]] = ptrtoint i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_]] to i32
+; CHECK-NEXT:    [[TMP22:%.*]] = ptrtoint i32* [[TMP1]] to i32
+; CHECK-NEXT:    [[TMP23:%.*]] = ptrtoint i32* [[__FIRST_ADDR_I_I_SROA_0_0]] to i32
 ; CHECK-NEXT:    [[TMP24:%.*]] = sub i32 [[TMP22]], [[TMP23]]
 ; CHECK-NEXT:    [[TMP25:%.*]] = ashr i32 [[TMP24]], 2
 ; CHECK-NEXT:    switch i32 [[TMP25]], label [[BB26_I_I:%.*]] [
 ; CHECK-NEXT:    i32 1, label [[BB22_I_I:%.*]]
 ; CHECK-NEXT:    i32 2, label [[BB18_I_I:%.*]]
 ; CHECK-NEXT:    i32 3, label [[BB14_I_I:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       bb14.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_7:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP26:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_7]], align 4
+; CHECK-NEXT:    [[TMP26:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0]], align 4
 ; CHECK-NEXT:    [[TMP27:%.*]] = icmp eq i32 [[TMP26]], 42
 ; CHECK-NEXT:    br i1 [[TMP27]], label [[BB16_I_I:%.*]], label [[BB17_I_I:%.*]]
 ; CHECK:       bb16.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb17.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_8:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_8]], i32 1
-; CHECK-NEXT:    store i32* [[TMP28]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP28:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0]], i32 1
 ; CHECK-NEXT:    br label [[BB18_I_I]]
 ; CHECK:       bb18.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_9:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP29:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_9]], align 4
+; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_1:%.*]] = phi i32* [ [[TMP28]], [[BB17_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_0]], [[BB13_I_I]] ]
+; CHECK-NEXT:    [[TMP29:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_1]], align 4
 ; CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i32 [[TMP29]], 42
 ; CHECK-NEXT:    br i1 [[TMP30]], label [[BB20_I_I:%.*]], label [[BB21_I_I:%.*]]
 ; CHECK:       bb20.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb21.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_10:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP31:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_10]], i32 1
-; CHECK-NEXT:    store i32* [[TMP31]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP31:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_1]], i32 1
 ; CHECK-NEXT:    br label [[BB22_I_I]]
 ; CHECK:       bb22.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_11:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP32:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_11]], align 4
+; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_2:%.*]] = phi i32* [ [[TMP31]], [[BB21_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_0]], [[BB13_I_I]] ]
+; CHECK-NEXT:    [[TMP32:%.*]] = load i32, i32* [[__FIRST_ADDR_I_I_SROA_0_2]], align 4
 ; CHECK-NEXT:    [[TMP33:%.*]] = icmp eq i32 [[TMP32]], 42
 ; CHECK-NEXT:    br i1 [[TMP33]], label [[BB24_I_I:%.*]], label [[BB25_I_I:%.*]]
 ; CHECK:       bb24.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       bb25.i.i:
-; CHECK-NEXT:    [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_12:%.*]] = load i32*, i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
-; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0___FIRST_ADDR_I_I_SROA_0_0_12]], i32 1
-; CHECK-NEXT:    store i32* [[TMP34]], i32** [[__FIRST_ADDR_I_I_SROA_0]], align 8
+; CHECK-NEXT:    [[TMP34:%.*]] = getelementptr i32, i32* [[__FIRST_ADDR_I_I_SROA_0_2]], i32 1
 ; CHECK-NEXT:    br label [[BB26_I_I]]
 ; CHECK:       bb26.i.i:
 ; CHECK-NEXT:    br label [[_ZST4FINDIN9__GNU_CXX17__NORMAL_ITERATORIPIST6VECTORIISAIIEEEEIET_S7_S7_RKT0__EXIT]]
 ; CHECK:       _ZSt4findIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET_S7_S7_RKT0_.exit:
-; CHECK-NEXT:    [[DOTIN_IN:%.*]] = phi i32** [ [[__LAST_ADDR_I_I_SROA_0]], [[BB26_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB24_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB20_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB16_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB10_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB7_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB4_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0]], [[BB1_I_I]] ]
+; CHECK-NEXT:    [[DOTIN_IN_SROA_SPECULATED:%.*]] = phi i32* [ [[TMP1]], [[BB26_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_2]], [[BB24_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_1]], [[BB20_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_0]], [[BB16_I_I]] ], [ [[TMP16]], [[BB10_I_I]] ], [ [[TMP13]], [[BB7_I_I]] ], [ [[TMP10]], [[BB4_I_I]] ], [ [[__FIRST_ADDR_I_I_SROA_0_0]], [[BB1_I_I]] ]
 ; CHECK-NEXT:    br label [[RETURN:%.*]]
 ; CHECK:       return:
-; CHECK-NEXT:    [[TMP35:%.*]] = load i32*, i32** [[DOTIN_IN]], align 4
-; CHECK-NEXT:    ret i32* [[TMP35]]
+; CHECK-NEXT:    ret i32* [[DOTIN_IN_SROA_SPECULATED]]
 ;
 entry:
   %__first_addr.i.i.sroa.0 = alloca i32*, align 8
   %__last_addr.i.i.sroa.0 = alloca i32*, align 8
   %0 = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0, i32 0, i32 1
   %1 = load i32*, i32** %0, align 4
   %2 = getelementptr %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >"* %X, i32 0, i32 0, i32 0, i32 0
   %3 = load i32*, i32** %2, align 4

llvm/test/Transforms/SROA/phi-with-duplicate-pred.ll

 
 cleanup7:                                         ; preds = %cleanup
   ret void
 }
 
 define void @f3() {
 ; CHECK-LABEL: @f3(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[E:%.*]] = alloca i16, align 1
 ; CHECK-NEXT:    br i1 undef, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    br label [[CLEANUP:%.*]]
 ; CHECK:       cleanup:
+; CHECK-NEXT:    [[G_0_SROA_SPECULATE_LOAD_CLEANUP:%.*]] = load i16, i16* @a, align 1
 ; CHECK-NEXT:    switch i32 2, label [[CLEANUP7:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[LBL1:%.*]]
 ; CHECK-NEXT:    i32 2, label [[LBL1]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.else:
 ; CHECK-NEXT:    br label [[LBL1]]
 ; CHECK:       lbl1:
-; CHECK-NEXT:    [[G_0:%.*]] = phi i16* [ @a, [[CLEANUP]] ], [ @a, [[CLEANUP]] ], [ [[E]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[G_0_SROA_SPECULATED:%.*]] = phi i16 [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ [[G_0_SROA_SPECULATE_LOAD_CLEANUP]], [[CLEANUP]] ], [ undef, [[IF_ELSE]] ]
 ; CHECK-NEXT:    br label [[FINAL:%.*]]
 ; CHECK:       final:
-; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* [[G_0]], align 1
 ; CHECK-NEXT:    unreachable
 ; CHECK:       cleanup7:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %e = alloca i16, align 1
   br i1 undef, label %if.then, label %if.else