[RISCV] Don't form MULW for (sext_inreg (mul X, Y), i32)) if the mul has another use.

[craig.topper]

Summary

If this pattern doesn't fully remove the mul we'll end up with
a MUL and MULW with the same inputs.

On the assumption that multipliers are a limited resource and have
higher latency than an add, it is likely better to use a single MUL
and a sext.w instruction.

[craig.topper]

llvm/test/CodeGen/RISCV/xaluo.ll

703

This is an interesting case. The mul is used by the sext.w and the sw. Both only consume the lower 32 bits. So it would be better to use MULW for the sext_inreg+mul and pass that result to the sw.

Pretty sure anything we do to try to make that happen in DAG combine or lowering will be defeated by SimplifyDemandedBits. Unless we add a RISCVISD::MULW node to hide it.

We could probably catch this specific case with a PreprocessISelDAG peephole that would like for a sext_inreg+mul. We could examine all other users of the mul and see if they only need the lower 32 bits. We might not be able to catch many cases without recursively checking the users of the users though. Ideally we'd be able to see that the user was a ADDW/SUBW but that requires know the use is an add that is itself used by a sext_inreg.

1050–1052

This demonstrates that we now get full benefit of the (mul (and X, 0xffffffff), (and Y, 0xffffffff)) optimization.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoM.td

74

Super nitty, but I see su and my mind doesn't jump to "single use". I think more "signed/unsigned". Maybe something like mul_oneuse?

[craig.topper]

Rename mul_su->mul_oneuse

[craig.topper]

I made a dedicated fix for the motivating issue with 5692fc38e0d17abc55a4a84da98f021a1d53d76d so I'm not as concerned with pushing this patch now.

[asb]

In D99029#2654346, @craig.topper wrote:

I made a dedicated fix for the motivating issue with 5692fc38e0d17abc55a4a84da98f021a1d53d76d so I'm not as concerned with pushing this patch now.

Ack. The approach of adding a one-use check seems sensible, so if it does make sense to respin and push this further, obviously just ping here.

llvm/lib/Target/RISCV/RISCVInstrInfoM.td

 def : PatGprGpr<mulhu, MULHU>;
 // No ISDOpcode for mulhsu
 def : PatGprGpr<sdiv, DIV>;
 def : PatGprGpr<udiv, DIVU>;
 def : PatGprGpr<srem, REM>;
 def : PatGprGpr<urem, REMU>;
 } // Predicates = [HasStdExtM]
 
+// A 'mul' node with a single use.
+def mul_oneuse : PatFrag<(ops node:$lhs, node:$rhs), (mul node:$lhs, node:$rhs), [{
+  return N->hasOneUse();
+}]>;
+
 let Predicates = [HasStdExtM, IsRV64] in {
-def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
+def : Pat<(sext_inreg (mul_oneuse GPR:$rs1, GPR:$rs2), i32),
           (MULW GPR:$rs1, GPR:$rs2)>;
 
 def : PatGprGpr<riscv_divw, DIVW>;
 def : PatGprGpr<riscv_divuw, DIVUW>;
 def : PatGprGpr<riscv_remuw, REMUW>;
 
 // Handle the specific cases where using DIVU/REMU would be correct and result
 // in fewer instructions than emitting DIVUW/REMUW then zero-extending the

llvm/test/CodeGen/RISCV/xaluo.ll

 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    sw a1, 0(a2)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    mul a3, a0, a1
-; RV64-NEXT:    mulw a0, a0, a1
-; RV64-NEXT:    xor a0, a0, a3
+; RV64-NEXT:    mul a1, a0, a1
+; RV64-NEXT:    sext.w a0, a1
+; RV64-NEXT:    xor a0, a0, a1
 ; RV64-NEXT:    snez a0, a0
-; RV64-NEXT:    sw a3, 0(a2)
+; RV64-NEXT:    sw a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a3, a0, a1
 ; RV32ZBA-NEXT:    mul a1, a0, a1
 ; RV32ZBA-NEXT:    srai a0, a1, 31
 ; RV32ZBA-NEXT:    xor a0, a3, a0
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    sw a1, 0(a2)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    mul a3, a0, a1
-; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    xor a0, a0, a3
+; RV64ZBA-NEXT:    mul a1, a0, a1
+; RV64ZBA-NEXT:    sext.w a0, a1
+; RV64ZBA-NEXT:    xor a0, a0, a1
 ; RV64ZBA-NEXT:    snez a0, a0
-; RV64ZBA-NEXT:    sw a3, 0(a2)
+; RV64ZBA-NEXT:    sw a1, 0(a2)
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }

 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo2.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    addi a2, zero, 13
-; RV64-NEXT:    mul a3, a0, a2
-; RV64-NEXT:    mulw a0, a0, a2
-; RV64-NEXT:    xor a0, a0, a3
+; RV64-NEXT:    mul a2, a0, a2
+; RV64-NEXT:    sext.w a0, a2
+; RV64-NEXT:    xor a0, a0, a2
 ; RV64-NEXT:    snez a0, a0
-; RV64-NEXT:    sw a3, 0(a1)
+; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo2.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    addi a2, zero, 13
 ; RV32ZBA-NEXT:    mulh a3, a0, a2
 ; RV32ZBA-NEXT:    mul a2, a0, a2
 ; RV32ZBA-NEXT:    srai a0, a2, 31
 ; RV32ZBA-NEXT:    xor a0, a3, a0
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    sw a2, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo2.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a0, a0
 ; RV64ZBA-NEXT:    addi a2, zero, 13
-; RV64ZBA-NEXT:    mul a3, a0, a2
-; RV64ZBA-NEXT:    mulw a0, a0, a2
-; RV64ZBA-NEXT:    xor a0, a0, a3
+; RV64ZBA-NEXT:    mul a2, a0, a2
+; RV64ZBA-NEXT:    sext.w a0, a2
+; RV64ZBA-NEXT:    xor a0, a0, a2
 ; RV64ZBA-NEXT:    snez a0, a0
-; RV64ZBA-NEXT:    sw a3, 0(a1)
+; RV64ZBA-NEXT:    sw a2, 0(a1)
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 13)
   %val = extractvalue {i32, i1} %t, 0
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }

 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    sw a0, 0(a2)
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo3.i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slli a1, a1, 32
-; RV64-NEXT:    srli a3, a1, 32
 ; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a4, a0, 32
 ; RV64-NEXT:    mulhu a0, a0, a1
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    snez a1, a0
-; RV64-NEXT:    mulw a0, a4, a3
+; RV64-NEXT:    srli a1, a0, 32
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    sw a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo3.i32:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    mul a3, a0, a1
 ; RV32ZBA-NEXT:    mulhu a0, a0, a1
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    sw a0, 0(a2)
 ; RV32ZBA-NEXT:    mv a0, a3
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo3.i32:
 ; RV64ZBA:       # %bb.0:
 ; RV64ZBA-NEXT:    zext.w a1, a1
 ; RV64ZBA-NEXT:    zext.w a0, a0
-; RV64ZBA-NEXT:    mul a3, a0, a1
-; RV64ZBA-NEXT:    srli a3, a3, 32
-; RV64ZBA-NEXT:    snez a3, a3
-; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    sw a3, 0(a2)
+; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    srli a1, a0, 32
+; RV64ZBA-NEXT:    snez a1, a1
+; RV64ZBA-NEXT:    sext.w a0, a0
+; RV64ZBA-NEXT:    sw a1, 0(a2)
 ; RV64ZBA-NEXT:    ret
   %4 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %0, i32 %1)
   %5 = extractvalue { i32, i1 } %4, 1
   %6 = extractvalue { i32, i1 } %4, 0
   %7 = zext i1 %5 to i32
   store i32 %7, i32* %2, align 4
   ret i32 %6
 }

 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB39_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1
 ; RV64-NEXT:    sext.w a3, a0
-; RV64-NEXT:    mul a4, a3, a2
-; RV64-NEXT:    mulw a2, a3, a2
-; RV64-NEXT:    bne a2, a4, .LBB39_2
+; RV64-NEXT:    mul a2, a3, a2
+; RV64-NEXT:    sext.w a3, a2
+; RV64-NEXT:    bne a3, a2, .LBB39_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB39_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.select.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a3, a0, a1
 ; RV32ZBA-NEXT:    srai a3, a3, 31
 ; RV32ZBA-NEXT:    bne a2, a3, .LBB39_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a1
 ; RV32ZBA-NEXT:  .LBB39_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.select.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a2, a1
 ; RV64ZBA-NEXT:    sext.w a3, a0
-; RV64ZBA-NEXT:    mul a4, a3, a2
-; RV64ZBA-NEXT:    mulw a2, a3, a2
-; RV64ZBA-NEXT:    bne a2, a4, .LBB39_2
+; RV64ZBA-NEXT:    mul a2, a3, a2
+; RV64ZBA-NEXT:    sext.w a3, a2
+; RV64ZBA-NEXT:    bne a3, a2, .LBB39_2
 ; RV64ZBA-NEXT:  # %bb.1: # %entry
 ; RV64ZBA-NEXT:    mv a0, a1
 ; RV64ZBA-NEXT:  .LBB39_2: # %entry
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = select i1 %obit, i32 %v1, i32 %v2

 ; RV32-NEXT:    xor a0, a2, a0
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.not.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    mul a2, a0, a1
-; RV64-NEXT:    mulw a0, a0, a1
-; RV64-NEXT:    xor a0, a0, a2
+; RV64-NEXT:    mul a0, a0, a1
+; RV64-NEXT:    sext.w a1, a0
+; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.not.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    srai a0, a0, 31
 ; RV32ZBA-NEXT:    xor a0, a2, a0
 ; RV32ZBA-NEXT:    seqz a0, a0
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.not.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    mul a2, a0, a1
-; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    xor a0, a0, a2
+; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    sext.w a1, a0
+; RV64ZBA-NEXT:    xor a0, a1, a0
 ; RV64ZBA-NEXT:    seqz a0, a0
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }

 ; RV32-NEXT:  .LBB55_2: # %continue
 ; RV32-NEXT:    addi a0, zero, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.br.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a1, a1
 ; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    mul a2, a0, a1
-; RV64-NEXT:    mulw a0, a0, a1
-; RV64-NEXT:    beq a0, a2, .LBB55_2
+; RV64-NEXT:    mul a0, a0, a1
+; RV64-NEXT:    sext.w a1, a0
+; RV64-NEXT:    beq a1, a0, .LBB55_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    mv a0, zero
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB55_2: # %continue
 ; RV64-NEXT:    addi a0, zero, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: smulo.br.i32:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mulh a2, a0, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a1
 ; RV32ZBA-NEXT:    srai a0, a0, 31
 ; RV32ZBA-NEXT:    beq a2, a0, .LBB55_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    mv a0, zero
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB55_2: # %continue
 ; RV32ZBA-NEXT:    addi a0, zero, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: smulo.br.i32:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sext.w a1, a1
 ; RV64ZBA-NEXT:    sext.w a0, a0
-; RV64ZBA-NEXT:    mul a2, a0, a1
-; RV64ZBA-NEXT:    mulw a0, a0, a1
-; RV64ZBA-NEXT:    beq a0, a2, .LBB55_2
+; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    sext.w a1, a0
+; RV64ZBA-NEXT:    beq a1, a0, .LBB55_2
 ; RV64ZBA-NEXT:  # %bb.1: # %overflow
 ; RV64ZBA-NEXT:    mv a0, zero
 ; RV64ZBA-NEXT:    ret
 ; RV64ZBA-NEXT:  .LBB55_2: # %continue
 ; RV64ZBA-NEXT:    addi a0, zero, 1
 ; RV64ZBA-NEXT:    ret
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)