[MCA] Disable RCU for InOrderIssueStage

[asavonic]

Summary

This is a follow-up for:
D98604 [MCA] Ensure that writes occur in-order

When instructions are aligned by the order of writes, they retire
in-order naturally. There is no need for an RCU, so it is disabled.
RCU statistic is adjusted to handle this.

[foad]

Can you remove some of the code added to RetireControlUnit.cpp by D94928 and D98356, if it no longer has to cope with in-order CPUs?

[andreadb]

There is nothing wrong with using a dummy RCU for the InOrderIssue stage.

The RCUtokenID is always stored in the instruction at dispatch time. You don't need any changes to pre-existing dispatch stage APIs (and listeners).

Note that your code still does this:

unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
IS.dispatch(RCUTokenID);

Your check on TotalROBEntries is fine. However, RetireControlUnitStatistics could (and probably should) be disabled for in-order processors (since it doesn't really makes sense).
Excluding those API changes which I don't particularly like, the other changes look mostly harmless and are basically a NFC restructuring.

I strongly suggest that we focus on fixing D98604 first.
Once D98604 is fixed, then you can update this patch and discuss the changes to RetireControlUnitStatistics (and whether those make any sense in practice for in-order processors). I don't think that we should touch the dispatch stage, nor the event associated to it.

[asavonic]

In D98628#2625892, @andreadb wrote:

There is nothing wrong with using a dummy RCU for the InOrderIssue stage.

The RCUtokenID is always stored in the instruction at dispatch time. You don't need any changes to pre-existing dispatch stage APIs (and listeners).

Thanks, I missed that.

Note that your code still does this:

unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
IS.dispatch(RCUTokenID);

Your check on TotalROBEntries is fine. However, RetireControlUnitStatistics could (and probably should) be disabled for in-order processors (since it doesn't really makes sense).

I made RCU optional and disabled the corresponding statistic for in-order processors.

In D98628#2625846, @foad wrote:

Can you remove some of the code added to RetireControlUnit.cpp by D94928 and D98356, if it no longer has to cope with in-order CPUs?

Done. RCU is initialized and used only for out-of-order processors now.

[asavonic]

RCU is now optional for RetireStage
RCU statistic is disabled for in-order processors.

[andreadb]

I personally don't like the idea of making the RCU optional in the RetireStage. The is no point in having a RetireStage if there is no RCU.

For in-order processors, the RetireStage is not really needed. Instructions are always issued in-order, and for some instructions, we allow out-of-order commit.
For the purpose of MCA, we don't require an RCU; the retire stage would simply propagates "instruction retired" events. Having a stage just for that purpouse is a bit silly.

If you want to fully get rid of the RCU, then there is a better way: just get rid of the RetireStage for in-order processors, and generate "instruction retired" events directly from the InOrderIssueStage.
For in-order, the "instruction executed" and "instruction retired" events always match (both events are generated during the same cycle).

I suggest the following changes:

1. Remove the RetireStage and always notify that an instruction is retired after it has finished execution.
2. (As a consequence of 1.) You don't need any changes to the RetireStage. The RCU should not be optional, so pass it always by reference to the constructor.
3. Please revert the changes to the RetireStatistics. We don't use those stats for in-order processors, so there is no reason why that file should be touched.
4. (As a consequence of 1. and 2.) Do not print character R in the TimelineView if E and R are the same cycle. This means ignoring a loop at around line 244.

Point 4. means that we no longer get the R character in the timeline. In my opinion this is more accurate, since focus is on the write-back, and there is no delayed commit. We could add a note about this in the section which describes the timeline view.

Minor nit:
Please rename function notifyInstructionExecute (in InOrderIssueStage.cpp) to notifyInstructionIssue.

[asavonic]

Removed RetireStage from the in-order pipeline.
Retire and execute events are emitted in the same cycle.

[andreadb]

LGTM.

Thanks!

llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s

63

I am assuming that this change is correct.
Not sure if we have already enough load/store tests. If not, then it may be worthy to add some tests (maybe as a follow-up. But only if you think that it is required).

[asavonic]

llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s

63

No, I think the change is incorrect. Thank you very much for spotting this! VLDR is issued 1 cycle earlier, and it does not obey to -1 ReadAdvance anymore.

This happens because we check ReadAdvance only for current WriteState objects. Since we now retire instructions in the same cycle as they're executed, the corresponding WriteState objects are also invalidated in the same cycle. A subsequent instruction cannot check for a negative ReadAdvance because the WriteState objects are invalidated at this point.

I'm thinking on how to fix this. Can we free registers when an instruction is retired, but keep WriteState objects for N cycles more?

[andreadb]

llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s

63

mm.. this is a bit of annoying to model as it would require a structural change.
I think that you can solve this problem by introducing a counter in the register file which acts as a timer. At the beginning of each cycle, that counter is incremented by one.
When a write is executed, we could store the actual value of that counter into one of its fields. So that we know the relative cycle at which it has finished execution. So even if the object is invalidated, we still retain the "last write cycle" information.

Not sure if it makes sense...

[andreadb]

Hey Andrew,

could you please rebase your patch? I have committed a fix for the issue with negative read-advance cycles.
Now you need to notify the PRF every time an instruction is executed. That way, the PRF will be able to correctly keep track of the "write executed" cycle.
I don't think that there are other important changes to make.

Cheers,
-Andrea

[asavonic]

• Enabled negative readadvance tracking.
• Reverted unnecessary changes in RetireStage.

[andreadb]

LGTM. Thanks Andrew!

PR49524 can now be resolved either as invalid or fixed (mentioning that we no longer use a RetireStage for in-order processors).
Since the issue with structural hazards has been fixed, you can also resolve PR41796.

-Andrea

llvm/docs/CommandGuide/llvm-mca.rst

 """"""""""""""""""""""""""""""""""""
 In-order processors are modelled as a single ``InOrderIssueStage`` stage. It
 bypasses Dispatch, Scheduler and Load/Store unit. Instructions are issued as
 soon as their operand registers are available and resource requirements are
 met. Multiple instructions can be issued in one cycle according to the value of
 the ``IssueWidth`` parameter in LLVM's scheduling model.
 
 Once issued, an instruction is moved to ``IssuedInst`` set until it is ready to
-retire. If ``RetireControlUnit`` is defined in the LLVM's scheduling model,
-:program:`llvm-mca` ensures that instructions are retired in-order. However, an
-instruction is allowed to retire out-of-order if ``RetireOOO`` property is true
-for at least one of its writes.
+retire. :program:`llvm-mca` ensures that writes are committed in-order. However,
+an instruction is allowed to commit writes and retire out-of-order if
+``RetireOOO`` property is true for at least one of its writes.

llvm/include/llvm/MCA/Stages/InOrderIssueStage.h

 
 namespace llvm {
 struct MCSchedModel;
 class MCSubtargetInfo;
 
 namespace mca {
 class RegisterFile;
 class ResourceManager;
-struct RetireControlUnit;
 
 class InOrderIssueStage final : public Stage {
   const MCSchedModel &SM;
   const MCSubtargetInfo &STI;
-  RetireControlUnit &RCU;
   RegisterFile &PRF;
   std::unique_ptr<ResourceManager> RM;
 
   /// Instructions that were issued, but not executed yet.
   SmallVector<InstRef, 4> IssuedInst;
 
   /// Number of instructions issued in the current cycle.
   unsigned NumIssued;
class InOrderIssueStage final : public Stage {
   /// false. StallCycles is set to the number of cycles left before the
   /// instruction can be issued.
   bool canExecute(const InstRef &IR, unsigned *StallCycles) const;
 
   /// Issue the instruction, or update StallCycles if IR is stalled.
   Error tryIssue(InstRef &IR, unsigned *StallCycles);
 
   /// Update status of instructions from IssuedInst.
-  Error updateIssuedInst();
+  void updateIssuedInst();
+
+  /// Retire instruction once it is executed.
+  void retireInstruction(InstRef &IR);
 
 public:
-  InOrderIssueStage(RetireControlUnit &RCU, RegisterFile &PRF,
-                    const MCSchedModel &SM, const MCSubtargetInfo &STI)
-      : SM(SM), STI(STI), RCU(RCU), PRF(PRF),
-        RM(std::make_unique<ResourceManager>(SM)), NumIssued(0),
-        StallCyclesLeft(0), Bandwidth(0), LastWriteBackCycle(0) {}
+  InOrderIssueStage(RegisterFile &PRF, const MCSchedModel &SM,
+                    const MCSubtargetInfo &STI)
+      : SM(SM), STI(STI), PRF(PRF), RM(std::make_unique<ResourceManager>(SM)),
+        NumIssued(0), StallCyclesLeft(0), Bandwidth(0),
+        LastWriteBackCycle(0) {}
 
   bool isAvailable(const InstRef &) const override;
   bool hasWorkToComplete() const override;
   Error execute(InstRef &IR) override;
   Error cycleStart() override;
   Error cycleEnd() override;
 };
 
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_IN_ORDER_ISSUE_STAGE_H

llvm/lib/MCA/Context.cpp

Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
   StagePipeline->appendStage(std::move(Execute));
   StagePipeline->appendStage(std::move(Retire));
   return StagePipeline;
 }
 
 std::unique_ptr<Pipeline>
 Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();
-  auto RCU = std::make_unique<RetireControlUnit>(SM);
   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
-  auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
-                                      Opts.StoreQueueSize, Opts.AssumeNoAlias);
 
   auto Entry = std::make_unique<EntryStage>(SrcMgr);
-  auto InOrderIssue = std::make_unique<InOrderIssueStage>(*RCU, *PRF, SM, STI);
-  auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
+  auto InOrderIssue = std::make_unique<InOrderIssueStage>(*PRF, SM, STI);
 
   auto StagePipeline = std::make_unique<Pipeline>();
   StagePipeline->appendStage(std::move(Entry));
   StagePipeline->appendStage(std::move(InOrderIssue));
-  StagePipeline->appendStage(std::move(Retire));
 
-  addHardwareUnit(std::move(RCU));
   addHardwareUnit(std::move(PRF));
-  addHardwareUnit(std::move(LSU));
 
   return StagePipeline;
 }
 
 } // namespace mca
 } // namespace llvm

llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp

 
 namespace llvm {
 namespace mca {
 
 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
       AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
       MaxRetirePerCycle(0) {
+  assert(SM.isOutOfOrder() &&
+         "RetireControlUnit is not available for in-order processors");
   // Check if the scheduling model provides extra information about the machine
   // processor. If so, then use that information to set the reorder buffer size
   // and the maximum number of instructions retired per cycle.
   if (SM.hasExtraProcessorInfo()) {
     const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
     if (EPI.ReorderBufferSize)
       AvailableEntries = EPI.ReorderBufferSize;
     MaxRetirePerCycle = EPI.MaxRetirePerCycle;
   }
   NumROBEntries = AvailableEntries;
-  if (!SM.isOutOfOrder() && !NumROBEntries)
-    return;
   assert(NumROBEntries && "Invalid reorder buffer size!");
   Queue.resize(2 * NumROBEntries);
 }
 
 // Reserves a number of slots, and returns a new token.
 unsigned RetireControlUnit::dispatch(const InstRef &IR) {
-  if (!NumROBEntries)
-    return UnhandledTokenID;
-
   const Instruction &Inst = *IR.getInstruction();
   unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
   assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
 
   unsigned TokenID = NextAvailableSlotIdx;
   Queue[NextAvailableSlotIdx] = {IR, Entries, false};
   NextAvailableSlotIdx += std::max(1U, Entries);
   NextAvailableSlotIdx %= Queue.size();

llvm/lib/MCA/Stages/InOrderIssueStage.cpp

static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS,
 
   for (ReadState &RS : IS.getUses())
     PRF.addRegisterRead(RS, STI);
 
   for (WriteState &WS : IS.getDefs())
     PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs);
 }
 
-static void notifyInstructionExecute(
+static void notifyInstructionIssue(
     const InstRef &IR,
     const SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedRes,
     const Stage &S) {
 
   S.notifyEvent<HWInstructionEvent>(
       HWInstructionEvent(HWInstructionEvent::Ready, IR));
   S.notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, UsedRes));
 
   LLVM_DEBUG(dbgs() << "[E] Issued #" << IR << "\n");
 }
 
 static void notifyInstructionDispatch(const InstRef &IR, unsigned Ops,
                                       const SmallVectorImpl<unsigned> &UsedRegs,
                                       const Stage &S) {
 
   S.notifyEvent<HWInstructionEvent>(
       HWInstructionDispatchedEvent(IR, UsedRegs, Ops));
 
   LLVM_DEBUG(dbgs() << "[E] Dispatched #" << IR << "\n");
 }
 
 llvm::Error InOrderIssueStage::execute(InstRef &IR) {
-  Instruction &IS = *IR.getInstruction();
-  const InstrDesc &Desc = IS.getDesc();
-
-  unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
-  if (!Desc.RetireOOO)
-    RCUTokenID = RCU.dispatch(IR);
-  IS.dispatch(RCUTokenID);
-
-  if (Desc.EndGroup) {
-    Bandwidth = 0;
-  } else {
-    unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps();
-    assert(Bandwidth >= NumMicroOps);
-    Bandwidth -= NumMicroOps;
-  }
-
   if (llvm::Error E = tryIssue(IR, &StallCyclesLeft))
     return E;
 
   if (StallCyclesLeft) {
     StalledInst = IR;
-    Bandwidth = 0;
   }
 
   return llvm::ErrorSuccess();
 }
 
 llvm::Error InOrderIssueStage::tryIssue(InstRef &IR, unsigned *StallCycles) {
   Instruction &IS = *IR.getInstruction();
   unsigned SourceIndex = IR.getSourceIndex();
+  const InstrDesc &Desc = IS.getDesc();
 
   if (!canExecute(IR, StallCycles)) {
     LLVM_DEBUG(dbgs() << "[E] Stalled #" << IR << " for " << *StallCycles
                       << " cycles\n");
+    Bandwidth = 0;
     return llvm::ErrorSuccess();
   }
 
+  unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
+  IS.dispatch(RCUTokenID);
+
   SmallVector<unsigned, 4> UsedRegs(PRF.getNumRegisterFiles());
   addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs);
 
-  notifyInstructionDispatch(IR, IS.getDesc().NumMicroOps, UsedRegs, *this);
+  unsigned NumMicroOps = IS.getNumMicroOps();
+  notifyInstructionDispatch(IR, NumMicroOps, UsedRegs, *this);
 
   SmallVector<std::pair<ResourceRef, ResourceCycles>, 4> UsedResources;
-  RM->issueInstruction(IS.getDesc(), UsedResources);
+  RM->issueInstruction(Desc, UsedResources);
   IS.execute(SourceIndex);
 
   // Replace resource masks with valid resource processor IDs.
   for (std::pair<ResourceRef, ResourceCycles> &Use : UsedResources) {
     uint64_t Mask = Use.first.first;
     Use.first.first = RM->resolveResourceMask(Mask);
   }
-  notifyInstructionExecute(IR, UsedResources, *this);
+  notifyInstructionIssue(IR, UsedResources, *this);
+
+  if (Desc.EndGroup) {
+    Bandwidth = 0;
+  } else {
+    assert(Bandwidth >= NumMicroOps);
+    Bandwidth -= NumMicroOps;
+  }
 
   IssuedInst.push_back(IR);
-  ++NumIssued;
+  NumIssued += NumMicroOps;
 
   if (!IR.getInstruction()->getDesc().RetireOOO)
     LastWriteBackCycle = findLastWriteBackCycle(IR);
 
   return llvm::ErrorSuccess();
 }
 
-llvm::Error InOrderIssueStage::updateIssuedInst() {
+void InOrderIssueStage::updateIssuedInst() {
   // Update other instructions. Executed instructions will be retired during the
   // next cycle.
   unsigned NumExecuted = 0;
   for (auto I = IssuedInst.begin(), E = IssuedInst.end();
        I != (E - NumExecuted);) {
     InstRef &IR = *I;
     Instruction &IS = *IR.getInstruction();
 
     IS.cycleEvent();
     if (!IS.isExecuted()) {
       LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR
                         << " is still executing\n");
       ++I;
       continue;
     }
     notifyEvent<HWInstructionEvent>(
         HWInstructionEvent(HWInstructionEvent::Executed, IR));
 
     LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
     ++NumExecuted;
     std::iter_swap(I, E - NumExecuted);
   }
 
-  // Retire instructions in the next cycle
   if (NumExecuted) {
-    for (auto I = IssuedInst.end() - NumExecuted, E = IssuedInst.end(); I != E;
-         ++I) {
-      if (llvm::Error E = moveToTheNextStage(*I))
-        return E;
+    for (auto I = IssuedInst.end() - NumExecuted, E = IssuedInst.end();
+         I != E; ++I) {
+      retireInstruction(*I);
     }
     IssuedInst.resize(IssuedInst.size() - NumExecuted);
   }
+}
 
-  return llvm::ErrorSuccess();
+void InOrderIssueStage::retireInstruction(InstRef &IR) {
+  Instruction &IS = *IR.getInstruction();
+  IS.retire();
+
+  llvm::SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
+  for (const WriteState &WS : IS.getDefs())
+    PRF.removeRegisterWrite(WS, FreedRegs);
+
+  notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
+  LLVM_DEBUG(dbgs() << "[E] Retired #" << IR << " \n");
 }
 
 llvm::Error InOrderIssueStage::cycleStart() {
   NumIssued = 0;
+  Bandwidth = SM.IssueWidth;
 
   // Release consumed resources.
   SmallVector<ResourceRef, 4> Freed;
   RM->cycleEvent(Freed);
 
-  if (llvm::Error E = updateIssuedInst())
-    return E;
+  updateIssuedInst();
 
   // Issue instructions scheduled for this cycle
   if (!StallCyclesLeft && StalledInst) {
     if (llvm::Error E = tryIssue(StalledInst, &StallCyclesLeft))
       return E;
   }
 
   if (!StallCyclesLeft) {
     StalledInst.invalidate();
     assert(NumIssued <= SM.IssueWidth && "Overflow.");
-    Bandwidth = SM.IssueWidth - NumIssued;
   } else {
     // The instruction is still stalled, cannot issue any new instructions in
     // this cycle.
     Bandwidth = 0;
   }
 
   return llvm::ErrorSuccess();
 }

llvm/lib/Target/AArch64/AArch64SchedA55.td

 def : InstRW<[CortexA55WriteFDivDP], (instrs FDIVDrr)>;
 def : InstRW<[CortexA55WriteFDivHP], (instregex "^FDIVv.*16$")>;
 def : InstRW<[CortexA55WriteFDivSP], (instregex "^FDIVv.*32$")>;
 def : InstRW<[CortexA55WriteFDivDP], (instregex "^FDIVv.*64$")>;
 def : InstRW<[CortexA55WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;
 def : InstRW<[CortexA55WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
 def : InstRW<[CortexA55WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
 
-def A55RCU : RetireControlUnit<64, 0>;
 }

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --timeline --iterations=2 < %s | FileCheck %s
 
 add      w2, w3, #1
 add      w4, w3, #2, lsl #12
 add      w0, w4, #3
 add      w1, w0, #4
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      8
-# CHECK-NEXT: Total Cycles:      10
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        8
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.80
-# CHECK-NEXT: IPC:               0.80
+# CHECK-NEXT: uOps Per Cycle:    0.89
+# CHECK-NEXT: IPC:               0.89
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3.0]  [3.1]  [4]    [5.0]  [5.1]  [6]    [7]    [8]    Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -     add w2, w3, #1
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -     add w4, w3, #2, lsl #12
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -     add w0, w4, #3
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -     add w1, w0, #4
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeeER.   .   add  w2, w3, #1
-# CHECK-NEXT: [0,1]     DeeER.   .   add  w4, w3, #2, lsl #12
-# CHECK-NEXT: [0,2]     .DeeER   .   add  w0, w4, #3
-# CHECK-NEXT: [0,3]     . DeeER  .   add  w1, w0, #4
-# CHECK-NEXT: [1,0]     . DeeER  .   add  w2, w3, #1
-# CHECK-NEXT: [1,1]     .  DeeER .   add  w4, w3, #2, lsl #12
-# CHECK-NEXT: [1,2]     .   DeeER.   add  w0, w4, #3
-# CHECK-NEXT: [1,3]     .    DeeER   add  w1, w0, #4
+# CHECK:      [0,0]     DeeE .  .   add w2, w3, #1
+# CHECK-NEXT: [0,1]     DeeE .  .   add w4, w3, #2, lsl #12
+# CHECK-NEXT: [0,2]     .DeeE.  .   add w0, w4, #3
+# CHECK-NEXT: [0,3]     . DeeE  .   add w1, w0, #4
+# CHECK-NEXT: [1,0]     . DeeE  .   add w2, w3, #1
+# CHECK-NEXT: [1,1]     .  DeeE .   add w4, w3, #2, lsl #12
+# CHECK-NEXT: [1,2]     .   DeeE.   add w0, w4, #3
+# CHECK-NEXT: [1,3]     .    DeeE   add w1, w0, #4
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     0.0    0.0    0.0       add  w2, w3, #1
 # CHECK-NEXT: 1.     2     0.0    0.0    0.0       add  w4, w3, #2, lsl #12
 # CHECK-NEXT: 2.     2     0.0    0.0    0.0       add  w0, w4, #3
 # CHECK-NEXT: 3.     2     0.0    0.0    0.0       add  w1, w0, #4
 # CHECK-NEXT:        2     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s
 
 ldr w4, [x2], #4
 ldr w5, [x3]
 madd  w0, w5, w4, w0
 add x3, x3, x13
 subs  x1, x1, #1
 str  w0, [x21, x18, lsl #2]
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      12
-# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total Cycles:      20
 # CHECK-NEXT: Total uOps:        14
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.67
-# CHECK-NEXT: IPC:               0.57
+# CHECK-NEXT: uOps Per Cycle:    0.70
+# CHECK-NEXT: IPC:               0.60
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  2      3     1.00    *                   ldr w4, [x2], #4
 # CHECK-NEXT:  1      3     1.00    *                   ldr w5, [x3]
 # CHECK-NEXT:  1      4     1.00                        madd  w0, w5, w4, w0
 # CHECK-NEXT:  1      3     0.50                        add x3, x3, x13
 # CHECK-NEXT:  1      3     0.50                        subs  x1, x1, #1
 # CHECK-NEXT:  1      4     1.00           *            str w0, [x21, x18, lsl #2]
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT     - Register unavailable:                      8  (38.1%)
+# CHECK-NEXT: RAT     - Register unavailable:                      8  (40.0%)
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              11  (52.4%)
-# CHECK-NEXT:  1,              6  (28.6%)
-# CHECK-NEXT:  2,              4  (19.0%)
+# CHECK-NEXT:  0,              10  (50.0%)
+# CHECK-NEXT:  1,              6  (30.0%)
+# CHECK-NEXT:  2,              4  (20.0%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          11  (52.4%)
-# CHECK-NEXT:  1,          6  (28.6%)
-# CHECK-NEXT:  2,          4  (19.0%)
+# CHECK-NEXT:  0,          10  (50.0%)
+# CHECK-NEXT:  1,          6  (30.0%)
+# CHECK-NEXT:  2,          4  (20.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: No scheduler resources used.
 
-# CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
-# CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           14  (66.7%)
-# CHECK-NEXT:  1,           4  (19.0%)
-# CHECK-NEXT:  2,           1  (4.8%)
-# CHECK-NEXT:  3,           2  (9.5%)
-
-# CHECK:      Total ROB Entries:                64
-# CHECK-NEXT: Max Used ROB Entries:             6  ( 9.4% )
-# CHECK-NEXT: Average Used ROB Entries per cy:  2  ( 3.1% )
-
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    14
-# CHECK-NEXT: Max number of mappings used:         6
+# CHECK-NEXT: Max number of mappings used:         4
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - CortexA55UnitALU
 # CHECK-NEXT: [0.1] - CortexA55UnitALU
 # CHECK-NEXT: [1]   - CortexA55UnitB
 # CHECK-NEXT: [2]   - CortexA55UnitDiv
 # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
 # CHECK-NEXT: [3.1] - CortexA55UnitFPALU

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views --iterations=2 < %s | FileCheck %s
 
 ldr w4, [x2], #4
 ldr w5, [x3]
 madd  w0, w5, w4, w0
 add x3, x3, x13
 subs  x1, x1, #1
 str  w0, [x21, x18, lsl #2]
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      12
-# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total Cycles:      20
 # CHECK-NEXT: Total uOps:        14
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.67
-# CHECK-NEXT: IPC:               0.57
+# CHECK-NEXT: uOps Per Cycle:    0.70
+# CHECK-NEXT: IPC:               0.60
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  2      3     1.00    *                   ldr w4, [x2], #4
 # CHECK-NEXT:  1      3     1.00    *                   ldr w5, [x3]
 # CHECK-NEXT:  1      4     1.00                        madd  w0, w5, w4, w0
 # CHECK-NEXT:  1      3     0.50                        add x3, x3, x13
 # CHECK-NEXT:  1      3     0.50                        subs  x1, x1, #1
 # CHECK-NEXT:  1      4     1.00           *            str w0, [x21, x18, lsl #2]
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT     - Register unavailable:                      8  (38.1%)
+# CHECK-NEXT: RAT     - Register unavailable:                      8  (40.0%)
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              11  (52.4%)
-# CHECK-NEXT:  1,              6  (28.6%)
-# CHECK-NEXT:  2,              4  (19.0%)
+# CHECK-NEXT:  0,              10  (50.0%)
+# CHECK-NEXT:  1,              6  (30.0%)
+# CHECK-NEXT:  2,              4  (20.0%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          11  (52.4%)
-# CHECK-NEXT:  1,          6  (28.6%)
-# CHECK-NEXT:  2,          4  (19.0%)
+# CHECK-NEXT:  0,          10  (50.0%)
+# CHECK-NEXT:  1,          6  (30.0%)
+# CHECK-NEXT:  2,          4  (20.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: No scheduler resources used.
 
-# CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
-# CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           14  (66.7%)
-# CHECK-NEXT:  1,           4  (19.0%)
-# CHECK-NEXT:  2,           1  (4.8%)
-# CHECK-NEXT:  3,           2  (9.5%)
-
-# CHECK:      Total ROB Entries:                64
-# CHECK-NEXT: Max Used ROB Entries:             6  ( 9.4% )
-# CHECK-NEXT: Average Used ROB Entries per cy:  2  ( 3.1% )
-
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    14
-# CHECK-NEXT: Max number of mappings used:         6
+# CHECK-NEXT: Max number of mappings used:         4
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - CortexA55UnitALU
 # CHECK-NEXT: [0.1] - CortexA55UnitALU
 # CHECK-NEXT: [1]   - CortexA55UnitB
 # CHECK-NEXT: [2]   - CortexA55UnitDiv
 # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
 # CHECK-NEXT: [3.1] - CortexA55UnitFPALU

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -     ldr w5, [x3]
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00    -     madd  w0, w5, w4, w0
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -     add x3, x3, x13
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -     subs  x1, x1, #1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     1.00   str w0, [x21, x18, lsl #2]
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .    .    .   ldr w4, [x2], #4
-# CHECK-NEXT: [0,1]     .DeeER    .    .    .   ldr w5, [x3]
-# CHECK-NEXT: [0,2]     .   DeeeER.    .    .   madd  w0, w5, w4, w0
-# CHECK-NEXT: [0,3]     .    DeeER.    .    .   add x3, x3, x13
-# CHECK-NEXT: [0,4]     .    DeeER.    .    .   subs  x1, x1, #1
-# CHECK-NEXT: [0,5]     .    . DeeeER  .    .   str w0, [x21, x18, lsl #2]
-# CHECK-NEXT: [1,0]     .    .  DeeER  .    .   ldr w4, [x2], #4
-# CHECK-NEXT: [1,1]     .    .   DeeER .    .   ldr w5, [x3]
-# CHECK-NEXT: [1,2]     .    .    . DeeeER  .   madd  w0, w5, w4, w0
-# CHECK-NEXT: [1,3]     .    .    .  DeeER  .   add x3, x3, x13
-# CHECK-NEXT: [1,4]     .    .    .  DeeER  .   subs  x1, x1, #1
-# CHECK-NEXT: [1,5]     .    .    .    DeeeER   str w0, [x21, x18, lsl #2]
+# CHECK:      [0,0]     DeeE .    .    .   .   ldr  w4, [x2], #4
+# CHECK-NEXT: [0,1]     .DeeE.    .    .   .   ldr  w5, [x3]
+# CHECK-NEXT: [0,2]     .   DeeeE .    .   .   madd w0, w5, w4, w0
+# CHECK-NEXT: [0,3]     .    DeeE .    .   .   add  x3, x3, x13
+# CHECK-NEXT: [0,4]     .    DeeE .    .   .   subs x1, x1, #1
+# CHECK-NEXT: [0,5]     .    . DeeeE   .   .   str  w0, [x21, x18, lsl #2]
+# CHECK-NEXT: [1,0]     .    .  DeeE   .   .   ldr  w4, [x2], #4
+# CHECK-NEXT: [1,1]     .    .   DeeE  .   .   ldr  w5, [x3]
+# CHECK-NEXT: [1,2]     .    .    . DeeeE  .   madd w0, w5, w4, w0
+# CHECK-NEXT: [1,3]     .    .    .  DeeE  .   add  x3, x3, x13
+# CHECK-NEXT: [1,4]     .    .    .  DeeE  .   subs x1, x1, #1
+# CHECK-NEXT: [1,5]     .    .    .    DeeeE   str  w0, [x21, x18, lsl #2]
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     0.0    0.0    0.0       ldr  w4, [x2], #4
 # CHECK-NEXT: 1.     2     0.0    0.0    0.0       ldr  w5, [x3]
 # CHECK-NEXT: 2.     2     0.0    0.0    0.0       madd w0, w5, w4, w0
 # CHECK-NEXT: 3.     2     0.0    0.0    0.0       add  x3, x3, x13
 # CHECK-NEXT: 4.     2     0.0    0.0    0.0       subs x1, x1, #1
 # CHECK-NEXT: 5.     2     0.0    0.0    0.0       str  w0, [x21, x18, lsl #2]
 # CHECK-NEXT:        2     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s
 
 sdiv  w12, w21, w0
 add w8, w8, #1
 add w1, w2, w0
 add w3, w4, #1
 add w5, w6, w0
 add w7, w9, w0
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      12
-# CHECK-NEXT: Total Cycles:      20
+# CHECK-NEXT: Total Cycles:      19
 # CHECK-NEXT: Total uOps:        12
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.60
-# CHECK-NEXT: IPC:               0.60
+# CHECK-NEXT: uOps Per Cycle:    0.63
+# CHECK-NEXT: IPC:               0.63
 # CHECK-NEXT: Block RThroughput: 8.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      8     8.00                        sdiv  w12, w21, w0
 # CHECK-NEXT:  1      3     0.50                        add w8, w8, #1
 # CHECK-NEXT:  1      3     0.50                        add w1, w2, w0
 # CHECK-NEXT:  1      3     0.50                        add w3, w4, #1
 # CHECK-NEXT:  1      3     0.50                        add w5, w6, w0
 # CHECK-NEXT:  1      3     0.50                        add w7, w9, w0
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
-# CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 1  (5.0%)
+# CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 1  (5.3%)
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              12  (60.0%)
-# CHECK-NEXT:  1,              4  (20.0%)
-# CHECK-NEXT:  2,              4  (20.0%)
+# CHECK-NEXT:  0,              11  (57.9%)
+# CHECK-NEXT:  1,              4  (21.1%)
+# CHECK-NEXT:  2,              4  (21.1%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          12  (60.0%)
-# CHECK-NEXT:  1,          4  (20.0%)
-# CHECK-NEXT:  2,          4  (20.0%)
+# CHECK-NEXT:  0,          11  (57.9%)
+# CHECK-NEXT:  1,          4  (21.1%)
+# CHECK-NEXT:  2,          4  (21.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: No scheduler resources used.
 
-# CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
-# CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           14  (70.0%)
-# CHECK-NEXT:  1,           2  (10.0%)
-# CHECK-NEXT:  2,           2  (10.0%)
-# CHECK-NEXT:  3,           2  (10.0%)
-
-# CHECK:      Total ROB Entries:                64
-# CHECK-NEXT: Max Used ROB Entries:             7  ( 10.9% )
-# CHECK-NEXT: Average Used ROB Entries per cy:  2  ( 3.1% )
-
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    12
-# CHECK-NEXT: Max number of mappings used:         7
+# CHECK-NEXT: Max number of mappings used:         6
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - CortexA55UnitALU
 # CHECK-NEXT: [0.1] - CortexA55UnitALU
 # CHECK-NEXT: [1]   - CortexA55UnitB
 # CHECK-NEXT: [2]   - CortexA55UnitDiv
 # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
 # CHECK-NEXT: [3.1] - CortexA55UnitFPALU

 # CHECK-NEXT:  -      -      -     8.00    -      -      -      -      -      -      -      -     sdiv  w12, w21, w0
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w8, w8, #1
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w1, w2, w0
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w3, w4, #1
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w5, w6, w0
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w7, w9, w0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789
+# CHECK-NEXT:                     012345678
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeeER.    .   .   sdiv w12, w21, w0
-# CHECK-NEXT: [0,1]     .    DeeER.    .   .   add  w8, w8, #1
-# CHECK-NEXT: [0,2]     .    DeeER.    .   .   add  w1, w2, w0
-# CHECK-NEXT: [0,3]     .    .DeeER    .   .   add  w3, w4, #1
-# CHECK-NEXT: [0,4]     .    .DeeER    .   .   add  w5, w6, w0
-# CHECK-NEXT: [0,5]     .    . DeeER   .   .   add  w7, w9, w0
-# CHECK-NEXT: [1,0]     .    .  DeeeeeeeER .   sdiv w12, w21, w0
-# CHECK-NEXT: [1,1]     .    .    .  DeeER .   add  w8, w8, #1
-# CHECK-NEXT: [1,2]     .    .    .  DeeER .   add  w1, w2, w0
-# CHECK-NEXT: [1,3]     .    .    .   DeeER.   add  w3, w4, #1
-# CHECK-NEXT: [1,4]     .    .    .   DeeER.   add  w5, w6, w0
-# CHECK-NEXT: [1,5]     .    .    .    DeeER   add  w7, w9, w0
+# CHECK:      [0,0]     DeeeeeeeE .    .  .   sdiv  w12, w21, w0
+# CHECK-NEXT: [0,1]     .    DeeE .    .  .   add w8, w8, #1
+# CHECK-NEXT: [0,2]     .    DeeE .    .  .   add w1, w2, w0
+# CHECK-NEXT: [0,3]     .    .DeeE.    .  .   add w3, w4, #1
+# CHECK-NEXT: [0,4]     .    .DeeE.    .  .   add w5, w6, w0
+# CHECK-NEXT: [0,5]     .    . DeeE    .  .   add w7, w9, w0
+# CHECK-NEXT: [1,0]     .    .  DeeeeeeeE .   sdiv  w12, w21, w0
+# CHECK-NEXT: [1,1]     .    .    .  DeeE .   add w8, w8, #1
+# CHECK-NEXT: [1,2]     .    .    .  DeeE .   add w1, w2, w0
+# CHECK-NEXT: [1,3]     .    .    .   DeeE.   add w3, w4, #1
+# CHECK-NEXT: [1,4]     .    .    .   DeeE.   add w5, w6, w0
+# CHECK-NEXT: [1,5]     .    .    .    DeeE   add w7, w9, w0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     0.0    0.0    0.0       sdiv w12, w21, w0
 # CHECK-NEXT: 1.     2     0.0    0.0    0.0       add  w8, w8, #1
 # CHECK-NEXT: 2.     2     0.0    0.0    0.0       add  w1, w2, w0
 # CHECK-NEXT: 3.     2     0.0    0.0    0.0       add  w3, w4, #1
 # CHECK-NEXT: 4.     2     0.0    0.0    0.0       add  w5, w6, w0
 # CHECK-NEXT: 5.     2     0.0    0.0    0.0       add  w7, w9, w0
 # CHECK-NEXT:        2     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s
 
 fdiv  s1, s2, s3
 add w8, w8, #1
 add w1, w2, w0
 add w3, w4, #1
 add w5, w6, w0
 add w7, w9, w0
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      12
-# CHECK-NEXT: Total Cycles:      25
+# CHECK-NEXT: Total Cycles:      24
 # CHECK-NEXT: Total uOps:        12
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.48
-# CHECK-NEXT: IPC:               0.48
+# CHECK-NEXT: uOps Per Cycle:    0.50
+# CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 10.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      13    10.00                       fdiv  s1, s2, s3
 # CHECK-NEXT:  1      3     0.50                        add w8, w8, #1
 # CHECK-NEXT:  1      3     0.50                        add w1, w2, w0
 # CHECK-NEXT:  1      3     0.50                        add w3, w4, #1
 # CHECK-NEXT:  1      3     0.50                        add w5, w6, w0
 # CHECK-NEXT:  1      3     0.50                        add w7, w9, w0
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
-# CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 7  (28.0%)
+# CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 7  (29.2%)
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              19  (76.0%)
-# CHECK-NEXT:  2,              6  (24.0%)
+# CHECK-NEXT:  0,              18  (75.0%)
+# CHECK-NEXT:  2,              6  (25.0%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          19  (76.0%)
-# CHECK-NEXT:  2,          6  (24.0%)
+# CHECK-NEXT:  0,          18  (75.0%)
+# CHECK-NEXT:  2,          6  (25.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: No scheduler resources used.
 
-# CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
-# CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           18  (72.0%)
-# CHECK-NEXT:  1,           2  (8.0%)
-# CHECK-NEXT:  2,           5  (20.0%)
-
-# CHECK:      Total ROB Entries:                64
-# CHECK-NEXT: Max Used ROB Entries:             7  ( 10.9% )
-# CHECK-NEXT: Average Used ROB Entries per cy:  2  ( 3.1% )
-
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    12
 # CHECK-NEXT: Max number of mappings used:         7
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - CortexA55UnitALU
 # CHECK-NEXT: [0.1] - CortexA55UnitALU
 # CHECK-NEXT: [1]   - CortexA55UnitB

 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w8, w8, #1
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w1, w2, w0
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w3, w4, #1
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w5, w6, w0
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -      -      -      -      -     add w7, w9, w0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          01234
+# CHECK-NEXT: Index     0123456789          0123
 
-# CHECK:      [0,0]     DeeeeeeeeeeeeER.    .   .   fdiv  s1, s2, s3
-# CHECK-NEXT: [0,1]     DeeER.    .    .    .   .   add w8, w8, #1
-# CHECK-NEXT: [0,2]     .DeeER    .    .    .   .   add w1, w2, w0
-# CHECK-NEXT: [0,3]     .DeeER    .    .    .   .   add w3, w4, #1
-# CHECK-NEXT: [0,4]     . DeeER   .    .    .   .   add w5, w6, w0
-# CHECK-NEXT: [0,5]     . DeeER   .    .    .   .   add w7, w9, w0
-# CHECK-NEXT: [1,0]     .    .    DeeeeeeeeeeeeER   fdiv  s1, s2, s3
-# CHECK-NEXT: [1,1]     .    .    DeeER.    .   .   add w8, w8, #1
-# CHECK-NEXT: [1,2]     .    .    .DeeER    .   .   add w1, w2, w0
-# CHECK-NEXT: [1,3]     .    .    .DeeER    .   .   add w3, w4, #1
-# CHECK-NEXT: [1,4]     .    .    . DeeER   .   .   add w5, w6, w0
-# CHECK-NEXT: [1,5]     .    .    . DeeER   .   .   add w7, w9, w0
+# CHECK:      [0,0]     DeeeeeeeeeeeeE .    .  .   fdiv s1, s2, s3
+# CHECK-NEXT: [0,1]     DeeE .    .    .    .  .   add  w8, w8, #1
+# CHECK-NEXT: [0,2]     .DeeE.    .    .    .  .   add  w1, w2, w0
+# CHECK-NEXT: [0,3]     .DeeE.    .    .    .  .   add  w3, w4, #1
+# CHECK-NEXT: [0,4]     . DeeE    .    .    .  .   add  w5, w6, w0
+# CHECK-NEXT: [0,5]     . DeeE    .    .    .  .   add  w7, w9, w0
+# CHECK-NEXT: [1,0]     .    .    DeeeeeeeeeeeeE   fdiv s1, s2, s3
+# CHECK-NEXT: [1,1]     .    .    DeeE .    .  .   add  w8, w8, #1
+# CHECK-NEXT: [1,2]     .    .    .DeeE.    .  .   add  w1, w2, w0
+# CHECK-NEXT: [1,3]     .    .    .DeeE.    .  .   add  w3, w4, #1
+# CHECK-NEXT: [1,4]     .    .    . DeeE    .  .   add  w5, w6, w0
+# CHECK-NEXT: [1,5]     .    .    . DeeE    .  .   add  w7, w9, w0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     0.0    0.0    0.0       fdiv s1, s2, s3
 # CHECK-NEXT: 1.     2     0.0    0.0    0.0       add  w8, w8, #1
 # CHECK-NEXT: 2.     2     0.0    0.0    0.0       add  w1, w2, w0
 # CHECK-NEXT: 3.     2     0.0    0.0    0.0       add  w3, w4, #1
 # CHECK-NEXT: 4.     2     0.0    0.0    0.0       add  w5, w6, w0
 # CHECK-NEXT: 5.     2     0.0    0.0    0.0       add  w7, w9, w0
 # CHECK-NEXT:        2     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s
 
 v_add_f32 v0, v0, v0
 v_add_f32 v1, v1, v1
 v_add_f32 v2, v1, v0
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    1
-# CHECK-NEXT: uOps Per Cycle:    0.23
-# CHECK-NEXT: IPC:               0.23
+# CHECK-NEXT: uOps Per Cycle:    0.25
+# CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -     v_add_f32_e32 v0, v0, v0
 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -     v_add_f32_e32 v1, v1, v1
 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -     v_add_f32_e32 v2, v1, v0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeER   . .   v_add_f32_e32 v0, v0, v0
-# CHECK-NEXT: [0,1]     .DeeeeER  . .   v_add_f32_e32 v1, v1, v1
-# CHECK-NEXT: [0,2]     .    .DeeeeER   v_add_f32_e32 v2, v1, v0
+# CHECK:      [0,0]     DeeeeE    ..   v_add_f32_e32 v0, v0, v0
+# CHECK-NEXT: [0,1]     .DeeeeE   ..   v_add_f32_e32 v1, v1, v1
+# CHECK-NEXT: [0,2]     .    .DeeeeE   v_add_f32_e32 v2, v1, v0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       v_add_f32_e32 v0, v0, v0
 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       v_add_f32_e32 v1, v1, v1
 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       v_add_f32_e32 v2, v1, v0
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=arm -mcpu=cortex-m7 --timeline --iterations=1 < %s | FileCheck %s
 
 add r1, r1, #1
 # ReadAdvance: 0
 add r1, r1, #2
 # ReadAdvance: -1
 vldr d0, [r1]
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      7
+# CHECK-NEXT: Total Cycles:      5
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.43
-# CHECK-NEXT: IPC:               0.43
+# CHECK-NEXT: uOps Per Cycle:    0.60
+# CHECK-NEXT: IPC:               0.60
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2.0]  [2.1]  [3]    [4]    [5]    [6]    [7]    [8]    [9.0]  [9.1]  Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     add.w  r1, r1, #1
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     add.w  r1, r1, #2
 # CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -      -      -      -     2.00   vldr d0, [r1]
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234
 
-# CHECK:      [0,0]     DER  ..   add.w r1, r1, #1
-# CHECK-NEXT: [0,1]     .DER ..   add.w r1, r1, #2
-# CHECK-NEXT: [0,2]     .  DeER   vldr  d0, [r1]
+# CHECK:      [0,0]     DE  .   add.w r1, r1, #1
+# CHECK-NEXT: [0,1]     .DE .   add.w r1, r1, #2
+# CHECK-NEXT: [0,2]     . DeE   vldr  d0, [r1]
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       add.w  r1, r1, #1
 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       add.w  r1, r1, #2
 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vldr d0, [r1]
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/tools/llvm-mca/Views/TimelineView.cpp

case HWInstructionEvent::Retired: {
     unsigned CycleDispatched = static_cast<unsigned>(TVEntry.CycleDispatched);
     WaitTimeEntry &WTEntry = WaitTime[Index % getSource().size()];
     WTEntry.CyclesSpentInSchedulerQueue +=
         TVEntry.CycleIssued - CycleDispatched;
     assert(CycleDispatched <= TVEntry.CycleReady &&
            "Instruction cannot be ready if it hasn't been dispatched yet!");
     WTEntry.CyclesSpentInSQWhileReady +=
         TVEntry.CycleIssued - TVEntry.CycleReady;
+    if (CurrentCycle > TVEntry.CycleExecuted) {
       WTEntry.CyclesSpentAfterWBAndBeforeRetire +=
           (CurrentCycle - 1) - TVEntry.CycleExecuted;
+    }
     break;
   }
   case HWInstructionEvent::Ready:
     Timeline[Index].CycleReady = CurrentCycle;
     break;
   case HWInstructionEvent::Issued:
     Timeline[Index].CycleIssued = CurrentCycle;
     break;
else {
            ++I)
         OS << TimelineView::DisplayChar::Executing;
       OS << TimelineView::DisplayChar::Executed;
     }
   }
 
   for (unsigned I = Entry.CycleExecuted + 1, E = Entry.CycleRetired; I < E; ++I)
     OS << TimelineView::DisplayChar::RetireLag;
+  if (Entry.CycleExecuted < Entry.CycleRetired)
     OS << TimelineView::DisplayChar::Retired;
 
   // Skip other columns.
   for (unsigned I = Entry.CycleRetired + 1, E = LastCycle; I <= E; ++I)
     OS << ((I % 5 == 0 || I == LastCycle) ? '.' : ' ');
 }
 
 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) {
   OS << "\n\nTimeline view:\n";

llvm/tools/llvm-mca/llvm-mca.cpp

static void processViewOptions(bool IsOutOfOrder) {
 
   const cl::opt<bool> &Default =
       EnableAllViews.getPosition() < EnableAllStats.getPosition()
           ? EnableAllStats
           : EnableAllViews;
   processOptionImpl(PrintRegisterFileStats, Default);
   processOptionImpl(PrintDispatchStats, Default);
   processOptionImpl(PrintSchedulerStats, Default);
+  if (IsOutOfOrder)
     processOptionImpl(PrintRetireStats, Default);
 }
 
 // Returns true on success.
 static bool runPipeline(mca::Pipeline &P) {
   // Handle pipeline errors here.
   Expected<unsigned> Cycles = P.run();
   if (!Cycles) {
     WithColor::error() << toString(Cycles.takeError());