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Differential D98598

GlobalISel: Preserve source value information for outgoing byval args
ClosedPublic

Authored by arsenm on Mar 14 2021, 8:02 AM.

Details

Reviewers
aemerson
paquette
bogner
aditya_nandakumar
dsanders
Summary

Pass through the original argument IR value in order to preserve the
aliasing information in the memcpy memory operands.

Diff Detail

Event Timeline

arsenm created this revision.Mar 14 2021, 8:02 AM
Herald added subscribers: kerbowa, hiraditya, rovka and 2 others. · View Herald TranscriptMar 14 2021, 8:02 AM
arsenm requested review of this revision.Mar 14 2021, 8:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 14 2021, 8:02 AM
Herald added a subscriber: wdng. · View Herald Transcript
arsenm added a parent revision: D98597: GlobalISel: Insert memcpy for outgoing byval arguments.Mar 14 2021, 8:02 AM
Harbormaster completed remote builds in B93706: Diff 330510.Mar 14 2021, 8:41 AM
aemerson accepted this revision.Mar 15 2021, 9:45 PM
This revision is now accepted and ready to land.Mar 15 2021, 9:45 PM
arsenm closed this revision.Mar 18 2021, 6:17 AM

b9a03849836f6409291025a31089bfabfa96dd0b

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
18 lines
lib/
CodeGen/
GlobalISel/
22 lines
5 lines
Target/
AArch64/
GISel/
2 lines
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
57 lines

Diff 330510

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Show All 16 Lines
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetCallingConv.h" #include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/IR/Attributes.h" #include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h" #include "llvm/IR/CallingConv.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h" #include "llvm/Support/MachineValueType.h"
#include <cstdint> #include <cstdint>
#include <functional> #include <functional>
namespace llvm { namespace llvm {
class CallBase; class CallBase;
class DataLayout; class DataLayout;
class Function; class Function;
class FunctionLoweringInfo; class FunctionLoweringInfo;
class MachineIRBuilder; class MachineIRBuilder;
struct MachinePointerInfo; struct MachinePointerInfo;
class MachineRegisterInfo; class MachineRegisterInfo;
class TargetLowering; class TargetLowering;
class Value;
class CallLowering { class CallLowering {
const TargetLowering *TLI; const TargetLowering *TLI;
virtual void anchor(); virtual void anchor();
public: public:
struct BaseArgInfo { struct BaseArgInfo {
Type *Ty; Type *Ty;
Show All 10 Linespublic:
struct ArgInfo : public BaseArgInfo { struct ArgInfo : public BaseArgInfo {
SmallVector<Register, 4> Regs; SmallVector<Register, 4> Regs;
// If the argument had to be split into multiple parts according to the // If the argument had to be split into multiple parts according to the
// target calling convention, then this contains the original vregs // target calling convention, then this contains the original vregs
// if the argument was an incoming arg. // if the argument was an incoming arg.
SmallVector<Register, 2> OrigRegs; SmallVector<Register, 2> OrigRegs;
/// Optionally track the original IR value for the argument. This may not be
/// meaningful in all contexts. This should only be used on for forwarding
/// through to use for aliasing information in MachinePointerInfo for memory
/// arguments.
const Value *OrigValue = nullptr;
ArgInfo(ArrayRef<Register> Regs, Type *Ty, ArgInfo(ArrayRef<Register> Regs, Type *Ty,
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(), ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
bool IsFixed = true) bool IsFixed = true, const Value *OrigValue = nullptr)
: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()) { : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
OrigValue(OrigValue) {
if (!Regs.empty() && Flags.empty()) if (!Regs.empty() && Flags.empty())
this->Flags.push_back(ISD::ArgFlagsTy()); this->Flags.push_back(ISD::ArgFlagsTy());
// FIXME: We should have just one way of saying "no register". // FIXME: We should have just one way of saying "no register".
assert(((Ty->isVoidTy() || Ty->isEmptyTy()) == assert(((Ty->isVoidTy() || Ty->isEmptyTy()) ==
(Regs.empty() || Regs[0] == 0)) && (Regs.empty() || Regs[0] == 0)) &&
"only void types should have no register"); "only void types should have no register");
} }
ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
bool IsFixed = true)
: ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {}
ArgInfo() : BaseArgInfo() {} ArgInfo() : BaseArgInfo() {}
}; };
struct CallLoweringInfo { struct CallLoweringInfo {
/// Calling convention to be used for the call. /// Calling convention to be used for the call.
CallingConv::ID CallConv = CallingConv::C; CallingConv::ID CallConv = CallingConv::C;
/// Destination of the call. It should be either a register, globaladdress, /// Destination of the call. It should be either a register, globaladdress,
▲ Show 20 Lines • Show All 397 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesbool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
} }
// First step is to marshall all the function's parameters into the correct // First step is to marshall all the function's parameters into the correct
// physregs and memory locations. Gather the sequence of argument types that // physregs and memory locations. Gather the sequence of argument types that
// we'll pass to the assigner function. // we'll pass to the assigner function.
unsigned i = 0; unsigned i = 0;
unsigned NumFixedArgs = CB.getFunctionType()->getNumParams(); unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
for (auto &Arg : CB.args()) { for (auto &Arg : CB.args()) {
ArgInfo OrigArg{ArgRegs[i], Arg->getType(), getAttributesForArgIdx(CB, i), ArgInfo OrigArg{ArgRegs[i], *Arg.get(), getAttributesForArgIdx(CB, i),
i < NumFixedArgs}; i < NumFixedArgs};
setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB); setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB);
// If we have an explicit sret argument that is an Instruction, (i.e., it // If we have an explicit sret argument that is an Instruction, (i.e., it
// might point to function-local memory), we can't meaningfully tail-call. // might point to function-local memory), we can't meaningfully tail-call.
if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg)) if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
CanBeTailCalled = false; CanBeTailCalled = false;
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesvoid CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
if (SplitVTs.size() == 0) if (SplitVTs.size() == 0)
return; return;
if (SplitVTs.size() == 1) { if (SplitVTs.size() == 1) {
// No splitting to do, but we want to replace the original type (e.g. [1 x // No splitting to do, but we want to replace the original type (e.g. [1 x
// double] -> double). // double] -> double).
SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
OrigArg.Flags[0], OrigArg.IsFixed); OrigArg.Flags[0], OrigArg.IsFixed,
OrigArg.OrigValue);
return; return;
} }
// Create one ArgInfo for each virtual register in the original ArgInfo. // Create one ArgInfo for each virtual register in the original ArgInfo.
assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
OrigArg.Ty, CallConv, false); OrigArg.Ty, CallConv, false);
▲ Show 20 Lines • Show All 446 Lines • ▼ Show 20 Lines for (unsigned Part = 0; Part < NumArgRegs; ++Part) {
// value. // value.
uint64_t MemSize = Flags.getByValSize(); uint64_t MemSize = Flags.getByValSize();
int64_t Offset = VA.getLocMemOffset(); int64_t Offset = VA.getLocMemOffset();
MachinePointerInfo DstMPO; MachinePointerInfo DstMPO;
Register StackAddr = Register StackAddr =
Handler.getStackAddress(MemSize, Offset, DstMPO, Flags); Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
MachinePointerInfo SrcMPO(Args[i].OrigValue);
if (!Args[i].OrigValue) {
// We still need to accurately track the stack address space if we
// don't know the underlying value.
const LLT PtrTy = MRI.getType(StackAddr); const LLT PtrTy = MRI.getType(StackAddr);
SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
// FIXME: We do not have access to the original IR value here to }
// preserve the aliasing information.
MachinePointerInfo SrcMPO(PtrTy.getAddressSpace());
Align DstAlign = std::max(Flags.getNonZeroByValAlign(), Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
inferAlignFromPtrInfo(MF, DstMPO)); inferAlignFromPtrInfo(MF, DstMPO));
// TODO: Theoretically the source value could have a higher alignment, Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
// but we don't have that here inferAlignFromPtrInfo(MF, SrcMPO));
Align SrcAlign = Flags.getNonZeroByValAlign();
Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0], Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
DstMPO, DstAlign, SrcMPO, SrcAlign, DstMPO, DstAlign, SrcMPO, SrcAlign,
MemSize, VA); MemSize, VA);
} }
continue; continue;
} }
▲ Show 20 Lines • Show All 403 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 LinesAlign llvm::inferAlignFromPtrInfo(MachineFunction &MF,
const MachinePointerInfo &MPO) { const MachinePointerInfo &MPO) {
auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>(); auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) { if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()), return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
MPO.Offset); MPO.Offset);
} }
if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
const Module *M = MF.getFunction().getParent();
return V->getPointerAlignment(M->getDataLayout());
}
return Align(1); return Align(1);
} }
Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF, Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF,
const TargetInstrInfo &TII, const TargetInstrInfo &TII,
MCRegister PhysReg, MCRegister PhysReg,
const TargetRegisterClass &RC, const TargetRegisterClass &RC,
LLT RegTy) { LLT RegTy) {
▲ Show 20 Lines • Show All 317 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Show First 20 Lines • Show All 444 Lines • ▼ Show 20 Linesbool AArch64CallLowering::lowerFormalArguments(
auto &DL = F.getParent()->getDataLayout(); auto &DL = F.getParent()->getDataLayout();
SmallVector<ArgInfo, 8> SplitArgs; SmallVector<ArgInfo, 8> SplitArgs;
unsigned i = 0; unsigned i = 0;
for (auto &Arg : F.args()) { for (auto &Arg : F.args()) {
if (DL.getTypeStoreSize(Arg.getType()).isZero()) if (DL.getTypeStoreSize(Arg.getType()).isZero())
continue; continue;
ArgInfo OrigArg{VRegs[i], Arg.getType()}; ArgInfo OrigArg{VRegs[i], Arg};
setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv()); splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
++i; ++i;
} }
if (!MBB.empty()) if (!MBB.empty())
MIRBuilder.setInstr(*MBB.begin()); MIRBuilder.setInstr(*MBB.begin());
▲ Show 20 Lines • Show All 584 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show First 20 Lines • Show All 648 Lines • ▼ Show 20 Lines if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
for (int I = 0, E = VRegs[Idx].size(); I != E; ++I) for (int I = 0, E = VRegs[Idx].size(); I != E; ++I)
B.buildUndef(VRegs[Idx][I]); B.buildUndef(VRegs[Idx][I]);
++Idx; ++Idx;
continue; continue;
} }
} }
ArgInfo OrigArg(VRegs[Idx], Arg.getType()); ArgInfo OrigArg(VRegs[Idx], Arg);
const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex; const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
setArgFlags(OrigArg, OrigArgIdx, DL, F); setArgFlags(OrigArg, OrigArgIdx, DL, F);
splitToValueTypes(OrigArg, SplitArgs, DL, CC); splitToValueTypes(OrigArg, SplitArgs, DL, CC);
++Idx; ++Idx;
} }
// At least one interpolation mode must be enabled or else the GPU will // At least one interpolation mode must be enabled or else the GPU will
▲ Show 20 Lines • Show All 407 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,910 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](s32), 0 :: (dereferenceable store 8 into stack, align 4, addrspace 5), (dereferenceable load 8, align 4, addrspace 5) ; CHECK: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](s32), 0 :: (dereferenceable store 8 into stack, align 4, addrspace 5), (dereferenceable load 8 from %ir.val, align 4, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32) ; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32) ; CHECK: $sgpr13 = COPY [[COPY15]](s32)
Show All 38 Linesdefine void @call_byval_3ai32_byval_i8_align32([3 x i32] addrspace(5)* %incoming0, i8 addrspace(5)* align 32 %incoming1) #0 {
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]] ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]] ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(p5) = COPY $sgpr32 ; CHECK: [[COPY19:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C1]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C2]](s32), 0 :: (dereferenceable store 12 into stack, align 4, addrspace 5), (dereferenceable load 12, align 4, addrspace 5) ; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C2]](s32), 0 :: (dereferenceable store 12 into stack, align 4, addrspace 5), (dereferenceable load 12 from %ir.incoming0, align 4, addrspace 5)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: G_MEMCPY [[PTR_ADD1]](p5), [[COPY9]](p5), [[C4]](s32), 0 :: (dereferenceable store 1 into stack + 32, align 32, addrspace 5), (dereferenceable load 1, align 32, addrspace 5) ; CHECK: G_MEMCPY [[PTR_ADD1]](p5), [[COPY9]](p5), [[C4]](s32), 0 :: (dereferenceable store 1 into stack + 32, align 32, addrspace 5), (dereferenceable load 1 from %ir.incoming1, align 32, addrspace 5)
; CHECK: $vgpr0 = COPY [[C]](s32) ; CHECK: $vgpr0 = COPY [[C]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY13]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[COPY13]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; CHECK: $sgpr12 = COPY [[COPY15]](s32) ; CHECK: $sgpr12 = COPY [[COPY15]](s32)
; CHECK: $sgpr13 = COPY [[COPY16]](s32) ; CHECK: $sgpr13 = COPY [[COPY16]](s32)
; CHECK: $sgpr14 = COPY [[COPY17]](s32) ; CHECK: $sgpr14 = COPY [[COPY17]](s32)
; CHECK: $vgpr31 = COPY [[COPY18]](s32) ; CHECK: $vgpr31 = COPY [[COPY18]](s32)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @void_func_byval_a3i32_byval_i8_align32, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31 ; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @void_func_byval_a3i32_byval_i8_align32, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; CHECK: ADJCALLSTACKDOWN 0, 36, implicit-def $scc ; CHECK: ADJCALLSTACKDOWN 0, 36, implicit-def $scc
; CHECK: [[COPY21:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]] ; CHECK: [[COPY21:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]]
; CHECK: S_SETPC_B64_return [[COPY21]] ; CHECK: S_SETPC_B64_return [[COPY21]]
call void @void_func_byval_a3i32_byval_i8_align32([3 x i32] addrspace(5)* byval([3 x i32]) %incoming0, i8 addrspace(5)* align 32 %incoming1, i32 999) call void @void_func_byval_a3i32_byval_i8_align32([3 x i32] addrspace(5)* byval([3 x i32]) %incoming0, i8 addrspace(5)* align 32 %incoming1, i32 999)
ret void ret void
} }
declare void @void_func_byval_a4i64_align4([4 x i64] addrspace(5)* byval([4 x i64]) align 4 %arg0) #0
; Make sure we are aware of the higher alignment of the incoming value
; than implied by the outgoing byval alignment in the memory operand.
define void @call_byval_a4i64_align4_higher_source_align([4 x i64] addrspace(5)* align 256 %incoming_high_align) #0 {
; CHECK-LABEL: name: call_byval_a4i64_align4_higher_source_align
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; CHECK: [[COPY8:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[COPY9:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @void_func_byval_a4i64_align4
; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]
; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY5]]
; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY4]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY18:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY18]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C1]](s32), 0 :: (dereferenceable store 32 into stack, align 4, addrspace 5), (dereferenceable load 32 from %ir.incoming_high_align, align 256, addrspace 5)
; CHECK: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY12]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32)
; CHECK: $sgpr14 = COPY [[COPY16]](s32)
; CHECK: $vgpr31 = COPY [[COPY17]](s32)
; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @void_func_byval_a4i64_align4, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; CHECK: ADJCALLSTACKDOWN 0, 32, implicit-def $scc
; CHECK: [[COPY20:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY9]]
; CHECK: S_SETPC_B64_return [[COPY20]]
call void @void_func_byval_a4i64_align4([4 x i64] addrspace(5)* byval([4 x i64]) align 4 %incoming_high_align)
ret void
}
define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 { define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {
; CHECK-LABEL: name: test_call_external_void_func_v2i8 ; CHECK-LABEL: name: test_call_external_void_func_v2i8
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 ; CHECK: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16 ; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
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