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Differential D98501

[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.
ClosedPublic

Authored by khchen on Mar 12 2021, 6:07 AM.

Details

Reviewers
craig.topper
frasercrmck
Commits
rG9998b00c2ecd: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.
Summary

Fix the unexpected of using op1's element type as shift amount type.

Diff Detail

Event Timeline

khchen created this revision.Mar 12 2021, 6:07 AM
Herald added subscribers: vkmr, evandro, luismarques and 23 others. · View Herald TranscriptMar 12 2021, 6:07 AM
khchen requested review of this revision.Mar 12 2021, 6:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 12 2021, 6:07 AM
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frasercrmck added a comment.Mar 12 2021, 7:18 AM

I can see that the shift amount should be XLen, but is there a crash that this fixes? Or is it that it shouldn't be possible to generate these intrinsics in the first place? I'm wondering what (if anything) can be put in place to stop this from happening again.

Harbormaster completed remote builds in B93480: Diff 330224.Mar 12 2021, 8:27 AM
khchen added a comment.Mar 17 2021, 7:11 AM
In D98501#2622189, @frasercrmck wrote:

I can see that the shift amount should be XLen, but is there a crash that this fixes? Or is it that it shouldn't be possible to generate these intrinsics in the first place? I'm wondering what (if anything) can be put in place to stop this from happening again.

I think it's shouldn't be generated and we noted them when we start working on supporting rvv intrinsics.

Maybe we could define the explicitly type for vector/vector and vector/scalar in the IR intrinsic, it would make intrinsics more strongly typed.
But personally I prefer to keep current intrinsic design...

frasercrmck accepted this revision.Mar 17 2021, 7:53 AM
In D98501#2631735, @khchen wrote:

I think it's shouldn't be generated and we noted them when we start working on supporting rvv intrinsics.

Maybe we could define the explicitly type for vector/vector and vector/scalar in the IR intrinsic, it would make intrinsics more strongly typed.
But personally I prefer to keep current intrinsic design...

Yeah fair enough, I see the issue. I don't propose we change the intrinsic design. I was also generating intrinsics at some point and was having difficulty determining which types to provide, as it tends to just crash when you get it wrong.

Ideally we'd have a check in the backend that the types are as we expect. Either explicit (asserts) or implicit (it doesn't select).

But all of that is increasing the scope of this patch, and this patch is already slowing down my browser, so let's get it in sooner rather than later :)

This revision is now accepted and ready to land.Mar 17 2021, 7:53 AM
Closed by commit rG9998b00c2ecd: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. (authored by khchen). · Explain WhyMar 17 2021, 10:48 AM
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rG9998b00c2ecd: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount..

Revision Contents

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llvm/
test/
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RISCV/
rvv/
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Diff 331318

llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll

Show First 20 Lines • Show All 490 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnclip.wx v26, v8, a0 ; CHECK-NEXT: vnclip.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnclip.wx v28, v8, a0 ; CHECK-NEXT: vnclip.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnclip.wx v26, v8, a0 ; CHECK-NEXT: vnclip.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnclip.wx v28, v8, a0 ; CHECK-NEXT: vnclip.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnclip.wi v26, v8, 9 ; CHECK-NEXT: vnclip.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnclip.wi v28, v8, 9 ; CHECK-NEXT: vnclip.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnclip.wi v26, v8, 9 ; CHECK-NEXT: vnclip.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnclip.wi v28, v8, 9 ; CHECK-NEXT: vnclip.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll

Show First 20 Lines • Show All 670 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnclip.wx v26, v8, a0 ; CHECK-NEXT: vnclip.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnclip.wx v28, v8, a0 ; CHECK-NEXT: vnclip.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnclip.wx v26, v8, a0 ; CHECK-NEXT: vnclip.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnclip.wx v28, v8, a0 ; CHECK-NEXT: vnclip.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnclip_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vnclip_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnclip_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnclip_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vnclip_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnclip.wx v25, v8, a0 ; CHECK-NEXT: vnclip.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnclip_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnclip_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vnclip_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnclip.wx v26, v8, a0 ; CHECK-NEXT: vnclip.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnclip_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnclip_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vnclip_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnclip.wx v28, v8, a0 ; CHECK-NEXT: vnclip.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnclip_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnclip.wi v26, v8, 9 ; CHECK-NEXT: vnclip.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnclip.wi v28, v8, 9 ; CHECK-NEXT: vnclip.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnclip.wi v26, v8, 9 ; CHECK-NEXT: vnclip.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnclip.wi v28, v8, 9 ; CHECK-NEXT: vnclip.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnclip_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vnclip_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnclip_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnclip.wi v25, v8, 9 ; CHECK-NEXT: vnclip.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnclip_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnclip_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnclip.wi v26, v8, 9 ; CHECK-NEXT: vnclip.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnclip_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnclip_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnclip.wi v28, v8, 9 ; CHECK-NEXT: vnclip.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnclip_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll

Show First 20 Lines • Show All 490 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnclipu.wx v26, v8, a0 ; CHECK-NEXT: vnclipu.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnclipu.wx v28, v8, a0 ; CHECK-NEXT: vnclipu.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnclipu.wx v26, v8, a0 ; CHECK-NEXT: vnclipu.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnclipu.wx v28, v8, a0 ; CHECK-NEXT: vnclipu.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnclipu.wi v26, v8, 9 ; CHECK-NEXT: vnclipu.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnclipu.wi v28, v8, 9 ; CHECK-NEXT: vnclipu.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnclipu.wi v26, v8, 9 ; CHECK-NEXT: vnclipu.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnclipu.wi v28, v8, 9 ; CHECK-NEXT: vnclipu.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll

Show First 20 Lines • Show All 670 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnclipu.wx v26, v8, a0 ; CHECK-NEXT: vnclipu.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnclipu.wx v28, v8, a0 ; CHECK-NEXT: vnclipu.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnclipu.wx v26, v8, a0 ; CHECK-NEXT: vnclipu.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnclipu.wx v28, v8, a0 ; CHECK-NEXT: vnclipu.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnclipu_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vnclipu_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnclipu_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnclipu_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vnclipu_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnclipu.wx v25, v8, a0 ; CHECK-NEXT: vnclipu.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnclipu_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnclipu_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vnclipu_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnclipu.wx v26, v8, a0 ; CHECK-NEXT: vnclipu.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnclipu_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnclipu_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vnclipu_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnclipu.wx v28, v8, a0 ; CHECK-NEXT: vnclipu.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnclipu_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnclipu.wi v26, v8, 9 ; CHECK-NEXT: vnclipu.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnclipu.wi v28, v8, 9 ; CHECK-NEXT: vnclipu.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnclipu.wi v26, v8, 9 ; CHECK-NEXT: vnclipu.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnclipu.wi v28, v8, 9 ; CHECK-NEXT: vnclipu.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnclipu_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vnclipu_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnclipu_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnclipu.wi v25, v8, 9 ; CHECK-NEXT: vnclipu.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnclipu_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnclipu_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnclipu.wi v26, v8, 9 ; CHECK-NEXT: vnclipu.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnclipu_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnclipu_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnclipu.wi v28, v8, 9 ; CHECK-NEXT: vnclipu.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnclipu_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll

Show First 20 Lines • Show All 490 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.nxv16i16(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i32>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsra.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i32> %1,
i32 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i64>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i32>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsra.wv v25, v8, v10
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0,
<vscale x 2 x i32> %1,
i32 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i64>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i32>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsra.wv v26, v8, v12
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0,
<vscale x 4 x i32> %1,
i32 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i64>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i32>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsra.wv v28, v8, v16
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0,
<vscale x 8 x i32> %1,
i32 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i64>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0 ; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0 ; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0 ; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0 ; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( define <vscale x 1 x i8> @intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
<vscale x 1 x i64>, ; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8:
i32,
i32);
define <vscale x 1 x i32> @intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32(
<vscale x 1 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32>,
<vscale x 1 x i64>,
i32,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
i32 %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64>,
i32,
i32);
define <vscale x 2 x i32> @intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32>,
<vscale x 2 x i64>,
i32,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
i32 %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64>,
i32,
i32);
define <vscale x 4 x i32> @intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32>,
<vscale x 4 x i64>,
i32,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
i32 %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64>,
i32,
i32);
define <vscale x 8 x i32> @intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32>,
<vscale x 8 x i64>,
i32,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
i32 %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i32> %a
}
define <vscale x 1 x i8> @intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9 ; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9 ; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9 ; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9 ; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32(
<vscale x 1 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
i32 9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
i32 9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
i32 9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
i32 9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i32> %a
}

llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll

Show First 20 Lines • Show All 670 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0 ; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0 ; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0 ; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0 ; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vnsra_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnsra_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vnsra_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnsra.wx v25, v8, a0 ; CHECK-NEXT: vnsra.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnsra_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vnsra_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnsra.wx v26, v8, a0 ; CHECK-NEXT: vnsra.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnsra_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vnsra_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnsra.wx v28, v8, a0 ; CHECK-NEXT: vnsra.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnsra_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnsra_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnsra_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnsra_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnsra_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9 ; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnsra_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9 ; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnsra_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnsra_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnsra_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnsra_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9 ; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnsra_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9 ; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnsra_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vnsra_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vnsra_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsra.wi v25, v8, 9 ; CHECK-NEXT: vnsra.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vnsra_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsra.wi v26, v8, 9 ; CHECK-NEXT: vnsra.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vnsra_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsra.wi v28, v8, 9 ; CHECK-NEXT: vnsra.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vnsra_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsra_mask_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll

Show First 20 Lines • Show All 490 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.nxv16i16(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32( declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i32>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i32> %1,
i32 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i64>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i32>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wv v25, v8, v10
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i64> %0,
<vscale x 2 x i32> %1,
i32 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i64>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i32>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsrl.wv v26, v8, v12
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i64> %0,
<vscale x 4 x i32> %1,
i32 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i64>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i32>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsrl.wv v28, v8, v16
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0,
<vscale x 8 x i32> %1,
i32 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i64>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i32> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0 ; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0 ; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0 ; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0 ; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( define <vscale x 1 x i8> @intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
<vscale x 1 x i64>, ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8:
i32,
i32);
define <vscale x 1 x i32> @intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32(
<vscale x 1 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32>,
<vscale x 1 x i64>,
i32,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
i32 %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64>,
i32,
i32);
define <vscale x 2 x i32> @intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32>,
<vscale x 2 x i64>,
i32,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
i32 %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64>,
i32,
i32);
define <vscale x 4 x i32> @intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32>,
<vscale x 4 x i64>,
i32,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
i32 %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64>,
i32,
i32);
define <vscale x 8 x i32> @intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64> %0,
i32 %1,
i32 %2)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32>,
<vscale x 8 x i64>,
i32,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
i32 %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i32> %a
}
define <vscale x 1 x i8> @intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9 ; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9 ; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9 ; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9 ; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32(
<vscale x 1 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i64> %1,
i32 9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32(
<vscale x 2 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i64> %1,
i32 9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32(
<vscale x 4 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i64> %1,
i32 9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32(
<vscale x 8 x i64> %0,
i32 9,
i32 %1)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i64> %1,
i32 9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i32> %a
}

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll

Show First 20 Lines • Show All 670 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( declare <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( declare <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( declare <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( declare <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0 ; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( declare <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0 ; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( declare <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( declare <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( declare <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( declare <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0 ; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( declare <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0 ; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( declare <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vnsrl_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( declare <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vnsrl_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vnsrl_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wx v25, v8, a0 ; CHECK-NEXT: vnsrl.wx v25, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( declare <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vnsrl_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vnsrl_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vnsrl.wx v26, v8, a0 ; CHECK-NEXT: vnsrl.wx v26, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( declare <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vnsrl_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vnsrl_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vnsrl.wx v28, v8, a0 ; CHECK-NEXT: vnsrl.wx v28, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( declare <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vnsrl_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t ; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9 ; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9 ; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9 ; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9 ; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vnsrl_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i32_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vnsrl.wi v25, v8, 9 ; CHECK-NEXT: vnsrl.wi v25, v8, 9
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vnsrl_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i32_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vnsrl.wi v26, v8, 9 ; CHECK-NEXT: vnsrl.wi v26, v8, 9
; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vnsrl_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i32_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vnsrl.wi v28, v8, 9 ; CHECK-NEXT: vnsrl.wi v28, v8, 9
; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vnsrl_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i32_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsll_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsll_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsll_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsll_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsll_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsll_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsll_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i32 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsll_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsll_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsll_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsll_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsll_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsll_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsll_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsll_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsll_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsll_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsll_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i32 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll

Show First 20 Lines • Show All 967 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsll_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsll_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsll_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsll_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsll_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsll_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsll_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i64 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsll_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsll_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsll_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsll_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsll_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsll_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsll_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsll_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsll_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsll_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsll_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsll_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsll_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsll_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsll_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsll_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsll_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsll_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsll_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsll_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsll_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsll_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsll_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsll_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsll_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsll_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsll_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsll_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsll_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsll_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: vsll.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsll_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsll_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsll.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsll.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsll.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsll.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i64 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsll.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsll.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsll.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsll.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsll.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsll.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsll.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsll.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsll.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vsll_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsll_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsll_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsll.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsll.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsll_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsll_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsll.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsll.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsll_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsll_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsll_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsll.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsll.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsll_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsll_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsll_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsll.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsra_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsra_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsra_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsra_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsra_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsra_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsra_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i32 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsra_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsra_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsra_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsra_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsra_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsra_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsra_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsra_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsra_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsra_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsra_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i32 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll

Show First 20 Lines • Show All 967 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsra_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsra_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsra_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsra_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsra_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsra_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsra_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i64 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsra_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsra_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsra_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsra_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsra_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsra_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsra_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsra_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsra_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsra_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsra_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsra_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsra_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsra_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsra_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsra_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsra_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsra_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsra_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsra_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsra_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsra_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsra_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsra_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsra_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsra_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsra_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsra_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsra_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsra_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsra_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsra_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i64 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vsra_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsra_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsra_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsra.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsra.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsra_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsra_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsra_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsra.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsra.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsra_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsra_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsra_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsra.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsra.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsra_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsra_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsra_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsra_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vsra.vi v8, v8, 9 ; CHECK-NEXT: vsra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsra.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i32 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i32 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll

Show First 20 Lines • Show All 967 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i64 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsrl_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsrl_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsrl_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsrl_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsrl_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsrl_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsrl_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsrl_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i64 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vsrl.vi v8, v8, 9 ; CHECK-NEXT: vsrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i32);
define <vscale x 1 x i64> @intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssra.vv v8, v8, v9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i32 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i64> @intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i32);
define <vscale x 2 x i64> @intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssra.vv v8, v8, v10
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i32 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i64> @intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i32);
define <vscale x 4 x i64> @intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssra.vv v8, v8, v12
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i32 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i64> @intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i32);
define <vscale x 8 x i64> @intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssra.vv v8, v8, v16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i32 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i64> @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vssra_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vssra_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vssra_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vssra_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vssra_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vssra_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssra_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i32 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vssra_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vssra_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vssra_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vssra_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vssra_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssra_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vssra_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vssra_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vssra_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vssra_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssra_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssra_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vssra.vv v8, v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vssra.vv v8, v9, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssra_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vssra.vv v8, v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu
; CHECK-NEXT: vssra.vv v8, v10, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssra_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsll.vx v12, v12, a1
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: vor.vv v28, v12, v28
; CHECK-NEXT: vssra.vv v8, v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsll.vx v16, v16, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vor.vv v28, v16, v28
; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu
; CHECK-NEXT: vssra.vv v8, v12, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssra_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v16, v16, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: vssra.vv v8, v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: csrrs a3, vlenb, zero ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: sub sp, sp, a3
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs1r.v v0, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v24, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v0, v24, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v24, v24, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1re8.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: csrrs a0, vlenb, zero
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i32 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vssra_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vssra_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 2 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vssra_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 4 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vssra_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 8 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll

Show First 20 Lines • Show All 967 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vssra_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vssra_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vssra_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vssra_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vssra_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vssra_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssra_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i64 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vssra_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vssra_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vssra_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vssra_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vssra_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssra_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vssra_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vssra_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vssra_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vssra_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssra_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vssra_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vssra_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vssra_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssra_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: vssra.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssra.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssra.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssra.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssra.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssra.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssra.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i64 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssra.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssra.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssra.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssra.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssra.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssra.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssra.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssra.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssra.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vssra_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssra.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vssra_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssra.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vssra_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssra.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vssra_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssra.vi v8, v8, 9 ; CHECK-NEXT: vssra.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.nxv1i64( declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i32);
define <vscale x 1 x i64> @intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssrl.vv v8, v8, v9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i32 %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i64> @intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
i32 %4)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i32);
define <vscale x 2 x i64> @intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssrl.vv v8, v8, v10
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i32 %2)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i64> @intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
i32 %4)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i32);
define <vscale x 4 x i64> @intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssrl.vv v8, v8, v12
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i32 %2)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i64> @intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
i32 %4)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i32);
define <vscale x 8 x i64> @intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssrl.vv v8, v8, v16
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i32 %2)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
i32 %4)
ret <vscale x 8 x i64> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i8> @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i8> @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i8> @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i8> @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i8> @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i32,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i32 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i32,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i32 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i32,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vssrl.vv v8, v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v25, v25, a1
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu
; CHECK-NEXT: vssrl.vv v8, v9, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vssrl.vv v8, v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vmv.v.x v26, a1 ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu
; CHECK-NEXT: vssrl.vv v8, v10, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsll.vx v12, v12, a1
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: vor.vv v28, v12, v28
; CHECK-NEXT: vssrl.vv v8, v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsll.vx v16, v16, a1
; CHECK-NEXT: vsrl.vx v16, v16, a1
; CHECK-NEXT: vor.vv v28, v16, v28
; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu
; CHECK-NEXT: vssrl.vv v8, v12, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v16, v16, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v16, v24, v16
; CHECK-NEXT: vssrl.vv v8, v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: csrrs a3, vlenb, zero ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: sub sp, sp, a3
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs1r.v v0, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a3, a2, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.x v24, a1
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsll.vx v0, v24, a1
; CHECK-NEXT: vmv.v.x v24, a0
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v24, v24, v0
; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1re8.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: csrrs a0, vlenb, zero
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i32 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i32 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i32 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 2 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 4 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 9,
i32 %1)
ret <vscale x 8 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll

Show First 20 Lines • Show All 967 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i8> @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( declare <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i8> @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( declare <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i8> @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( declare <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( declare <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i8> @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( declare <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i8> @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( declare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i8, i64,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 %2, i64 %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( declare <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( declare <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( declare <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( declare <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( declare <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( declare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
i16, i64,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 %2, i64 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( declare <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( declare <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( declare <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( declare <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( declare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
i32, i64,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i64 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64( declare <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64( declare <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64( declare <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu
; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: vssrl.vx v8, v8, a0
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64( declare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu
; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t ; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i8( %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i8( %a = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i8( %a = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i8( %a = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i8( %a = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i8( %a = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
i8 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
i8 9, i64 9,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
define <vscale x 1 x i16> @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i16( %a = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i16( %a = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i16( %a = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i16( %a = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i16( %a = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i16 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
i16 9, i64 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
define <vscale x 1 x i32> @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i32( %a = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i32( %a = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i32( %a = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i32( %a = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i32 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 9, i64 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i64> @intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vssrl.vi v8, v8, 9 ; CHECK-NEXT: vssrl.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t ; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 9, i64 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }