[WebAssembly] Remove unimplemented-simd target features

[tlively]

Summary

Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature for gating
SIMD instructions that engines have not implemented. With this change,
v128.const is now enabled by default with the simd128 target feature.

[tlively]

• Restore partially-removed qfma/qfms

[dschuff]

clang/docs/ClangCommandLineReference.rst

3801

extraneous change?

clang/include/clang/Basic/BuiltinsWebAssembly.def

191–194

is QFMA actually in MVP simd? I thought it was non-deterministic?

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1715

out of curiosity, are there any cases where a splat could be smaller than a v128 const, since the consts are pretty big?

[tlively]

clang/docs/ClangCommandLineReference.rst

3801

Yes, will revert, thanks.

clang/include/clang/Basic/BuiltinsWebAssembly.def

191–194

No, as you discovered, it's removed in the next patch. I kind of ended up with these patches in the wrong order, but I think it should be ok.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

1715

Yes, for sure. In fact, this code used to find the const lowering that resulted in the fewest bytes emitted. Our users much prefer to have the fewest instructions emitted, though, since this lowering is often critical for performance.

clang/docs/ClangCommandLineReference.rst

 
 undef all system defines
 
 .. option:: -undefined<arg>, --no-undefined
 
 .. option:: -z <arg>
 
 Pass -z <arg> to the linker
-

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_signselect_i32x4, "V4iV4iV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_signselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_shuffle_v8x16, "V16ScV16ScV16ScIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, "iV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_any_true_i16x8, "iV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_any_true_i32x4, "iV4i", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_any_true_i64x2, "iV2LLi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_any_true_i64x2, "iV2LLi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i8x16, "iV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i16x8, "iV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i32x4, "iV4i", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_all_true_i64x2, "iV2LLi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_all_true_i64x2, "iV2LLi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_bitmask_i8x16, "iV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_bitmask_i16x8, "iV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_bitmask_i32x4, "iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_bitmask_i64x2, "iV2LLi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_abs_f32x4, "V4fV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "simd128")

 TARGET_BUILTIN(__builtin_wasm_trunc_f64x2, "V2dV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_nearest_f64x2, "V2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_dot_s_i32x4_i16x8, "V4iV8sV8s", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, "V16ScV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8UsV8Us", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4UiV4Ui", "nc", "simd128")

clang/include/clang/Driver/Options.td

def msign_return_address_EQ : Joined<["-"], "msign-return-address=">,
   HelpText<"Select return address signing scope">;
 def mbranch_protection_EQ : Joined<["-"], "mbranch-protection=">,
   HelpText<"Enforce targets of indirect branches and function returns">;
 
 def mharden_sls_EQ : Joined<["-"], "mharden-sls=">,
   HelpText<"Select straight-line speculation hardening scope">;
 
 def msimd128 : Flag<["-"], "msimd128">, Group<m_wasm_Features_Group>;
-def munimplemented_simd128 : Flag<["-"], "munimplemented-simd128">, Group<m_wasm_Features_Group>;
-def mno_unimplemented_simd128 : Flag<["-"], "mno-unimplemented-simd128">, Group<m_wasm_Features_Group>;
 def mno_simd128 : Flag<["-"], "mno-simd128">, Group<m_wasm_Features_Group>;
 def mnontrapping_fptoint : Flag<["-"], "mnontrapping-fptoint">, Group<m_wasm_Features_Group>;
 def mno_nontrapping_fptoint : Flag<["-"], "mno-nontrapping-fptoint">, Group<m_wasm_Features_Group>;
 def msign_ext : Flag<["-"], "msign-ext">, Group<m_wasm_Features_Group>;
 def mno_sign_ext : Flag<["-"], "mno-sign-ext">, Group<m_wasm_Features_Group>;
 def mexception_handing : Flag<["-"], "mexception-handling">, Group<m_wasm_Features_Group>;
 def mno_exception_handing : Flag<["-"], "mno-exception-handling">, Group<m_wasm_Features_Group>;
 def matomics : Flag<["-"], "matomics">, Group<m_wasm_Features_Group>;

clang/lib/Basic/Targets/WebAssembly.h

 namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
 
   enum SIMDEnum {
     NoSIMD,
     SIMD128,
-    UnimplementedSIMD128,
   } SIMDLevel = NoSIMD;
 
   bool HasNontrappingFPToInt = false;
   bool HasSignExt = false;
   bool HasExceptionHandling = false;
   bool HasBulkMemory = false;
   bool HasAtomics = false;
   bool HasMutableGlobals = false;

clang/lib/Basic/Targets/WebAssembly.cpp

bool WebAssemblyTargetInfo::setABI(const std::string &Name) {
 
   ABI = Name;
   return true;
 }
 
 bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("simd128", SIMDLevel >= SIMD128)
-      .Case("unimplemented-simd128", SIMDLevel >= UnimplementedSIMD128)
       .Case("nontrapping-fptoint", HasNontrappingFPToInt)
       .Case("sign-ext", HasSignExt)
       .Case("exception-handling", HasExceptionHandling)
       .Case("bulk-memory", HasBulkMemory)
       .Case("atomics", HasAtomics)
       .Case("mutable-globals", HasMutableGlobals)
       .Case("multivalue", HasMultivalue)
       .Case("tail-call", HasTailCall)
void WebAssemblyTargetInfo::fillValidCPUList(
   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
 }
 
 void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts,
                                              MacroBuilder &Builder) const {
   defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
   if (SIMDLevel >= SIMD128)
     Builder.defineMacro("__wasm_simd128__");
-  if (SIMDLevel >= UnimplementedSIMD128)
-    Builder.defineMacro("__wasm_unimplemented_simd128__");
   if (HasNontrappingFPToInt)
     Builder.defineMacro("__wasm_nontrapping_fptoint__");
   if (HasSignExt)
     Builder.defineMacro("__wasm_sign_ext__");
   if (HasExceptionHandling)
     Builder.defineMacro("__wasm_exception_handling__");
   if (HasBulkMemory)
     Builder.defineMacro("__wasm_bulk_memory__");
   if (HasAtomics)
     Builder.defineMacro("__wasm_atomics__");
   if (HasMutableGlobals)
     Builder.defineMacro("__wasm_mutable_globals__");
   if (HasMultivalue)
     Builder.defineMacro("__wasm_multivalue__");
   if (HasTailCall)
     Builder.defineMacro("__wasm_tail_call__");
   if (HasReferenceTypes)
     Builder.defineMacro("__wasm_reference_types__");
 }
 
 void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features,
                                          SIMDEnum Level, bool Enabled) {
   if (Enabled) {
     switch (Level) {
-    case UnimplementedSIMD128:
-      Features["unimplemented-simd128"] = true;
-      LLVM_FALLTHROUGH;
     case SIMD128:
       Features["simd128"] = true;
       LLVM_FALLTHROUGH;
     case NoSIMD:
       break;
     }
     return;
   }
 
   switch (Level) {
   case NoSIMD:
   case SIMD128:
     Features["simd128"] = false;
-    LLVM_FALLTHROUGH;
-  case UnimplementedSIMD128:
-    Features["unimplemented-simd128"] = false;
     break;
   }
 }
 
 void WebAssemblyTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
                                               StringRef Name,
                                               bool Enabled) const {
   if (Name == "simd128")
     setSIMDLevel(Features, SIMD128, Enabled);
-  else if (Name == "unimplemented-simd128")
-    setSIMDLevel(Features, UnimplementedSIMD128, Enabled);
   else
     Features[Name] = Enabled;
 }
 
 bool WebAssemblyTargetInfo::initFeatureMap(
     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
     const std::vector<std::string> &FeaturesVec) const {
   if (CPU == "bleeding-edge") {
for (const auto &Feature : Features) {
     if (Feature == "+simd128") {
       SIMDLevel = std::max(SIMDLevel, SIMD128);
       continue;
     }
     if (Feature == "-simd128") {
       SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
       continue;
     }
-    if (Feature == "+unimplemented-simd128") {
-      SIMDLevel = std::max(SIMDLevel, SIMDEnum(UnimplementedSIMD128));
-      continue;
-    }
-    if (Feature == "-unimplemented-simd128") {
-      SIMDLevel = std::min(SIMDLevel, SIMDEnum(UnimplementedSIMD128 - 1));
-      continue;
-    }
     if (Feature == "+nontrapping-fptoint") {
       HasNontrappingFPToInt = true;
       continue;
     }
     if (Feature == "-nontrapping-fptoint") {
       HasNontrappingFPToInt = false;
       continue;
     }

clang/test/CodeGen/builtins-wasm.c

-// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +unimplemented-simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
-// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +unimplemented-simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
+// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
+// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +simd128 -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
 // RUN: not %clang_cc1 -triple wasm64-unknown-unknown -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s 2>&1 | FileCheck %s -check-prefixes MISSING-SIMD
 
 // SIMD convenience types
 typedef signed char i8x16 __attribute((vector_size(16)));
 typedef short i16x8 __attribute((vector_size(16)));
 typedef int i32x4 __attribute((vector_size(16)));
 typedef long long i64x2 __attribute((vector_size(16)));
 typedef unsigned char u8x16 __attribute((vector_size(16)));

clang/test/Preprocessor/wasm-target-features.c

 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm32-unknown-unknown -msimd128 \
 // RUN:   | FileCheck %s -check-prefix=SIMD128
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm64-unknown-unknown -msimd128 \
 // RUN:   | FileCheck %s -check-prefix=SIMD128
 //
 // SIMD128:#define __wasm_simd128__ 1{{$}}
 
 // RUN: %clang -E -dM %s -o - 2>&1 \
-// RUN:     -target wasm32-unknown-unknown -munimplemented-simd128 \
-// RUN:   | FileCheck %s -check-prefix=SIMD128-UNIMPLEMENTED
-// RUN: %clang -E -dM %s -o - 2>&1 \
-// RUN:     -target wasm64-unknown-unknown -munimplemented-simd128 \
-// RUN:   | FileCheck %s -check-prefix=SIMD128-UNIMPLEMENTED
-//
-// SIMD128-UNIMPLEMENTED:#define __wasm_unimplemented_simd128__ 1{{$}}
-
-// RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm32-unknown-unknown -mnontrapping-fptoint \
 // RUN:   | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm64-unknown-unknown -mnontrapping-fptoint \
 // RUN:   | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT
 //
 // NONTRAPPING-FPTOINT:#define __wasm_nontrapping_fptoint__ 1{{$}}
 

 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm32-unknown-unknown -mcpu=mvp \
 // RUN:   | FileCheck %s -check-prefix=MVP
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target wasm64-unknown-unknown -mcpu=mvp \
 // RUN:   | FileCheck %s -check-prefix=MVP
 //
 // MVP-NOT:#define __wasm_simd128__
-// MVP-NOT:#define __wasm_unimplemented_simd128__
 // MVP-NOT:#define __wasm_nontrapping_fptoint__
 // MVP-NOT:#define __wasm_sign_ext__
 // MVP-NOT:#define __wasm_exception_handling__
 // MVP-NOT:#define __wasm_bulk_memory__
 // MVP-NOT:#define __wasm_atomics__
 // MVP-NOT:#define __wasm_mutable_globals__
 // MVP-NOT:#define __wasm_multivalue__
 // MVP-NOT:#define __wasm_tail_call__

llvm/lib/Target/WebAssembly/WebAssembly.td

 
 //===----------------------------------------------------------------------===//
 // WebAssembly Subtarget features.
 //===----------------------------------------------------------------------===//
 
 def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
                                       "Enable 128-bit SIMD">;
 
-def FeatureUnimplementedSIMD128 :
-      SubtargetFeature<"unimplemented-simd128",
-                       "SIMDLevel", "UnimplementedSIMD128",
-                       "Enable 128-bit SIMD not yet implemented in engines",
-                       [FeatureSIMD128]>;
-
 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
                                       "Enable Atomics">;
 
 def FeatureNontrappingFPToInt :
       SubtargetFeature<"nontrapping-fptoint",
                        "HasNontrappingFPToInt", "true",
                        "Enable non-trapping float-to-int conversion operators">;
 

llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
     case MVT::externref:
       return VT;
     case MVT::f16:
       return MVT::f32;
     case MVT::v16i8:
     case MVT::v8i16:
     case MVT::v4i32:
     case MVT::v4f32:
-      if (Subtarget->hasSIMD128())
-        return VT;
-      break;
     case MVT::v2i64:
     case MVT::v2f64:
-      if (Subtarget->hasUnimplementedSIMD128())
+      if (Subtarget->hasSIMD128())
         return VT;
       break;
     default:
       break;
     }
     return MVT::INVALID_SIMPLE_VALUE_TYPE;
   }
   bool computeAddress(const Value *Obj, Address &Addr);

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

if (SwizzleCounts.size())
     std::forward_as_tuple(std::tie(SwizzleSrc, SwizzleIndices),
                           NumSwizzleLanes) = GetMostCommon(SwizzleCounts);
 
   // Predicate returning true if the lane is properly initialized by the
   // original instruction
   std::function<bool(size_t, const SDValue &)> IsLaneConstructed;
   SDValue Result;
   // Prefer swizzles over vector consts over splats
-  if (NumSwizzleLanes >= NumSplatLanes &&
-      (!Subtarget->hasUnimplementedSIMD128() ||
-       NumSwizzleLanes >= NumConstantLanes)) {
+  if (NumSwizzleLanes >= NumSplatLanes && NumSwizzleLanes >= NumConstantLanes) {
     Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc,
                          SwizzleIndices);
     auto Swizzled = std::make_pair(SwizzleSrc, SwizzleIndices);
     IsLaneConstructed = [&, Swizzled](size_t I, const SDValue &Lane) {
       return Swizzled == GetSwizzleSrcs(I, Lane);
     };
-  } else if (NumConstantLanes >= NumSplatLanes &&
-             Subtarget->hasUnimplementedSIMD128()) {
-    // If we support v128.const, emit it directly
+  } else if (NumConstantLanes >= NumSplatLanes) {
     SmallVector<SDValue, 16> ConstLanes;
     for (const SDValue &Lane : Op->op_values()) {
       if (IsConstant(Lane)) {
         ConstLanes.push_back(Lane);
       } else if (LaneT.isFloatingPoint()) {
         ConstLanes.push_back(DAG.getConstantFP(0, DL, LaneT));
       } else {
         ConstLanes.push_back(DAG.getConstant(0, DL, LaneT));
       }
     }
     Result = DAG.getBuildVector(VecT, DL, ConstLanes);
     IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
       return IsConstant(Lane);
     };
-  } else if (NumConstantLanes >= NumSplatLanes && VecT.isInteger()) {
-    // Otherwise, if this is an integer vector, pack the lane values together so
-    // we can construct the 128-bit constant from a pair of i64s using a splat
-    // followed by at most one i64x2.replace_lane. Also keep track of the lanes
-    // that actually matter so we can avoid the replace_lane in more cases.
-    std::array<uint64_t, 2> I64s{{0, 0}};
-    std::array<uint64_t, 2> ConstLaneMasks{{0, 0}};
-    size_t LaneBits = 128 / Lanes;
-    size_t HalfLanes = Lanes / 2;
-    for (size_t I = 0; I < Lanes; ++I) {
-      const SDValue &Lane = Op.getOperand(I);
-      if (IsConstant(Lane)) {
-        // How much we need to shift Val to position it in an i64
-        auto Shift = LaneBits * (I % HalfLanes);
-        auto Mask = maskTrailingOnes<uint64_t>(LaneBits);
-        auto Val = cast<ConstantSDNode>(Lane.getNode())->getZExtValue() & Mask;
-        I64s[I / HalfLanes] |= Val << Shift;
-        ConstLaneMasks[I / HalfLanes] |= Mask << Shift;
-      }
-    }
-    // Check whether all constant lanes in the second half of the vector are
-    // equivalent in the first half or vice versa to determine whether splatting
-    // either side will be sufficient to materialize the constant. As a special
-    // case, if the first and second halves have no constant lanes in common, we
-    // can just combine them.
-    bool FirstHalfSufficient = (I64s[0] & ConstLaneMasks[1]) == I64s[1];
-    bool SecondHalfSufficient = (I64s[1] & ConstLaneMasks[0]) == I64s[0];
-    bool CombinedSufficient = (ConstLaneMasks[0] & ConstLaneMasks[1]) == 0;
-
-    uint64_t Splatted;
-    if (SecondHalfSufficient) {
-      Splatted = I64s[1];
-    } else if (CombinedSufficient) {
-      Splatted = I64s[0] | I64s[1];
-    } else {
-      Splatted = I64s[0];
-    }
-
-    Result = DAG.getSplatBuildVector(MVT::v2i64, DL,
-                                     DAG.getConstant(Splatted, DL, MVT::i64));
-    if (!FirstHalfSufficient && !SecondHalfSufficient && !CombinedSufficient) {
-      Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v2i64, Result,
-                           DAG.getConstant(I64s[1], DL, MVT::i64),
-                           DAG.getConstant(1, DL, MVT::i32));
-    }
-    Result = DAG.getBitcast(VecT, Result);
-    IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
-      return IsConstant(Lane);
-    };
   } else {
     // Use a splat, but possibly a load_splat
     LoadSDNode *SplattedLoad;
     if ((SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
         SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) {
       Result = DAG.getMemIntrinsicNode(
           WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList(VecT),
           {SplattedLoad->getChain(), SplattedLoad->getBasePtr(),

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

 def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
 
 def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
 
 def HasSIMD128 :
     Predicate<"Subtarget->hasSIMD128()">,
     AssemblerPredicate<(all_of FeatureSIMD128), "simd128">;
 
-def HasUnimplementedSIMD128 :
-    Predicate<"Subtarget->hasUnimplementedSIMD128()">,
-    AssemblerPredicate<(all_of FeatureUnimplementedSIMD128), "unimplemented-simd128">;
-
 def HasAtomics :
     Predicate<"Subtarget->hasAtomics()">,
     AssemblerPredicate<(all_of FeatureAtomics), "atomics">;
 
 def HasMultivalue :
     Predicate<"Subtarget->hasMultivalue()">,
     AssemblerPredicate<(all_of FeatureMultivalue), "multivalue">;
 

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // instructions are merged to the proposal.
 
 //===----------------------------------------------------------------------===//
 // Constructing SIMD values
 //===----------------------------------------------------------------------===//
 
 // Constant: v128.const
 multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
-  let isMoveImm = 1, isReMaterializable = 1,
-      Predicates = [HasUnimplementedSIMD128] in
+  let isMoveImm = 1, isReMaterializable = 1 in
   defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                  [(set V128:$dst, (vec.vt pat))],
                                  "v128.const\t$dst, "#args,
                                  "v128.const\t"#args, 12>;
 }
 
 defm "" : ConstVec<I8x16,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,

llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h

 // Defined in WebAssemblyGenSubtargetInfo.inc.
 extern const SubtargetFeatureKV
     WebAssemblyFeatureKV[WebAssembly::NumSubtargetFeatures];
 
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
   enum SIMDEnum {
     NoSIMD,
     SIMD128,
-    UnimplementedSIMD128,
   } SIMDLevel = NoSIMD;
 
   bool HasAtomics = false;
   bool HasNontrappingFPToInt = false;
   bool HasSignExt = false;
   bool HasExceptionHandling = false;
   bool HasBulkMemory = false;
   bool HasMultivalue = false;
public:
   bool enableAtomicExpand() const override;
   bool enableIndirectBrExpand() const override { return true; }
   bool enableMachineScheduler() const override;
   bool useAA() const override;
 
   // Predicates used by WebAssemblyInstrInfo.td.
   bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
   bool hasSIMD128() const { return SIMDLevel >= SIMD128; }
-  bool hasUnimplementedSIMD128() const {
-    return SIMDLevel >= UnimplementedSIMD128;
-  }
   bool hasAtomics() const { return HasAtomics; }
   bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
   bool hasSignExt() const { return HasSignExt; }
   bool hasExceptionHandling() const { return HasExceptionHandling; }
   bool hasBulkMemory() const { return HasBulkMemory; }
   bool hasMultivalue() const { return HasMultivalue; }
   bool hasMutableGlobals() const { return HasMutableGlobals; }
   bool hasTailCall() const { return HasTailCall; }

llvm/test/CodeGen/WebAssembly/simd-arith.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
+
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
+
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; check that a non-test run (including explicit locals pass) at least finishes
-; RUN: llc < %s -O0 -mattr=+unimplemented-simd128
-; RUN: llc < %s -O2 -mattr=+unimplemented-simd128
+; RUN: llc < %s -O0 -mattr=+simd128
+; RUN: llc < %s -O2 -mattr=+simd128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8

llvm/test/CodeGen/WebAssembly/simd-build-vector.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes=CHECK,UNIMP
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes=CHECK,SIMD-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test that the logic to choose between v128.const vector
 ; initialization and splat vector initialization and to optimize the
 ; choice of splat value works correctly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-; CHECK-LABEL:  emulated_const_trivial_splat:
-; CHECK-NEXT:   .functype       emulated_const_trivial_splat () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_trivial_splat() {
-  ret <4 x i32> <i32 1, i32 2, i32 1, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_first_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_first_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_first_sufficient() {
-  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_second_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_second_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_second_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_combined_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_combined_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_combined_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 undef, i32 2>
-}
-
-; CHECK-LABEL:  emulated_const_either_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_either_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 1
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-; UNIMP: v128.const
-define <4 x i32> @emulated_const_either_sufficient() {
-  ret <4 x i32> <i32 1, i32 undef, i32 1, i32 undef>
-}
-
-; CHECK-LABEL: emulated_const_neither_sufficient:
-; CHECK-NEXT:   .functype       emulated_const_neither_sufficient () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 8589934593
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: i64.const       $push2=, 17179869184
-; SIMD-VM-NEXT: i64x2.replace_lane      $push3=, $pop1, 1, $pop2
-; SIMD-VM-NEXT: return  $pop3
-define <4 x i32> @emulated_const_neither_sufficient() {
-  ret <4 x i32> <i32 1, i32 2, i32 undef, i32 4>
-}
-
-; CHECK-LABEL:  emulated_const_combined_sufficient_large:
-; CHECK-NEXT:   .functype       emulated_const_combined_sufficient_large () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, 506097522914230528
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: return  $pop1
-define <16 x i8> @emulated_const_combined_sufficient_large() {
-  ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 undef,
-                 i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
-}
-
-; CHECK-LABEL: emulated_const_neither_sufficient_large:
-; CHECK-NEXT:   .functype       emulated_const_neither_sufficient_large () -> (v128)
-; SIMD-VM-NEXT: i64.const       $push0=, -70368726997663744
-; SIMD-VM-NEXT: i64x2.splat     $push1=, $pop0
-; SIMD-VM-NEXT: i64.const       $push2=, 504408655873966336
-; SIMD-VM-NEXT: i64x2.replace_lane      $push3=, $pop1, 1, $pop2
-; SIMD-VM-NEXT: return  $pop3
-define <16 x i8> @emulated_const_neither_sufficient_large() {
-  ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 255,
-                 i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
-}
-
 ; CHECK-LABEL: same_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_i16x8 (i32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
-; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
+; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <8 x i16> @same_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>,
     i16 %x,
     i32 5
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: different_const_one_replaced_i16x8:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_i16x8 (i32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
-; UNIMP-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
+; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <8 x i16> @different_const_one_replaced_i16x8(i16 %x) {
   %v = insertelement
     <8 x i16> <i16 1, i16 -2, i16 3, i16 -4, i16 5, i16 -6, i16 7, i16 -8>,
     i16 %x,
     i32 5
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: same_const_one_replaced_f32x4:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_f32x4 (f32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x0p0, 0x1.5p5
-; UNIMP-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: f32x4.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1.5p5, 0x1.5p5, 0x0p0, 0x1.5p5
+; CHECK-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <4 x float> @same_const_one_replaced_f32x4(float %x) {
   %v = insertelement
     <4 x float> <float 42., float 42., float 42., float 42.>,
     float %x,
     i32 2
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: different_const_one_replaced_f32x4:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_f32x4 (f32) -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1p0, 0x1p1, 0x0p0, 0x1p2
-; UNIMP-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
-; UNIMP-NEXT:  return          $pop[[L1]]
-; SIMD-VM: f32x4.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x1p0, 0x1p1, 0x0p0, 0x1p2
+; CHECK-NEXT:  f32x4.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0
+; CHECK-NEXT:  return          $pop[[L1]]
 define <4 x float> @different_const_one_replaced_f32x4(float %x) {
   %v = insertelement
     <4 x float> <float 1., float 2., float 3., float 4.>,
     float %x,
     i32 2
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: splat_common_const_i32x4:
 ; CHECK-NEXT:  .functype       splat_common_const_i32x4 () -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0, 3, 3, 1
-; UNIMP-NEXT:  return          $pop[[L0]]
-; SIMD-VM: i64x2.splat
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0, 3, 3, 1
+; CHECK-NEXT:  return          $pop[[L0]]
 define <4 x i32> @splat_common_const_i32x4() {
   ret <4 x i32> <i32 undef, i32 3, i32 3, i32 1>
 }
 
 ; CHECK-LABEL: splat_common_arg_i16x8:
 ; CHECK-NEXT:  .functype       splat_common_arg_i16x8 (i32, i32, i32) -> (v128)
 ; CHECK-NEXT:  i16x8.splat     $push[[L0:[0-9]+]]=, $2
 ; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 0, $1
define <16 x i8> @mashup_swizzle_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
   %v4 = insertelement <16 x i8> %v3, i8 42, i32 4
   ; const 14
   %v5 = insertelement <16 x i8> %v4, i8 42, i32 14
   ret <16 x i8> %v5
 }
 
 ; CHECK-LABEL: mashup_const_i8x16:
 ; CHECK-NEXT:  .functype       mashup_const_i8x16 (v128, v128, i32) -> (v128)
-; UNIMP:       v128.const      $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       i8x16.replace_lane
-; UNIMP:       return
-; SIMD-VM: i64x2.splat
+; CHECK:       v128.const      $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0
+; CHECK:       i8x16.replace_lane
+; CHECK:       i8x16.replace_lane
+; CHECK:       i8x16.replace_lane
+; CHECK:       return
 define <16 x i8> @mashup_const_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
   ; swizzle 0
   %m0 = extractelement <16 x i8> %mask, i32 0
   %s0 = extractelement <16 x i8> %src, i8 %m0
   %v0 = insertelement <16 x i8> undef, i8 %s0, i32 0
   ; splat 3
   %v1 = insertelement <16 x i8> %v0, i8 %splatted, i32 3
   ; splat 12
define <16 x i8> @mashup_splat_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
   %v2 = insertelement <16 x i8> %v1, i8 %splatted, i32 12
   ; const 4
   %v3 = insertelement <16 x i8> %v2, i8 42, i32 4
   ret <16 x i8> %v3
 }
 
 ; CHECK-LABEL: undef_const_insert_f32x4:
 ; CHECK-NEXT:  .functype       undef_const_insert_f32x4 () -> (v128)
-; UNIMP-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x0p0, 0x1.5p5, 0x0p0, 0x0p0
-; UNIMP-NEXT:  return          $pop[[L0]]
+; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 0x0p0, 0x1.5p5, 0x0p0, 0x0p0
+; CHECK-NEXT:  return          $pop[[L0]]
 ; SIMD-VM: f32x4.splat
 define <4 x float> @undef_const_insert_f32x4() {
   %v = insertelement <4 x float> undef, float 42., i32 1
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: undef_arg_insert_i32x4:
 ; CHECK-NEXT:  .functype       undef_arg_insert_i32x4 (i32) -> (v128)

llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test SIMD comparison operators
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: compare_eq_v16i8:

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector float-to-int and int-to-float instructions lower correctly
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: convert_s_v4f32:

 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x float> @convert_u_v4f32(<4 x i32> %x) {
   %a = uitofp <4 x i32> %x to <4 x float>
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: convert_s_v2f64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: f64x2.convert_i64x2_s
+; SIMD128-NOT: f64x2.convert_i64x2_s
 ; SIMD128-NEXT: .functype convert_s_v2f64 (v128) -> (v128){{$}}
 define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
   %a = sitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: convert_u_v2f64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: f64x2.convert_i64x2_u
+; SIMD128-NOT: f64x2.convert_i64x2_u
 ; SIMD128-NEXT: .functype convert_u_v2f64 (v128) -> (v128){{$}}
 define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
   %a = uitofp <2 x i64> %x to <2 x double>
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
 ; NO-SIMD128-NOT: f32x4

 ; SIMD128-NEXT: return $pop[[R]]
 define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = fptoui <4 x float> %x to <4 x i32>
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v2i64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_s
+; SIMD128-NOT: i64x2.trunc_sat_f64x2_s
 ; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}}
 define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) {
   %a = fptosi <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v2i64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: i64x2.trunc_sat_f64x2_u
+; SIMD128-NOT: i64x2.trunc_sat_f64x2_u
 ; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}}
 define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) {
   %a = fptoui <2 x double> %x to <2 x i64>
   ret <2 x i64> %a
 }

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s
 
 ; Test that SIMD128 intrinsics lower as expected. These intrinsics are
 ; only expected to lower successfully if the simd128 attribute is
 ; enabled and legal types are used.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: swizzle_v16i8:
-; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
 define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: add_sat_s_v16i8:
-; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v16i8:
-; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v16i8:
-; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v16i8:
-; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: avgr_u_v16i8:
-; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: popcnt_v16i8:
-; SIMD128-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype popcnt_v16i8 (v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.popcnt $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.popcnt(<16 x i8>)
 define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {
  %a = call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x)
  ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: any_v16i8:
-; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 define i32 @any_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v16i8:
-; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 define i32 @all_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitmask_v16i8:
-; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)
 define i32 @bitmask_v16i8(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v16i8:
-; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
   %a = call <16 x i8> @llvm.wasm.bitselect.v16i8(
      <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: signselect_v16i8:
-; SIMD128-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.signselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @signselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
   %a = call <16 x i8> @llvm.wasm.signselect.v16i8(
      <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: narrow_signed_v16i8:
-; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
 define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
   %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
     <8 x i16> %low, <8 x i16> %high
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: narrow_unsigned_v16i8:
-; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
 define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
   %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
     <8 x i16> %low, <8 x i16> %high
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.shuffle(
   <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
   i32, i32, i32, i32, i32)
 define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
       i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
       i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35)
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
       i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
       i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
       i32 undef, i32 undef, i32 undef, i32 2)
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v8i16:
-; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v8i16:
-; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v8i16:
-; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v8i16:
-; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: avgr_u_v8i16:
-; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: q15mulr_sat_s_v8i16:
-; SIMD128-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16>, <8 x i16>)
 define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16> %x,
                                                          <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extmul_low_s_v8i16:
-; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extmul_high_s_v8i16:
-; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extmul_low_u_v8i16:
-; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extmul_high_u_v8i16:
-; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(<16 x i8>, <16 x i8>)
 define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
   %a = call <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extadd_pairwise_s_v8i16:
-; SIMD128-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>)
 define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) {
   %a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extadd_pairwise_u_v8i16:
-; SIMD128-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>)
 define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {
   %a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: any_v8i16:
-; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 define i32 @any_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v8i16:
-; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 define i32 @all_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitmask_v8i16:
-; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)
 define i32 @bitmask_v8i16(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v8i16:
-; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
   %a = call <8 x i16> @llvm.wasm.bitselect.v8i16(
     <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: signselect_v8i16:
-; SIMD128-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.signselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @signselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
   %a = call <8 x i16> @llvm.wasm.signselect.v8i16(
     <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: narrow_signed_v8i16:
-; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)
 define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {
   %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
     <4 x i32> %low, <4 x i32> %high
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: narrow_unsigned_v8i16:
-; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)
 define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
   %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
     <4 x i32> %low, <4 x i32> %high
   )
   ret <8 x i16> %a
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: dot:
-; SIMD128-NEXT: .functype dot (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype dot (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>)
 define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y)
   ret <4 x i32> %a
 }
 
 
 ; CHECK-LABEL: extmul_low_s_v4i32:
-; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: extmul_high_s_v4i32:
-; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: extmul_low_u_v4i32:
-; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: extmul_high_u_v4i32:
-; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(<8 x i16>, <8 x i16>)
 define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
   %a = call <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: extadd_pairwise_s_v4i32:
-; SIMD128-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>)
 define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) {
   %a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: extadd_pairwise_u_v4i32:
-; SIMD128-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>)
 define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {
   %a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x)
   ret <4 x i32> %a
 }
 
 
 ; CHECK-LABEL: any_v4i32:
-; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 define i32 @any_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v4i32:
-; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 define i32 @all_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitmask_v4i32:
-; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)
 define i32 @bitmask_v4i32(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v4i32:
-; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
   %a = call <4 x i32> @llvm.wasm.bitselect.v4i32(
     <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: signselect_v4i32:
-; SIMD128-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.signselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @signselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
   %a = call <4 x i32> @llvm.wasm.signselect.v4i32(
     <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c
   )
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_s_v4i32:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_u_v4i32:
-; NO-SIMD128-NOT: f32x4
-; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0
-; SIMD128-NEXT: return $pop[[R]]
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
 declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>)
 define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_zero_signed_v4i32:
-; SIMD128-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double>)
 define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) {
   %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %a)
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32:
-; SIMD128-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
 define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
   %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
   ret <4 x i32> %v
 }
 
 
 ; CHECK-LABEL: widen_signed_v4i32:
-; SIMD128-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.widen.signed(<16 x i8>, i32 immarg)
 define <4 x i32> @widen_signed_v4i32(<16 x i8> %x) {
   %v = call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 1)
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: widen_unsigned_v4i32:
-; SIMD128-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8>, i32 immarg)
 define <4 x i32> @widen_unsigned_v4i32(<16 x i8> %x) {
   %v = call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 1)
   ret <4 x i32> %v
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: eq_v2i64:
-; SIMD128-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)
 define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: widen_low_s_v2i64:
-; SIMD128-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32>)
 define <2 x i64> @widen_low_s_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: widen_high_s_v2i64:
-; SIMD128-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32>)
 define <2 x i64> @widen_high_s_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: widen_low_u_v2i64:
-; SIMD128-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32>)
 define <2 x i64> @widen_low_u_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: widen_high_u_v2i64:
-; SIMD128-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32>)
 define <2 x i64> @widen_high_u_v2i64(<4 x i32> %x) {
   %a = call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: extmul_low_s_v2i64:
-; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(
     <4 x i32> %x, <4 x i32> %y
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: extmul_high_s_v2i64:
-; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(
     <4 x i32> %x, <4 x i32> %y
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: extmul_low_u_v2i64:
-; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(
     <4 x i32> %x, <4 x i32> %y
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: extmul_high_u_v2i64:
-; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(<4 x i32>, <4 x i32>)
 define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
   %a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(
     <4 x i32> %x, <4 x i32> %y
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: any_v2i64:
-; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 define i32 @any_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: all_v2i64:
-; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 define i32 @all_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitmask_v2i64:
-; SIMD128-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitmask_v2i64 (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare i32 @llvm.wasm.bitmask.v2i64(<2 x i64>)
 define i32 @bitmask_v2i64(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.bitmask.v2i64(<2 x i64> %x)
   ret i32 %a
 }
 
 ; CHECK-LABEL: bitselect_v2i64:
-; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   %a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
     <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: signselect_v2i64:
-; SIMD128-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.signselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @signselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   %a = call <2 x i64> @llvm.wasm.signselect.v2i64(
     <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c
   )
   ret <2 x i64> %a
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v4f32:
-; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) {
   %a = call <4 x float> @llvm.wasm.bitselect.v4f32(
     <4 x float> %v1, <4 x float> %v2, <4 x float> %c
   )
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: pmin_v4f32:
-; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) {
   %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: pmax_v4f32:
-; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) {
   %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: ceil_v4f32:
-; SIMD128-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.ceil.v4f32(<4 x float>)
 define <4 x float> @ceil_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.ceil.v4f32(<4 x float> %a)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: floor_v4f32:
-; SIMD128-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.floor.v4f32(<4 x float>)
 define <4 x float> @floor_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.floor.v4f32(<4 x float> %a)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: trunc_v4f32:
-; SIMD128-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.trunc.v4f32(<4 x float>)
 define <4 x float> @trunc_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.trunc.v4f32(<4 x float> %a)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: nearest_v4f32:
-; SIMD128-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.nearest.v4f32(<4 x float>)
 define <4 x float> @nearest_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.wasm.nearest.v4f32(<4 x float> %a)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: qfma_v4f32:
-; SIMD128-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.qfma.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @qfma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
   %v = call <4 x float> @llvm.wasm.qfma.v4f32(
     <4 x float> %a, <4 x float> %b, <4 x float> %c
   )
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: qfms_v4f32:
-; SIMD128-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.qfms.v4f32(<4 x float>, <4 x float>, <4 x float>)
 define <4 x float> @qfms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
   %v = call <4 x float> @llvm.wasm.qfms.v4f32(
     <4 x float> %a, <4 x float> %b, <4 x float> %c
   )
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: demote_zero_v4f32:
-; SIMD128-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.wasm.demote.zero(<2 x double>)
 define <4 x float> @demote_zero_v4f32(<2 x double> %a) {
   %v = call <4 x float> @llvm.wasm.demote.zero(<2 x double> %a)
   ret <4 x float> %v
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: bitselect_v2f64:
-; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) {
   %a = call <2 x double> @llvm.wasm.bitselect.v2f64(
     <2 x double> %v1, <2 x double> %v2, <2 x double> %c
   )
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: pmin_v2f64:
-; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) {
   %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: pmax_v2f64:
-; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) {
   %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: ceil_v2f64:
-; SIMD128-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.ceil.v2f64(<2 x double>)
 define <2 x double> @ceil_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.ceil.v2f64(<2 x double> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: floor_v2f64:
-; SIMD128-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.floor.v2f64(<2 x double>)
 define <2 x double> @floor_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.floor.v2f64(<2 x double> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: trunc_v2f64:
-; SIMD128-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.trunc.v2f64(<2 x double>)
 define <2 x double> @trunc_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.trunc.v2f64(<2 x double> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: nearest_v2f64:
-; SIMD128-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.nearest.v2f64(<2 x double>)
 define <2 x double> @nearest_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.wasm.nearest.v2f64(<2 x double> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: qfma_v2f64:
-; SIMD128-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.qfma.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @qfma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
   %v = call <2 x double> @llvm.wasm.qfma.v2f64(
     <2 x double> %a, <2 x double> %b, <2 x double> %c
   )
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: qfms_v2f64:
-; SIMD128-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.qfms.v2f64(<2 x double>, <2 x double>, <2 x double>)
 define <2 x double> @qfms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
   %v = call <2 x double> @llvm.wasm.qfms.v2f64(
     <2 x double> %a, <2 x double> %b, <2 x double> %c
   )
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: convert_low_signed_v2f64:
-; SIMD128-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.convert.low.signed(<4 x i32>)
 define <2 x double> @convert_low_signed_v2f64(<4 x i32> %a) {
   %v = call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: convert_low_unsigned_v2f64:
-; SIMD128-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32>)
 define <2 x double> @convert_low_unsigned_v2f64(<4 x i32> %a) {
   %v = call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %a)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: promote_low_v2f64:
-; SIMD128-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
-; SIMD128-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.wasm.promote.low(<4 x float>)
 define <2 x double> @promote_low_v2f64(<4 x float> %a) {
   %v = call <2 x double> @llvm.wasm.promote.low(<4 x float> %a)
   ret <2 x double> %v
 }

llvm/test/CodeGen/WebAssembly/simd-load-splat.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s
 
 ; Regression test for an ISel failure when a splatted load had more
 ; than one use. The main tests for load_splat are in simd-offset.ll.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: load_splat:

llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8

llvm/test/CodeGen/WebAssembly/simd-noopt.ll

-; RUN: llc < %s -fast-isel -mattr=+simd128,+sign-ext -verify-machineinstrs
-
-;; Ensures fastisel produces valid code when storing and loading split
-;; up v2i64 values. Lowering away v2i64s is a temporary measure while
-;; V8 does not have support for i64x2.* operations, and is done when
-;; -wasm-enable-unimplemented-simd is not present. This is a
-;; regression test for a bug that crashed llc after fastisel produced
-;; machineinstrs that used registers that had never been defined.
-
-target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown"
-
-define i64 @foo(<2 x i64> %vec) {
-entry:
-  %vec.addr = alloca <2 x i64>, align 16
-  store <2 x i64> %vec, <2 x i64>* %vec.addr, align 16
-  %0 = load <2 x i64>, <2 x i64>* %vec.addr, align 16
-  %1 = extractelement <2 x i64> %0, i32 0
-  ret i64 %1
-}

llvm/test/CodeGen/WebAssembly/simd-reductions.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Tests that redundant masking and conversions are folded out
 ; following SIMD reduction instructions.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
 declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
 
 ; CHECK-LABEL: any_v16i8_trunc:
-; SIMD128-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_trunc(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v16i8_ne:
-; SIMD128-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_ne(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v16i8_eq:
-; SIMD128-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v16i8_eq(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v16i8_trunc:
-; SIMD128-NEXT: .functype all_v16i8_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_trunc(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v16i8_ne:
-; SIMD128-NEXT: .functype all_v16i8_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_ne(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v16i8_eq:
-; SIMD128-NEXT: .functype all_v16i8_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v16i8_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v16i8_eq(<16 x i8> %x) {
   %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
 declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
 
 ; CHECK-LABEL: any_v8i16_trunc:
-; SIMD128-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_trunc(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v8i16_ne:
-; SIMD128-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_ne(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v8i16_eq:
-; SIMD128-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v8i16_eq(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v8i16_trunc:
-; SIMD128-NEXT: .functype all_v8i16_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_trunc(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v8i16_ne:
-; SIMD128-NEXT: .functype all_v8i16_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_ne(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v8i16_eq:
-; SIMD128-NEXT: .functype all_v8i16_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v8i16_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v8i16_eq(<8 x i16> %x) {
   %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
 declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
 
 ; CHECK-LABEL: any_v4i32_trunc:
-; SIMD128-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_trunc(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v4i32_ne:
-; SIMD128-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_ne(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v4i32_eq:
-; SIMD128-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v4i32_eq(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v4i32_trunc:
-; SIMD128-NEXT: .functype all_v4i32_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_trunc(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v4i32_ne:
-; SIMD128-NEXT: .functype all_v4i32_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_ne(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v4i32_eq:
-; SIMD128-NEXT: .functype all_v4i32_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v4i32_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v4i32_eq(<4 x i32> %x) {
   %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
 declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
 
 ; CHECK-LABEL: any_v2i64_trunc:
-; SIMD128-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_trunc(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v2i64_ne:
-; SIMD128-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_ne(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: any_v2i64_eq:
-; SIMD128-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @any_v2i64_eq(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v2i64_trunc:
-; SIMD128-NEXT: .functype all_v2i64_trunc (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_trunc (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_trunc(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = trunc i32 %a to i1
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v2i64_ne:
-; SIMD128-NEXT: .functype all_v2i64_ne (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_ne (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_ne(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = icmp ne i32 %a, 0
   %c = zext i1 %b to i32
   ret i32 %c
 }
 
 ; CHECK-LABEL: all_v2i64_eq:
-; SIMD128-NEXT: .functype all_v2i64_eq (v128) -> (i32){{$}}
-; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; CHECK-NEXT: .functype all_v2i64_eq (v128) -> (i32){{$}}
+; CHECK-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
 define i32 @all_v2i64_eq(<2 x i64> %x) {
   %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
   %b = icmp eq i32 %a, 1
   %c = zext i1 %b to i32
   ret i32 %c
 }

llvm/test/CodeGen/WebAssembly/simd-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
 
 ; Test that vector selects of various varieties lower correctly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8

llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that vector sign extensions lower to shifts
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sext_v16i8:

llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
 
 ; Test that operations that are not supported by SIMD are properly
 ; unrolled.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================

llvm/test/CodeGen/WebAssembly/simd.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 vector manipulation operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: const_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v16i8 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @const_v16i8() {
   ret <16 x i8> <i8 00, i8 01, i8 02, i8 03, i8 04, i8 05, i8 06, i8 07,
                  i8 08, i8 09, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
 }
define <16 x i8> @build_v16i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3,
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: const_v8i16:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v8i16 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @const_v8i16() {
   ret <8 x i16> <i16 256, i16 770, i16 1284, i16 1798,
                  i16 2312, i16 2826, i16 3340, i16 3854>
 }
 
define <8 x i16> @build_v8i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3,
   ret <8 x i16> %res
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4i32:
 ; NO-SIMD128-NOT: i32x4
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4i32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 50462976, 117835012, 185207048, 252579084{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @const_v4i32() {
   ret <4 x i32> <i32 50462976, i32 117835012, i32 185207048, i32 252579084>
 }
 
 ; CHECK-LABEL: splat_v4i32:
define <4 x i32> @build_v4i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
   ret <4 x i32> %res
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2i64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 506097522914230528, 1084818905618843912{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @const_v2i64() {
   ret <2 x i64> <i64 506097522914230528, i64 1084818905618843912>
 }
 
 ; CHECK-LABEL: splat_v2i64:
define <2 x i64> @build_v2i64(i64 %x0, i64 %x1) {
   ret <2 x i64> %res
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @const_v4f32() {
   ret <4 x float> <float 0x3860402000000000, float 0x38e0c0a080000000,
                    float 0x3961412100000000, float 0x39e1c1a180000000>
 }
define <4 x float> @build_v4f32(float %x0, float %x1, float %x2, float %x3) {
   ret <4 x float> %res
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @const_v2f64() {
   ret <2 x double> <double 0x0706050403020100, double 0x0F0E0D0C0B0A0908>
 }
 
 ; CHECK-LABEL: splat_v2f64:

llvm/test/MC/WebAssembly/basic-assembly.s

-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+reference-types,atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+reference-types,atomics,+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors, but don't check any output:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+reference-types,+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling -o %t.o < %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+reference-types,+atomics,+simd128,+nontrapping-fptoint,+exception-handling -o %t.o < %s
 
 
 empty_func:
     .functype empty_func () -> ()
     end_function
 
 test0:
 # local labels can appear between label and its .functype.

llvm/test/MC/WebAssembly/data-section.s

-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN32 %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN32 %s
 
 # Same again for wasm64
 
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN64 %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefixes=BIN,BIN64 %s
 
 # Minimal test for data sections.
 
 test0:
     .functype   test0 () -> (i32)
     i32.const .L.str
 .Ltestlabel:
     end_function

llvm/test/MC/WebAssembly/simd-encodings.s

-# RUN: llvm-mc -show-encoding -triple=wasm32-unknown-unknown -mattr=+unimplemented-simd128 < %s | FileCheck %s
+# RUN: llvm-mc -show-encoding -triple=wasm32-unknown-unknown -mattr=+simd128 < %s | FileCheck %s
 
 main:
     .functype main () -> ()
 
     # CHECK: v128.load 48 # encoding: [0xfd,0x00,0x04,0x30]
     v128.load 48
 
     # CHECK: i16x8.load8x8_s 32 # encoding: [0xfd,0x01,0x03,0x20]

llvm/test/MC/WebAssembly/type-index.s

-# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+reference-types,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+reference-types,+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
 # Check that it converts to .o without errors:
-# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+reference-types,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefix=BIN %s
+# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj -mattr=+reference-types,+simd128,+nontrapping-fptoint,+exception-handling < %s | obj2yaml | FileCheck -check-prefix=BIN %s
 
 # Minimal test for type indices and table references in call_indirect.
 
 test0:
     .functype   test0 (i32) -> (i32)
     call_indirect (f64) -> (f64)
     end_function
 

llvm/test/MC/WebAssembly/types.ll

-; RUN: llc -mattr=+unimplemented-simd128 -filetype=obj %s -o - | obj2yaml | FileCheck %s
+; RUN: llc -mattr=+simd128 -filetype=obj %s -o - | obj2yaml | FileCheck %s
 
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @i32()
 declare i64 @i64()
 declare float @f32()
 declare double @f64()
 declare <16 x i8> @v16i8()

llvm/test/MC/WebAssembly/wasm64.s

-# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
-# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+atomics,+unimplemented-simd128,+nontrapping-fptoint,+exception-handling -o - < %s | obj2yaml | FileCheck %s -check-prefix=BIN
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling < %s | FileCheck %s
+# RUN: llvm-mc -triple=wasm64-unknown-unknown -filetype=obj -mattr=+atomics,+simd128,+nontrapping-fptoint,+exception-handling -o - < %s | obj2yaml | FileCheck %s -check-prefix=BIN
 
 # Most of our other tests are for wasm32, this one adds some wasm64 specific tests.
 
 test:
     .functype   test (i64) -> ()
     .local      i64
 
     ### basic loads