A 1-bit smulo overflows is both inputs are -1 since the result
should be +1 which can't be represented in a signed 1 bit value.
We can detect this with an AND and a setcc. The multiply result
can also use the same AND.
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[DAGCombiner] Optimize 1-bit smulo to AND+SETNE. ClosedPublic Authored by craig.topper on Feb 28 2021, 9:39 AM.
Details Summary A 1-bit smulo overflows is both inputs are -1 since the result We can detect this with an AND and a setcc. The multiply result
Diff Detail
Event TimelineHerald added subscribers: ecnelises, pengfei, hiraditya. · View Herald TranscriptFeb 28 2021, 9:39 AM
This revision is now accepted and ready to land.Mar 13 2021, 4:18 AM This revision was landed with ongoing or failed builds.Mar 13 2021, 9:48 AM Closed by commit rG5b825433d785: [DAGCombiner] Optimize 1-bit smulo to AND+SETNE. (authored by craig.topper). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 330460 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/vec_smulo.ll
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Why not just handle the simplification of SMULO/UMULO of i1/vXi1 in getNode() ? I doubt any hardware has actual instructions for bool types so will expand to icmp/logic ops whatever.