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[DAGCombiner] Optimize 1-bit smulo to AND+SETNE.
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Authored by craig.topper on Feb 28 2021, 9:39 AM.

Details

Summary

A 1-bit smulo overflows is both inputs are -1 since the result
should be +1 which can't be represented in a signed 1 bit value.

We can detect this with an AND and a setcc. The multiply result
can also use the same AND.

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Event Timeline

craig.topper created this revision.Feb 28 2021, 9:39 AM
craig.topper requested review of this revision.Feb 28 2021, 9:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 28 2021, 9:39 AM
RKSimon added inline comments.Feb 28 2021, 10:27 AM
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
4669

Why not just handle the simplification of SMULO/UMULO of i1/vXi1 in getNode() ? I doubt any hardware has actual instructions for bool types so will expand to icmp/logic ops whatever.

craig.topper added inline comments.Feb 28 2021, 10:34 AM
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
4669

You'd have to return a MERGE_VALUES which seemed a little weird to do from getNode. You asked for a single node, but got 3 nodes.

RKSimon accepted this revision.Mar 13 2021, 4:18 AM

OK, happy for this to be treated as a fold. LGTM

This revision is now accepted and ready to land.Mar 13 2021, 4:18 AM
This revision was landed with ongoing or failed builds.Mar 13 2021, 9:48 AM
This revision was automatically updated to reflect the committed changes.