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Differential D97360

[TTI] Consider select form of and/or i1 as having arithmetic cost
ClosedPublic

Authored by aqjune on Feb 23 2021, 11:11 PM.

Details

Reviewers
fhahn
nikic
spatel
dmgreen
lebedev.ri
Commits
rGc89d9d8a48c0: [TTI] Consider select form of and/or i1 as having arithmetic cost
Summary

This is a patch that updates the cost of select i1 a, b, false to be equivalent to that of and i1 a, b
as well as the cost of select i1 a, true, b equivalent to or i1 a, b.

Until now, these selects were folded into and/or i1 by InstCombine, but the transformation is poison-unsafe.
This is a step towards removing the unsafe transformation. D93065 has relevant transformations linked.
These selects should be translated into the assemblies as and/or i1 do in the same manner. The cost should be equivalent.

Diff Detail

Unit TestsFailed

TimeTest
80 msx64 debian > LLVM.Analysis/CostModel/X86::logicalop.ll
110 msx64 windows > LLVM.Analysis/CostModel/X86::logicalop.ll

Event Timeline

aqjune requested review of this revision.Feb 23 2021, 11:11 PM
aqjune created this revision.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2021, 11:11 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
aqjune added a comment.Feb 23 2021, 11:12 PM

This patch has tests missing, and I'd like to add these. Where should I go to do this?

Harbormaster completed remote builds in B90544: Diff 325992.Feb 24 2021, 12:20 AM
lebedev.ri added a reviewer: lebedev.ri.Feb 24 2021, 8:13 AM
lebedev.ri added a subscriber: lebedev.ri.
In D97360#2584048, @aqjune wrote:

This patch has tests missing, and I'd like to add these. Where should I go to do this?

llvm/test/Analysis/CostModel/

aqjune updated this revision to Diff 326260.Feb 24 2021, 6:23 PM

Thanks!
Tests added

Herald added subscribers: frasercrmck, kerbowa, luismarques and 23 others. · View Herald TranscriptFeb 24 2021, 6:23 PM
aqjune updated this revision to Diff 326263.Feb 24 2021, 6:37 PM

Update tests to test throughput and size both

aqjune updated this revision to Diff 326264.Feb 24 2021, 6:39 PM

Clang-format

Harbormaster completed remote builds in B90724: Diff 326260.Feb 24 2021, 9:20 PM
Harbormaster completed remote builds in B90726: Diff 326263.Feb 24 2021, 9:30 PM
Harbormaster completed remote builds in B90727: Diff 326264.Feb 24 2021, 9:50 PM
spatel added a comment.Mar 1 2021, 7:39 AM

I can't tell from the tests (so we should probably add at least 1 to confirm) - do we expect the same behavior for vector types?

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
997

It would be nice to have a code comment here to show the expected patterns:

// select x, y, false --> x & y
// select x, true, y --> x | y
aqjune added a comment.Mar 1 2021, 7:41 AM

Yes, vectors are expected to have the same cost. I'll update tests for them.

spatel added a comment.Mar 1 2021, 8:03 AM
In D97360#2594268, @aqjune wrote:

Yes, vectors are expected to have the same cost. I'll update tests for them.

Thanks - IIUC, we're also going to need to some codegen changes to avoid regressions. For example (the icmps are to avoid diffs due to lack of signext/zeroext specifiers on parameters with vector type):

define <4 x i1> @b(<4 x i32> %x, <4 x i32> %y) {
  %c1 = icmp eq <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
  %c2 = icmp sgt <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
  %s = select <4 x i1> %c1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i1> %c2
  ret <4 x i1> %s
}
define <4 x i1> @b2(<4 x i32> %x, <4 x i32> %y) {
  %c1 = icmp eq <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
  %c2 = icmp sgt <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
  %s = or <4 x i1> %c1, %c2
  ret <4 x i1> %s
}
$ llc -o - logical.ll -mattr=avx -mtriple=x86_64--
_b:                                     ## @b
	vmovdqa	LCPI2_0(%rip), %xmm2            ## xmm2 = [42,42,42,42]
	vpcmpeqd	%xmm2, %xmm0, %xmm0
	vpcmpgtd	%xmm2, %xmm1, %xmm1
	vblendvps	%xmm0, LCPI2_1(%rip), %xmm1, %xmm0
	retq
_b2:                                    ## @b2
	vmovdqa	LCPI3_0(%rip), %xmm2            ## xmm2 = [42,42,42,42]
	vpcmpeqd	%xmm2, %xmm0, %xmm0
	vpcmpgtd	%xmm2, %xmm1, %xmm1
	vpor	%xmm1, %xmm0, %xmm0
	retq
aqjune updated this revision to Diff 327125.Mar 1 2021, 8:21 AM

add tests for vector operands

aqjune added a comment.Mar 1 2021, 8:26 AM
In D97360#2594315, @spatel wrote:

Thanks - IIUC, we're also going to need to some codegen changes to avoid regressions. For example (the icmps are to avoid diffs due to lack of signext/zeroext specifiers on parameters with vector type):

define <4 x i1> @b(<4 x i32> %x, <4 x i32> %y) {
  %c1 = icmp eq <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
  %c2 = icmp sgt <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
  %s = select <4 x i1> %c1, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i1> %c2
  ret <4 x i1> %s
}
define <4 x i1> @b2(<4 x i32> %x, <4 x i32> %y) {
  %c1 = icmp eq <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
  %c2 = icmp sgt <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
  %s = or <4 x i1> %c1, %c2
  ret <4 x i1> %s
}
$ llc -o - logical.ll -mattr=avx -mtriple=x86_64--
_b:                                     ## @b
	vmovdqa	LCPI2_0(%rip), %xmm2            ## xmm2 = [42,42,42,42]
	vpcmpeqd	%xmm2, %xmm0, %xmm0
	vpcmpgtd	%xmm2, %xmm1, %xmm1
	vblendvps	%xmm0, LCPI2_1(%rip), %xmm1, %xmm0
	retq
_b2:                                    ## @b2
	vmovdqa	LCPI3_0(%rip), %xmm2            ## xmm2 = [42,42,42,42]
	vpcmpeqd	%xmm2, %xmm0, %xmm0
	vpcmpgtd	%xmm2, %xmm1, %xmm1
	vpor	%xmm1, %xmm0, %xmm0
	retq

Thank you for the info..!
I'll check whether regression happens with different targets as well and make patches if any.

select form of and/or operations are eagerly folded by InstCombine currently, so they'll look good hopefully.

aqjune marked an inline comment as done.Mar 1 2021, 8:27 AM
aqjune added a comment.Mar 1 2021, 8:51 AM

Would adding 'select -> and/or i1' transformation into the end of CodeGenPrepare::runOnFunction work?
I see that there are quite many targets that generate different assemblies for select vs. and/or i1.

spatel added inline comments.Mar 1 2021, 8:58 AM
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
1001

Assert that Op[0/1]->getType()->getScalarSizeInBits() == 1 ?

spatel accepted this revision.Mar 1 2021, 9:00 AM
In D97360#2594420, @aqjune wrote:

Would adding 'select -> and/or i1' transformation into the end of CodeGenPrepare::runOnFunction work?
I see that there are quite many targets that generate different assemblies for select vs. and/or i1.

No, I think we should adjust some code in DAGCombiner for this. I was already looking at it, so I can continue if you want to keep working on the IR side.

LGTM.

This revision is now accepted and ready to land.Mar 1 2021, 9:00 AM
aqjune added a comment.Mar 1 2021, 9:04 AM
In D97360#2594461, @spatel wrote:
In D97360#2594420, @aqjune wrote:

Would adding 'select -> and/or i1' transformation into the end of CodeGenPrepare::runOnFunction work?
I see that there are quite many targets that generate different assemblies for select vs. and/or i1.

No, I think we should adjust some code in DAGCombiner for this. I was already looking at it, so I can continue if you want to keep working on the IR side.

LGTM.

This is great, thank you!

This revision was landed with ongoing or failed builds.Mar 1 2021, 9:18 AM
Closed by commit rGc89d9d8a48c0: [TTI] Consider select form of and/or i1 as having arithmetic cost (authored by aqjune). · Explain Why
This revision was automatically updated to reflect the committed changes.
aqjune added a commit: rGc89d9d8a48c0: [TTI] Consider select form of and/or i1 as having arithmetic cost.
aqjune marked an inline comment as done.Mar 1 2021, 9:27 AM
Harbormaster completed remote builds in B91344: Diff 327125.Mar 1 2021, 9:29 AM
spatel mentioned this in D97730: [SDAG] allow vector types for select->logic folds.Mar 1 2021, 1:45 PM
spatel mentioned this in rG7fce3322a283: [SDAG] allow vector types for select->logic folds.Mar 2 2021, 6:30 AM
dmgreen mentioned this in D99884: [LV] Logical and/or select costs.Apr 5 2021, 7:22 AM
dmgreen mentioned this in rG8675ef100f8c: [LV] Logical and/or select costs.Apr 8 2021, 2:40 AM

Revision Contents

PathSize
llvm/
include/
llvm/
Analysis/
15 lines
test/
Analysis/
CostModel/
AArch64/
28 lines
AMDGPU/
19 lines
ARM/
75 lines
PowerPC/
27 lines
RISCV/
22 lines
SystemZ/
19 lines
X86/
38 lines

Diff 326260

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===// //===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
/// This file provides helpers for the implementation of /// This file provides helpers for the implementation of
/// a TargetTransformInfo-conforming class. /// a TargetTransformInfo-conforming class.
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H #define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/VectorUtils.h" #include "llvm/Analysis/VectorUtils.h"
#include "llvm/IR/DataLayout.h" #include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/GetElementPtrTypeIterator.h" #include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Operator.h" #include "llvm/IR/Operator.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
using namespace llvm::PatternMatch;
namespace llvm { namespace llvm {
/// Base class for use as a mix-in that aids implementing /// Base class for use as a mix-in that aids implementing
/// a TargetTransformInfo-compatible class. /// a TargetTransformInfo-compatible class.
class TargetTransformInfoImplBase { class TargetTransformInfoImplBase {
protected: protected:
typedef TargetTransformInfo TTI; typedef TargetTransformInfo TTI;
▲ Show 20 Lines • Show All 950 Lines • ▼ Show 20 Lines int getUserCost(const User *U, ArrayRef<const Value *> Operands,
} }
case Instruction::Load: { case Instruction::Load: {
auto *LI = cast<LoadInst>(U); auto *LI = cast<LoadInst>(U);
return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(), return TargetTTI->getMemoryOpCost(Opcode, U->getType(), LI->getAlign(),
LI->getPointerAddressSpace(), LI->getPointerAddressSpace(),
CostKind, I); CostKind, I);
} }
case Instruction::Select: { case Instruction::Select: {
const Value *Op0, *Op1;
if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
spatelUnsubmitted
Done
ReplyInline Actions

It would be nice to have a code comment here to show the expected patterns:

// select x, y, false --> x & y
// select x, true, y --> x | y
spatel: It would be nice to have a code comment here to show the expected patterns: // select x, y…
match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
TTI::OperandValueProperties Op1VP = TTI::OP_None;
TTI::OperandValueProperties Op2VP = TTI::OP_None;
TTI::OperandValueKind Op1VK = TTI::getOperandInfo(Op0, Op1VP);
spatelUnsubmitted
Done
ReplyInline Actions

Assert that Op[0/1]->getType()->getScalarSizeInBits() == 1 ?

spatel: Assert that Op[0/1]->getType()->getScalarSizeInBits() == 1 ?
TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP);
SmallVector<const Value *, 2> Operands{Op0, Op1};
return TargetTTI->getArithmeticInstrCost(
match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And,
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-            match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And,
-            Ty, CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
+            match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
+            CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - match(U, m_LogicalOr()) ? Instruction…
Ty, CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, I);
}
Type *CondTy = U->getOperand(0)->getType(); Type *CondTy = U->getOperand(0)->getType();
return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy, return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
CmpInst::BAD_ICMP_PREDICATE, CmpInst::BAD_ICMP_PREDICATE,
CostKind, I); CostKind, I);
} }
case Instruction::ICmp: case Instruction::ICmp:
case Instruction::FCmp: { case Instruction::FCmp: {
Type *ValTy = U->getOperand(0)->getType(); Type *ValTy = U->getOperand(0)->getType();
▲ Show 20 Lines • Show All 117 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/AArch64/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-THROUGHPUT
; RUN: opt < %s -cost-model -analyze -cost-kind=code-size -mtriple=aarch64-- | FileCheck %s --check-prefix=CHECK-SIZE
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; CHECK-THROUGHPUT-LABEL: 'op'
; CHECK-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-SIZE-LABEL: 'op'
; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/AMDGPU/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
define amdgpu_kernel void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; CHECK-LABEL: 'op'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/ARM/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-RECIP
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-RECIP
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-RECIP
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-RECIP
; RUN: opt < %s -cost-model -analyze -cost-kind=code-size -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE-SIZE
; RUN: opt < %s -cost-model -analyze -cost-kind=code-size -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON-SIZE
; RUN: opt < %s -cost-model -analyze -cost-kind=code-size -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1-SIZE
; RUN: opt < %s -cost-model -analyze -cost-kind=code-size -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2-SIZE
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; CHECK-MVE-RECIP-LABEL: 'op'
; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-NEON-RECIP-LABEL: 'op'
; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-THUMB1-RECIP-LABEL: 'op'
; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-THUMB1-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; CHECK-THUMB2-RECIP-LABEL: 'op'
; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-THUMB2-RECIP-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; CHECK-MVE-SIZE-LABEL: 'op'
; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef
; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef
; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; CHECK-NEON-SIZE-LABEL: 'op'
; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef
; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef
; CHECK-NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; CHECK-THUMB1-SIZE-LABEL: 'op'
; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef
; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef
; CHECK-THUMB1-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
; CHECK-THUMB2-SIZE-LABEL: 'op'
; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %band = and i1 undef, undef
; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %bor = or i1 undef, undef
; CHECK-THUMB2-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/PowerPC/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck %s
; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -mattr=+vsx | FileCheck --check-prefix=CHECK-P9 %s
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; CHECK-LABEL: 'op'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; CHECK-P9-LABEL: 'op'
; CHECK-P9-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-P9-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-P9-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-P9-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-P9-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/RISCV/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -mtriple=riscv32 -cost-model -analyze < %s \
; RUN: | FileCheck %s -check-prefix=RVI
; RUN: opt -mtriple=riscv64 -cost-model -analyze < %s \
; RUN: | FileCheck %s -check-prefix=RVI
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; RVI-LABEL: 'op'
; RVI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; RVI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; RVI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; RVI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; RVI-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/SystemZ/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; CHECK-LABEL: 'op'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}

llvm/test/Analysis/CostModel/X86/logicalop.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 | FileCheck %s -check-prefixes=SSE2
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.1 | FileCheck %s -check-prefixes=SSE41
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s -check-prefixes=AVX,AVX1
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s -check-prefixes=AVX,AVX2
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl | FileCheck %s -check-prefixes=AVX,AVX512,AVX512F
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw,+avx512vl | FileCheck %s -check-prefixes=AVX,AVX512,AVX512BW
define void @op() {
; Logical and/or - select's cost must be equivalent to that of binop
; SSE2-LABEL: 'op'
; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SSE41-LABEL: 'op'
; SSE41-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; SSE41-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; SSE41-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; SSE41-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; SSE41-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; AVX-LABEL: 'op'
; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sand = select i1 undef, i1 undef, i1 false
; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %band = and i1 undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sor = select i1 undef, i1 true, i1 undef
; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bor = or i1 undef, undef
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
%sand = select i1 undef, i1 undef, i1 false
%band = and i1 undef, undef
%sor = select i1 undef, i1 true, i1 undef
%bor = or i1 undef, undef
ret void
}