This is an archive of the discontinued LLVM Phabricator instance.

Differential D97325

[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported.
ClosedPublic

Authored by craig.topper on Feb 23 2021, 12:08 PM.

Details

Reviewers
RKSimon
spatel
rogfer01
luismarques
Commits
rGfe50be12c8b8: [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where…
Summary

Rather than converting 3 signbits to bools and comparing them,
we can do bitwise logic on the whole vector and convert the
resulting sign bit to a bool at the end.

This is still a different algorithm than what we do in LegalizeDAG
through expandSADDOSSUBO. That algorithm needs to know that the
RHS of SSUBO is > 0, but that's costly when the type is split.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 23 2021, 12:08 PM
Herald added subscribers: frasercrmck, apazos, sameer.abuasal and 18 others. · View Herald TranscriptFeb 23 2021, 12:08 PM
craig.topper requested review of this revision.Feb 23 2021, 12:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2021, 12:09 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added inline comments.Feb 23 2021, 12:12 PM
llvm/test/CodeGen/RISCV/xaluo.ll
1952

Well this isn't at all interesting for testing smulo. I'll put a different constant here.

craig.topper updated this revision to Diff 325873.Feb 23 2021, 12:21 PM

Update after fixing test to not allow a mul to become an add.

Harbormaster completed remote builds in B90461: Diff 325869.Feb 23 2021, 2:33 PM
Harbormaster completed remote builds in B90464: Diff 325873.Feb 23 2021, 3:07 PM
RKSimon accepted this revision.Feb 24 2021, 2:28 AM

LGTM with one minor

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
3687

This "Node->getOpcode() == ISD::SADDO" is done several times in ExpandIntRes_SADDSUBO now (including a switch that can probably be reduced to an assert + compares).

This revision is now accepted and ready to land.Feb 24 2021, 2:28 AM
This revision was landed with ongoing or failed builds.Feb 24 2021, 10:06 AM
Closed by commit rGfe50be12c8b8: [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGfe50be12c8b8: [LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where….

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
32 lines
test/
CodeGen/
AArch64/
54 lines
54 lines
ARM/
134 lines
150 lines
134 lines
152 lines
RISCV/
21 lines
21 lines
46 lines
46 lines
125 lines
Thumb2/
170 lines

Diff 325869

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 3,656 Lines • ▼ Show 20 Lines if (HasCarryOp) {
// RHSSign -> RHS < 0 // RHSSign -> RHS < 0
// SumSign -> Sum < 0 // SumSign -> Sum < 0
// //
// Add: // Add:
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
// Sub: // Sub:
// Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
// //
EVT OType = Node->getValueType(1); // To get better codegen we can rewrite this by doing bitwise math on
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); // the integers and extract the final sign bit at the end. So the
// above becomes:
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETLT); //
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETLT); // Add:
SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
Node->getOpcode() == ISD::SADDO ? // Sub:
ISD::SETEQ : ISD::SETNE); // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
//
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETLT); // NOTE: This is different than the expansion we do in expandSADDSUBO
SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); // because it is more costly to determine the RHS is > 0 for SSUBO with the
// integers split.
EVT VT = LHS.getValueType();
SDValue SignsMatch = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
if (Node->getOpcode() == ISD::SADDO)
RKSimonUnsubmitted
Not Done
ReplyInline Actions

This "Node->getOpcode() == ISD::SADDO" is done several times in ExpandIntRes_SADDSUBO now (including a switch that can probably be reduced to an assert + compares).

RKSimon: This "Node->getOpcode() == ISD::SADDO" is done several times in ExpandIntRes_SADDSUBO now…
SignsMatch = DAG.getNOT(dl, SignsMatch, VT);
Ovf = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); SDValue SumSignNE = DAG.getNode(ISD::XOR, dl, VT, LHS, Sum);
Ovf = DAG.getNode(ISD::AND, dl, VT, SignsMatch, SumSignNE);
EVT OType = Node->getValueType(1);
Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
} }
// Use the calculated overflow everywhere. // Use the calculated overflow everywhere.
ReplaceValueWith(SDValue(Node, 1), Ovf); ReplaceValueWith(SDValue(Node, 1), Ovf);
} }
void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) { SDValue &Lo, SDValue &Hi) {
▲ Show 20 Lines • Show All 1,226 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Show First 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x7, #0 // =0 ; CHECK-NEXT: adds x8, x2, x6
; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: cmp x3, #0 // =0
; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: adds x11, x2, x6
; CHECK-NEXT: adcs x12, x3, x7 ; CHECK-NEXT: adcs x12, x3, x7
; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: eor x10, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: eor x13, x3, x12
; CHECK-NEXT: cset w15, lt ; CHECK-NEXT: cinv x14, x9, ge
; CHECK-NEXT: cinv x14, x8, ge ; CHECK-NEXT: bics xzr, x13, x10
; CHECK-NEXT: cmp w10, w15 ; CHECK-NEXT: asr x10, x12, #63
; CHECK-NEXT: cset w10, ne ; CHECK-NEXT: csel x2, x10, x8, lt
; CHECK-NEXT: asr x13, x12, #63 ; CHECK-NEXT: csel x3, x14, x12, lt
; CHECK-NEXT: tst w9, w10 ; CHECK-NEXT: adds x8, x0, x4
; CHECK-NEXT: csel x2, x13, x11, ne ; CHECK-NEXT: adcs x10, x1, x5
; CHECK-NEXT: csel x3, x14, x12, ne ; CHECK-NEXT: eor x11, x1, x5
; CHECK-NEXT: cmp x5, #0 // =0 ; CHECK-NEXT: cmp x10, #0 // =0
; CHECK-NEXT: cset w9, lt ; CHECK-NEXT: eor x12, x1, x10
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cinv x9, x9, ge
; CHECK-NEXT: cset w10, lt ; CHECK-NEXT: bics xzr, x12, x11
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: cset w9, eq ; CHECK-NEXT: csel x8, x11, x8, lt
; CHECK-NEXT: adds x11, x0, x4 ; CHECK-NEXT: csel x1, x9, x10, lt
; CHECK-NEXT: adcs x12, x1, x5 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, lt
; CHECK-NEXT: cinv x8, x8, ge
; CHECK-NEXT: cmp w10, w13
; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: asr x9, x12, #63
; CHECK-NEXT: csel x9, x9, x11, ne
; CHECK-NEXT: csel x1, x8, x12, ne
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x7, #0 // =0 ; CHECK-NEXT: subs x8, x2, x6
; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: cmp x3, #0 // =0
; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: subs x11, x2, x6
; CHECK-NEXT: sbcs x12, x3, x7 ; CHECK-NEXT: sbcs x12, x3, x7
; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: eor x10, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: eor x13, x3, x12
; CHECK-NEXT: cset w15, lt ; CHECK-NEXT: cinv x14, x9, ge
; CHECK-NEXT: cinv x14, x8, ge ; CHECK-NEXT: tst x10, x13
; CHECK-NEXT: cmp w10, w15 ; CHECK-NEXT: asr x10, x12, #63
; CHECK-NEXT: cset w10, ne ; CHECK-NEXT: csel x2, x10, x8, lt
; CHECK-NEXT: asr x13, x12, #63 ; CHECK-NEXT: csel x3, x14, x12, lt
; CHECK-NEXT: tst w9, w10 ; CHECK-NEXT: subs x8, x0, x4
; CHECK-NEXT: csel x2, x13, x11, ne ; CHECK-NEXT: sbcs x10, x1, x5
; CHECK-NEXT: csel x3, x14, x12, ne ; CHECK-NEXT: eor x11, x1, x5
; CHECK-NEXT: cmp x5, #0 // =0 ; CHECK-NEXT: cmp x10, #0 // =0
; CHECK-NEXT: cset w9, lt ; CHECK-NEXT: eor x12, x1, x10
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cinv x9, x9, ge
; CHECK-NEXT: cset w10, lt ; CHECK-NEXT: tst x11, x12
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: cset w9, ne ; CHECK-NEXT: csel x8, x11, x8, lt
; CHECK-NEXT: subs x11, x0, x4 ; CHECK-NEXT: csel x1, x9, x10, lt
; CHECK-NEXT: sbcs x12, x1, x5 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, lt
; CHECK-NEXT: cinv x8, x8, ge
; CHECK-NEXT: cmp w10, w13
; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: asr x9, x12, #63
; CHECK-NEXT: csel x9, x9, x11, ne
; CHECK-NEXT: csel x1, x8, x12, ne
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/ARM/sadd_sat.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; CHECK-ARMDSP-NEXT: bx lr ; CHECK-ARMDSP-NEXT: bx lr
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y) %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-LABEL: func2: ; CHECK-T1-LABEL: func2:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: mov r4, r1
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: eors r4, r3
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill ; CHECK-T1-NEXT: adds r0, r0, r2
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: adcs r3, r1
; CHECK-T1-NEXT: movs r4, #1 ; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: bics r1, r4
; CHECK-T1-NEXT: cmp r3, #0 ; CHECK-T1-NEXT: bpl .LBB1_2
; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r5, r0 ; CHECK-T1-NEXT: asrs r0, r3, #31
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r7, r4
; CHECK-T1-NEXT: bmi .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r7, r0 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bpl .LBB1_5
; CHECK-T1-NEXT: b .LBB1_6
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r6, r7, r5 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: rsbs r5, r6, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: adcs r5, r6
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: adds r6, r2, r6
; CHECK-T1-NEXT: adcs r1, r3
; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: bmi .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: .LBB1_5:
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r3
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r0, r7, r2
; CHECK-T1-NEXT: subs r2, r0, #1
; CHECK-T1-NEXT: sbcs r0, r2
; CHECK-T1-NEXT: ands r5, r0
; CHECK-T1-NEXT: beq .LBB1_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: asrs r6, r1, #31
; CHECK-T1-NEXT: .LBB1_8:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: lsls r2, r4, #31
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: beq .LBB1_11
; CHECK-T1-NEXT: b .LBB1_12
; CHECK-T1-NEXT: .LBB1_10:
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: bne .LBB1_12
; CHECK-T1-NEXT: .LBB1_11:
; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: .LBB1_12:
; CHECK-T1-NEXT: mov r0, r6
; CHECK-T1-NEXT: mov r1, r2 ; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: add sp, #4 ; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .p2align 2 ; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func2: ; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r7, lr}
; CHECK-T2-NEXT: push {r7, lr}
; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: adds r0, r0, r2 ; CHECK-T2-NEXT: adds r0, r0, r2
; CHECK-T2-NEXT: adcs.w r2, r1, r3 ; CHECK-T2-NEXT: eor.w r12, r1, r3
; CHECK-T2-NEXT: mov.w r1, #0 ; CHECK-T2-NEXT: adc.w r2, r1, r3
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: movmi r1, #1 ; CHECK-T2-NEXT: bic.w r3, r1, r12
; CHECK-T2-NEXT: mov.w r12, #0 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: subs.w r1, lr, r1
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi.w r12, #1 ; CHECK-T2-NEXT: asrmi r0, r2, #31
; CHECK-T2-NEXT: sub.w r3, lr, r12
; CHECK-T2-NEXT: clz r3, r3
; CHECK-T2-NEXT: lsrs r3, r3, #5
; CHECK-T2-NEXT: ands r3, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it pl
; CHECK-T2-NEXT: moveq r1, r2 ; CHECK-T2-NEXT: movpl r1, r2
; CHECK-T2-NEXT: pop {r7, pc} ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func2: ; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r11, lr}
; CHECK-ARM-NEXT: push {r11, lr}
; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov lr, #0
; CHECK-ARM-NEXT: movmi lr, #1
; CHECK-ARM-NEXT: adds r0, r0, r2 ; CHECK-ARM-NEXT: adds r0, r0, r2
; CHECK-ARM-NEXT: adcs r2, r1, r3 ; CHECK-ARM-NEXT: eor r12, r1, r3
; CHECK-ARM-NEXT: mov r1, #0 ; CHECK-ARM-NEXT: adc r2, r1, r3
; CHECK-ARM-NEXT: movmi r1, #1 ; CHECK-ARM-NEXT: eor r1, r1, r2
; CHECK-ARM-NEXT: mov r12, #0 ; CHECK-ARM-NEXT: bic r3, r1, r12
; CHECK-ARM-NEXT: subs r1, lr, r1
; CHECK-ARM-NEXT: movne r1, #1
; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: movmi r12, #1
; CHECK-ARM-NEXT: sub r3, lr, r12
; CHECK-ARM-NEXT: clz r3, r3
; CHECK-ARM-NEXT: lsr r3, r3, #5
; CHECK-ARM-NEXT: ands r3, r3, r1
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: asrne r0, r2, #31 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: asrmi r0, r2, #31
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: moveq r1, r2 ; CHECK-ARM-NEXT: movpl r1, r2
; CHECK-ARM-NEXT: pop {r11, pc} ; CHECK-ARM-NEXT: bx lr
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y) %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
ret i64 %tmp ret i64 %tmp
} }
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind { define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: adds r0, r0, r1 ; CHECK-T1-NEXT: adds r0, r0, r1
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/sadd_sat_plus.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines; CHECK-ARM-NEXT: bx lr
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-LABEL: func64: ; CHECK-T1-LABEL: func64:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: ldr r3, [sp, #12]
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: ldr r5, [sp, #28] ; CHECK-T1-NEXT: eors r2, r3
; CHECK-T1-NEXT: movs r2, #1 ; CHECK-T1-NEXT: ldr r4, [sp, #8]
; CHECK-T1-NEXT: movs r4, #0 ; CHECK-T1-NEXT: adds r0, r0, r4
; CHECK-T1-NEXT: cmp r5, #0 ; CHECK-T1-NEXT: adcs r3, r1
; CHECK-T1-NEXT: mov r3, r2 ; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: bmi .LBB1_2 ; CHECK-T1-NEXT: bics r1, r2
; CHECK-T1-NEXT: bpl .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r3, r4 ; CHECK-T1-NEXT: asrs r0, r3, #31
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r6, r2
; CHECK-T1-NEXT: bmi .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r6, r4 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bpl .LBB1_5
; CHECK-T1-NEXT: b .LBB1_6
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r7, r6, r3 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: rsbs r3, r7, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: adcs r3, r7
; CHECK-T1-NEXT: ldr r7, [sp, #24]
; CHECK-T1-NEXT: adds r0, r0, r7
; CHECK-T1-NEXT: adcs r1, r5
; CHECK-T1-NEXT: mov r5, r2
; CHECK-T1-NEXT: bmi .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: .LBB1_5:
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r2, r3
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r4, r6, r5
; CHECK-T1-NEXT: subs r5, r4, #1
; CHECK-T1-NEXT: sbcs r4, r5
; CHECK-T1-NEXT: ands r3, r4
; CHECK-T1-NEXT: beq .LBB1_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: asrs r0, r1, #31
; CHECK-T1-NEXT: .LBB1_8:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: beq .LBB1_11
; CHECK-T1-NEXT: b .LBB1_12
; CHECK-T1-NEXT: .LBB1_10:
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: bne .LBB1_12
; CHECK-T1-NEXT: .LBB1_11:
; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: .LBB1_12:
; CHECK-T1-NEXT: mov r1, r2 ; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: add sp, #4 ; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .p2align 2 ; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func64: ; CHECK-T2-LABEL: func64:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r7, lr} ; CHECK-T2-NEXT: ldr r2, [sp]
; CHECK-T2-NEXT: push {r7, lr} ; CHECK-T2-NEXT: ldr.w r12, [sp, #4]
; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8]
; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w r3, #0
; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r3, #1
; CHECK-T2-NEXT: adds r0, r0, r2 ; CHECK-T2-NEXT: adds r0, r0, r2
; CHECK-T2-NEXT: adcs.w r2, r1, r12 ; CHECK-T2-NEXT: adc.w r2, r1, r12
; CHECK-T2-NEXT: mov.w r1, #0 ; CHECK-T2-NEXT: eor.w r3, r1, r12
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: movmi r1, #1 ; CHECK-T2-NEXT: bic.w r3, r1, r3
; CHECK-T2-NEXT: subs r1, r3, r1
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: cmp.w r12, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: sub.w r3, r3, lr
; CHECK-T2-NEXT: clz r3, r3
; CHECK-T2-NEXT: lsrs r3, r3, #5
; CHECK-T2-NEXT: ands r3, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: asrne r0, r2, #31 ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: asrmi r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it pl
; CHECK-T2-NEXT: moveq r1, r2 ; CHECK-T2-NEXT: movpl r1, r2
; CHECK-T2-NEXT: pop {r7, pc} ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func64: ; CHECK-ARM-LABEL: func64:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r11, lr} ; CHECK-ARM-NEXT: ldr r12, [sp]
; CHECK-ARM-NEXT: push {r11, lr} ; CHECK-ARM-NEXT: ldr r2, [sp, #4]
; CHECK-ARM-NEXT: ldr r2, [sp, #8] ; CHECK-ARM-NEXT: adds r0, r0, r12
; CHECK-ARM-NEXT: mov r3, #0 ; CHECK-ARM-NEXT: eor r3, r1, r2
; CHECK-ARM-NEXT: ldr r12, [sp, #12] ; CHECK-ARM-NEXT: adc r2, r1, r2
; CHECK-ARM-NEXT: adds r0, r0, r2 ; CHECK-ARM-NEXT: eor r1, r1, r2
; CHECK-ARM-NEXT: mov r2, #0 ; CHECK-ARM-NEXT: bic r3, r1, r3
; CHECK-ARM-NEXT: adc lr, r1, r12
; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r1, #0
; CHECK-ARM-NEXT: movwmi r1, #1
; CHECK-ARM-NEXT: cmp lr, #0
; CHECK-ARM-NEXT: movwmi r2, #1
; CHECK-ARM-NEXT: subs r2, r1, r2
; CHECK-ARM-NEXT: movwne r2, #1
; CHECK-ARM-NEXT: cmp r12, #0
; CHECK-ARM-NEXT: movwmi r3, #1
; CHECK-ARM-NEXT: sub r1, r1, r3
; CHECK-ARM-NEXT: clz r1, r1
; CHECK-ARM-NEXT: lsr r1, r1, #5
; CHECK-ARM-NEXT: ands r2, r1, r2
; CHECK-ARM-NEXT: asrne r0, lr, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp lr, #0 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: asrmi r0, r2, #31
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: moveq r1, lr ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: pop {r11, pc} ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: movpl r1, r2
; CHECK-ARM-NEXT: bx lr
%a = mul i64 %y, %z %a = mul i64 %y, %z
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z) %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
ret i64 %tmp ret i64 %tmp
} }
define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind { define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ssub_sat.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; CHECK-ARMDSP-NEXT: bx lr ; CHECK-ARMDSP-NEXT: bx lr
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y) %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-LABEL: func2: ; CHECK-T1-LABEL: func2:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, r5, r7, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: mov r5, r1
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: eors r5, r3
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill ; CHECK-T1-NEXT: subs r0, r0, r2
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r4, r1
; CHECK-T1-NEXT: movs r4, #1 ; CHECK-T1-NEXT: sbcs r4, r3
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: eors r1, r4
; CHECK-T1-NEXT: cmp r3, #0 ; CHECK-T1-NEXT: ands r1, r5
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: bpl .LBB1_2
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r5, r0 ; CHECK-T1-NEXT: asrs r0, r4, #31
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: mov r7, r4
; CHECK-T1-NEXT: bmi .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r7, r0 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bpl .LBB1_5
; CHECK-T1-NEXT: b .LBB1_6
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r5, r7, r5 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: subs r6, r5, #1 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: sbcs r5, r6
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: subs r6, r2, r6
; CHECK-T1-NEXT: sbcs r1, r3
; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: bmi .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: .LBB1_5:
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r0, r7, r2
; CHECK-T1-NEXT: subs r2, r0, #1
; CHECK-T1-NEXT: sbcs r0, r2
; CHECK-T1-NEXT: ands r5, r0
; CHECK-T1-NEXT: beq .LBB1_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: asrs r6, r1, #31
; CHECK-T1-NEXT: .LBB1_8:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: lsls r2, r4, #31
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: beq .LBB1_11
; CHECK-T1-NEXT: b .LBB1_12
; CHECK-T1-NEXT: .LBB1_10:
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: bne .LBB1_12
; CHECK-T1-NEXT: .LBB1_11:
; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: .LBB1_12:
; CHECK-T1-NEXT: mov r0, r6
; CHECK-T1-NEXT: mov r1, r2 ; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: add sp, #4 ; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .p2align 2 ; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func2: ; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr}
; CHECK-T2-NEXT: push {r4, lr}
; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w r4, #0
; CHECK-T2-NEXT: mov.w r12, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r4, #1
; CHECK-T2-NEXT: subs.w lr, r4, lr
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne.w lr, #1
; CHECK-T2-NEXT: subs r0, r0, r2 ; CHECK-T2-NEXT: subs r0, r0, r2
; CHECK-T2-NEXT: sbcs.w r2, r1, r3 ; CHECK-T2-NEXT: eor.w r12, r1, r3
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: sbc.w r2, r1, r3
; CHECK-T2-NEXT: movmi.w r12, #1 ; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: subs.w r1, r4, r12 ; CHECK-T2-NEXT: ands.w r3, r12, r1
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: ands.w r3, lr, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: asrne r0, r2, #31 ; CHECK-T2-NEXT: asrmi r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it pl
; CHECK-T2-NEXT: moveq r1, r2 ; CHECK-T2-NEXT: movpl r1, r2
; CHECK-T2-NEXT: pop {r4, pc} ; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func2: ; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, lr}
; CHECK-ARM-NEXT: push {r4, lr}
; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: mov lr, #0
; CHECK-ARM-NEXT: movmi lr, #1
; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: mov r12, #0
; CHECK-ARM-NEXT: movmi r4, #1
; CHECK-ARM-NEXT: subs lr, r4, lr
; CHECK-ARM-NEXT: movne lr, #1
; CHECK-ARM-NEXT: subs r0, r0, r2 ; CHECK-ARM-NEXT: subs r0, r0, r2
; CHECK-ARM-NEXT: sbcs r2, r1, r3 ; CHECK-ARM-NEXT: eor r12, r1, r3
; CHECK-ARM-NEXT: movmi r12, #1 ; CHECK-ARM-NEXT: sbc r2, r1, r3
; CHECK-ARM-NEXT: subs r1, r4, r12 ; CHECK-ARM-NEXT: eor r1, r1, r2
; CHECK-ARM-NEXT: movne r1, #1 ; CHECK-ARM-NEXT: ands r3, r12, r1
; CHECK-ARM-NEXT: ands r3, lr, r1
; CHECK-ARM-NEXT: asrne r0, r2, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: asrmi r0, r2, #31
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: moveq r1, r2 ; CHECK-ARM-NEXT: movpl r1, r2
; CHECK-ARM-NEXT: pop {r4, pc} ; CHECK-ARM-NEXT: bx lr
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y) %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
ret i64 %tmp ret i64 %tmp
} }
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind { define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1 ; CHECK-T1-NEXT: subs r0, r0, r1
▲ Show 20 Lines • Show All 446 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ssub_sat_plus.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines; CHECK-ARM-NEXT: bx lr
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-LABEL: func64: ; CHECK-T1-LABEL: func64:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: ldr r2, [sp, #12]
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: mov r4, r1
; CHECK-T1-NEXT: ldr r5, [sp, #28] ; CHECK-T1-NEXT: eors r4, r2
; CHECK-T1-NEXT: movs r2, #1 ; CHECK-T1-NEXT: ldr r3, [sp, #8]
; CHECK-T1-NEXT: movs r4, #0 ; CHECK-T1-NEXT: subs r0, r0, r3
; CHECK-T1-NEXT: cmp r5, #0 ; CHECK-T1-NEXT: mov r3, r1
; CHECK-T1-NEXT: mov r3, r2 ; CHECK-T1-NEXT: sbcs r3, r2
; CHECK-T1-NEXT: bmi .LBB1_2 ; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: ands r1, r4
; CHECK-T1-NEXT: bpl .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r3, r4 ; CHECK-T1-NEXT: asrs r0, r3, #31
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r6, r2
; CHECK-T1-NEXT: bmi .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r6, r4 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bpl .LBB1_5
; CHECK-T1-NEXT: b .LBB1_6
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r3, r6, r3 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: subs r7, r3, #1 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: sbcs r3, r7
; CHECK-T1-NEXT: ldr r7, [sp, #24]
; CHECK-T1-NEXT: subs r0, r0, r7
; CHECK-T1-NEXT: sbcs r1, r5
; CHECK-T1-NEXT: mov r5, r2
; CHECK-T1-NEXT: bmi .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: .LBB1_5:
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r2, r3
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r4, r6, r5
; CHECK-T1-NEXT: subs r5, r4, #1
; CHECK-T1-NEXT: sbcs r4, r5
; CHECK-T1-NEXT: ands r3, r4
; CHECK-T1-NEXT: beq .LBB1_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: asrs r0, r1, #31
; CHECK-T1-NEXT: .LBB1_8:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: beq .LBB1_11
; CHECK-T1-NEXT: b .LBB1_12
; CHECK-T1-NEXT: .LBB1_10:
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: bne .LBB1_12
; CHECK-T1-NEXT: .LBB1_11:
; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: .LBB1_12:
; CHECK-T1-NEXT: mov r1, r2 ; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: add sp, #4 ; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .p2align 2 ; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func64: ; CHECK-T2-LABEL: func64:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr} ; CHECK-T2-NEXT: ldr r2, [sp]
; CHECK-T2-NEXT: push {r4, lr} ; CHECK-T2-NEXT: ldr.w r12, [sp, #4]
; CHECK-T2-NEXT: ldr.w r12, [sp, #12] ; CHECK-T2-NEXT: subs r0, r0, r2
; CHECK-T2-NEXT: movs r2, #0 ; CHECK-T2-NEXT: sbc.w r2, r1, r12
; CHECK-T2-NEXT: movs r3, #0 ; CHECK-T2-NEXT: eor.w r3, r1, r12
; CHECK-T2-NEXT: ldr r4, [sp, #8] ; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: cmp.w r12, #0 ; CHECK-T2-NEXT: ands r3, r1
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r2, #1
; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r3, #1
; CHECK-T2-NEXT: subs r2, r3, r2
; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r2, #1
; CHECK-T2-NEXT: subs r0, r0, r4
; CHECK-T2-NEXT: sbcs.w r4, r1, r12
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: subs.w r1, r3, lr
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: ands r2, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r4, #31
; CHECK-T2-NEXT: cmp r4, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: asrmi r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: moveq r1, r4 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: pop {r4, pc} ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it pl
; CHECK-T2-NEXT: movpl r1, r2
; CHECK-T2-NEXT: bx lr
; ;
; CHECK-ARM-LABEL: func64: ; CHECK-ARM-LABEL: func64:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, lr} ; CHECK-ARM-NEXT: ldr r12, [sp]
; CHECK-ARM-NEXT: push {r4, lr} ; CHECK-ARM-NEXT: ldr r2, [sp, #4]
; CHECK-ARM-NEXT: ldr lr, [sp, #12]
; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r3, #0
; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: movwmi r3, #1
; CHECK-ARM-NEXT: cmp lr, #0
; CHECK-ARM-NEXT: movwmi r4, #1
; CHECK-ARM-NEXT: ldr r12, [sp, #8]
; CHECK-ARM-NEXT: subs r4, r3, r4
; CHECK-ARM-NEXT: mov r2, #0
; CHECK-ARM-NEXT: movwne r4, #1
; CHECK-ARM-NEXT: subs r0, r0, r12 ; CHECK-ARM-NEXT: subs r0, r0, r12
; CHECK-ARM-NEXT: sbcs r12, r1, lr ; CHECK-ARM-NEXT: eor r3, r1, r2
; CHECK-ARM-NEXT: movwmi r2, #1 ; CHECK-ARM-NEXT: sbc r2, r1, r2
; CHECK-ARM-NEXT: subs r1, r3, r2 ; CHECK-ARM-NEXT: eor r1, r1, r2
; CHECK-ARM-NEXT: movwne r1, #1 ; CHECK-ARM-NEXT: ands r3, r3, r1
; CHECK-ARM-NEXT: ands r2, r4, r1
; CHECK-ARM-NEXT: asrne r0, r12, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp r12, #0 ; CHECK-ARM-NEXT: asrmi r0, r2, #31
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: moveq r1, r12 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: pop {r4, pc} ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: movpl r1, r2
; CHECK-ARM-NEXT: bx lr
%a = mul i64 %y, %z %a = mul i64 %y, %z
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z) %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
ret i64 %tmp ret i64 %tmp
} }
define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind { define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/sadd_sat.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: sltu a1, a0, a1 ; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: add a2, a5, a1 ; RV32I-NEXT: add a2, a5, a1
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez a2, .LBB1_2 ; RV32I-NEXT: bgez a2, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: slti a5, a2, 0 ; RV32I-NEXT: xor a5, a4, a2
; RV32I-NEXT: slti a4, a4, 0
; RV32I-NEXT: xor a5, a4, a5
; RV32I-NEXT: snez a5, a5
; RV32I-NEXT: slti a3, a3, 0
; RV32I-NEXT: xor a3, a4, a3 ; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: seqz a3, a3 ; RV32I-NEXT: not a3, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: bnez a3, .LBB1_4 ; RV32I-NEXT: bltz a3, .LBB1_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, a2, 31 ; RV32I-NEXT: srai a0, a2, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func2: ; RV64I-LABEL: func2:
Show All 23 Lines
; RV32IZbb-NEXT: add a0, a0, a2 ; RV32IZbb-NEXT: add a0, a0, a2
; RV32IZbb-NEXT: sltu a1, a0, a1 ; RV32IZbb-NEXT: sltu a1, a0, a1
; RV32IZbb-NEXT: add a2, a5, a1 ; RV32IZbb-NEXT: add a2, a5, a1
; RV32IZbb-NEXT: lui a1, 524288 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez a2, .LBB1_2 ; RV32IZbb-NEXT: bgez a2, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: addi a1, a1, -1 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: slti a5, a2, 0 ; RV32IZbb-NEXT: xor a5, a4, a2
; RV32IZbb-NEXT: slti a4, a4, 0
; RV32IZbb-NEXT: xor a5, a4, a5
; RV32IZbb-NEXT: snez a5, a5
; RV32IZbb-NEXT: slti a3, a3, 0
; RV32IZbb-NEXT: xor a3, a4, a3 ; RV32IZbb-NEXT: xor a3, a4, a3
; RV32IZbb-NEXT: seqz a3, a3 ; RV32IZbb-NEXT: andn a3, a5, a3
; RV32IZbb-NEXT: and a3, a3, a5 ; RV32IZbb-NEXT: bltz a3, .LBB1_4
; RV32IZbb-NEXT: bnez a3, .LBB1_4
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: mv a1, a2 ; RV32IZbb-NEXT: mv a1, a2
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, a2, 31 ; RV32IZbb-NEXT: srai a0, a2, 31
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func2: ; RV64IZbb-LABEL: func2:
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: add a0, a0, a4
; RV32I-NEXT: sltu a1, a0, a1 ; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: add a3, a3, a1 ; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez a3, .LBB1_2 ; RV32I-NEXT: bgez a3, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: slti a4, a3, 0 ; RV32I-NEXT: xor a4, a2, a3
; RV32I-NEXT: slti a2, a2, 0
; RV32I-NEXT: xor a4, a2, a4
; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: slti a5, a5, 0
; RV32I-NEXT: xor a2, a2, a5 ; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: seqz a2, a2 ; RV32I-NEXT: not a2, a2
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: bnez a2, .LBB1_4 ; RV32I-NEXT: bltz a2, .LBB1_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, a3, 31 ; RV32I-NEXT: srai a0, a3, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func64: ; RV64I-LABEL: func64:
Show All 23 Lines
; RV32IZbb-NEXT: add a0, a0, a4 ; RV32IZbb-NEXT: add a0, a0, a4
; RV32IZbb-NEXT: sltu a1, a0, a1 ; RV32IZbb-NEXT: sltu a1, a0, a1
; RV32IZbb-NEXT: add a3, a3, a1 ; RV32IZbb-NEXT: add a3, a3, a1
; RV32IZbb-NEXT: lui a1, 524288 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez a3, .LBB1_2 ; RV32IZbb-NEXT: bgez a3, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: addi a1, a1, -1 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: slti a4, a3, 0 ; RV32IZbb-NEXT: xor a4, a2, a3
; RV32IZbb-NEXT: slti a2, a2, 0
; RV32IZbb-NEXT: xor a4, a2, a4
; RV32IZbb-NEXT: snez a4, a4
; RV32IZbb-NEXT: slti a5, a5, 0
; RV32IZbb-NEXT: xor a2, a2, a5 ; RV32IZbb-NEXT: xor a2, a2, a5
; RV32IZbb-NEXT: seqz a2, a2 ; RV32IZbb-NEXT: andn a2, a4, a2
; RV32IZbb-NEXT: and a2, a2, a4 ; RV32IZbb-NEXT: bltz a2, .LBB1_4
; RV32IZbb-NEXT: bnez a2, .LBB1_4
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: mv a1, a3 ; RV32IZbb-NEXT: mv a1, a3
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, a3, 31 ; RV32IZbb-NEXT: srai a0, a3, 31
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func64: ; RV64IZbb-LABEL: func64:
▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y); %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
ret i32 %tmp; ret i32 %tmp;
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: func2: ; RV32I-LABEL: func2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a6, a1 ; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: sltu a1, a0, a2 ; RV32I-NEXT: sltu a1, a0, a2
; RV32I-NEXT: sub a5, a6, a3 ; RV32I-NEXT: sub a5, a4, a3
; RV32I-NEXT: sub t0, a5, a1 ; RV32I-NEXT: sub a5, a5, a1
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez t0, .LBB1_2 ; RV32I-NEXT: bgez a5, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: slti a7, t0, 0 ; RV32I-NEXT: xor a6, a4, a5
; RV32I-NEXT: slti a4, a6, 0
; RV32I-NEXT: xor a5, a4, a7
; RV32I-NEXT: snez a5, a5
; RV32I-NEXT: slti a3, a3, 0
; RV32I-NEXT: xor a3, a4, a3 ; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: snez a3, a3 ; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: bltz a3, .LBB1_4
; RV32I-NEXT: bnez a3, .LBB1_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: mv a1, t0 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, t0, 31 ; RV32I-NEXT: srai a0, a5, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func2: ; RV64I-LABEL: func2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sgtz a2, a1 ; RV64I-NEXT: sgtz a2, a1
; RV64I-NEXT: sub a1, a0, a1 ; RV64I-NEXT: sub a1, a0, a1
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: xor a2, a2, a0 ; RV64I-NEXT: xor a2, a2, a0
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bltz a1, .LBB1_3 ; RV64I-NEXT: bltz a1, .LBB1_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: beqz a2, .LBB1_4 ; RV64I-NEXT: beqz a2, .LBB1_4
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB1_3: ; RV64I-NEXT: .LBB1_3:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a2, .LBB1_2 ; RV64I-NEXT: bnez a2, .LBB1_2
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func2: ; RV32IZbb-LABEL: func2:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: mv a6, a1 ; RV32IZbb-NEXT: mv a4, a1
; RV32IZbb-NEXT: sltu a1, a0, a2 ; RV32IZbb-NEXT: sltu a1, a0, a2
; RV32IZbb-NEXT: sub a5, a6, a3 ; RV32IZbb-NEXT: sub a5, a4, a3
; RV32IZbb-NEXT: sub t0, a5, a1 ; RV32IZbb-NEXT: sub a5, a5, a1
; RV32IZbb-NEXT: lui a1, 524288 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez t0, .LBB1_2 ; RV32IZbb-NEXT: bgez a5, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: addi a1, a1, -1 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: slti a7, t0, 0 ; RV32IZbb-NEXT: xor a6, a4, a5
; RV32IZbb-NEXT: slti a4, a6, 0
; RV32IZbb-NEXT: xor a5, a4, a7
; RV32IZbb-NEXT: snez a5, a5
; RV32IZbb-NEXT: slti a3, a3, 0
; RV32IZbb-NEXT: xor a3, a4, a3 ; RV32IZbb-NEXT: xor a3, a4, a3
; RV32IZbb-NEXT: snez a3, a3 ; RV32IZbb-NEXT: and a3, a3, a6
; RV32IZbb-NEXT: and a3, a3, a5 ; RV32IZbb-NEXT: bltz a3, .LBB1_4
; RV32IZbb-NEXT: bnez a3, .LBB1_4
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: sub a0, a0, a2 ; RV32IZbb-NEXT: sub a0, a0, a2
; RV32IZbb-NEXT: mv a1, t0 ; RV32IZbb-NEXT: mv a1, a5
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, t0, 31 ; RV32IZbb-NEXT: srai a0, a5, 31
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func2: ; RV64IZbb-LABEL: func2:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sgtz a2, a1 ; RV64IZbb-NEXT: sgtz a2, a1
; RV64IZbb-NEXT: sub a1, a0, a1 ; RV64IZbb-NEXT: sub a1, a0, a1
; RV64IZbb-NEXT: slt a0, a1, a0 ; RV64IZbb-NEXT: slt a0, a1, a0
; RV64IZbb-NEXT: xor a2, a2, a0 ; RV64IZbb-NEXT: xor a2, a2, a0
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64IZbb-NEXT: ret
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32I-LABEL: func64: ; RV32I-LABEL: func64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a6, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: sltu a1, a0, a4 ; RV32I-NEXT: sltu a1, a0, a4
; RV32I-NEXT: sub a3, a6, a5 ; RV32I-NEXT: sub a3, a2, a5
; RV32I-NEXT: sub t0, a3, a1 ; RV32I-NEXT: sub a3, a3, a1
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez t0, .LBB1_2 ; RV32I-NEXT: bgez a3, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: slti a7, t0, 0 ; RV32I-NEXT: xor a6, a2, a3
; RV32I-NEXT: slti a2, a6, 0
; RV32I-NEXT: xor a3, a2, a7
; RV32I-NEXT: snez a3, a3
; RV32I-NEXT: slti a5, a5, 0
; RV32I-NEXT: xor a2, a2, a5 ; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: snez a2, a2 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: bltz a2, .LBB1_4
; RV32I-NEXT: bnez a2, .LBB1_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sub a0, a0, a4 ; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: mv a1, t0 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, t0, 31 ; RV32I-NEXT: srai a0, a3, 31
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func64: ; RV64I-LABEL: func64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sgtz a3, a2 ; RV64I-NEXT: sgtz a3, a2
; RV64I-NEXT: sub a1, a0, a2 ; RV64I-NEXT: sub a1, a0, a2
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: xor a2, a3, a0 ; RV64I-NEXT: xor a2, a3, a0
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bltz a1, .LBB1_3 ; RV64I-NEXT: bltz a1, .LBB1_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: beqz a2, .LBB1_4 ; RV64I-NEXT: beqz a2, .LBB1_4
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB1_3: ; RV64I-NEXT: .LBB1_3:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a2, .LBB1_2 ; RV64I-NEXT: bnez a2, .LBB1_2
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func64: ; RV32IZbb-LABEL: func64:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: mv a6, a1 ; RV32IZbb-NEXT: mv a2, a1
; RV32IZbb-NEXT: sltu a1, a0, a4 ; RV32IZbb-NEXT: sltu a1, a0, a4
; RV32IZbb-NEXT: sub a3, a6, a5 ; RV32IZbb-NEXT: sub a3, a2, a5
; RV32IZbb-NEXT: sub t0, a3, a1 ; RV32IZbb-NEXT: sub a3, a3, a1
; RV32IZbb-NEXT: lui a1, 524288 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez t0, .LBB1_2 ; RV32IZbb-NEXT: bgez a3, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: addi a1, a1, -1 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: slti a7, t0, 0 ; RV32IZbb-NEXT: xor a6, a2, a3
; RV32IZbb-NEXT: slti a2, a6, 0
; RV32IZbb-NEXT: xor a3, a2, a7
; RV32IZbb-NEXT: snez a3, a3
; RV32IZbb-NEXT: slti a5, a5, 0
; RV32IZbb-NEXT: xor a2, a2, a5 ; RV32IZbb-NEXT: xor a2, a2, a5
; RV32IZbb-NEXT: snez a2, a2 ; RV32IZbb-NEXT: and a2, a2, a6
; RV32IZbb-NEXT: and a2, a2, a3 ; RV32IZbb-NEXT: bltz a2, .LBB1_4
; RV32IZbb-NEXT: bnez a2, .LBB1_4
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: sub a0, a0, a4 ; RV32IZbb-NEXT: sub a0, a0, a4
; RV32IZbb-NEXT: mv a1, t0 ; RV32IZbb-NEXT: mv a1, a3
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, t0, 31 ; RV32IZbb-NEXT: srai a0, a3, 31
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func64: ; RV64IZbb-LABEL: func64:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sgtz a3, a2 ; RV64IZbb-NEXT: sgtz a3, a2
; RV64IZbb-NEXT: sub a1, a0, a2 ; RV64IZbb-NEXT: sub a1, a0, a2
; RV64IZbb-NEXT: slt a0, a1, a0 ; RV64IZbb-NEXT: slt a0, a1, a0
; RV64IZbb-NEXT: xor a2, a3, a0 ; RV64IZbb-NEXT: xor a2, a3, a0
▲ Show 20 Lines • Show All 250 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/xaluo.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: saddo1.i64: ; RV32-LABEL: saddo1.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a5, a1, a3 ; RV32-NEXT: add a5, a1, a3
; RV32-NEXT: add a2, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a5, a5, a0 ; RV32-NEXT: add a5, a5, a0
; RV32-NEXT: slti a0, a5, 0 ; RV32-NEXT: xor a0, a1, a5
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0
; RV32-NEXT: slti a3, a3, 0
; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: not a1, a1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: sw a2, 0(a4) ; RV32-NEXT: sw a2, 0(a4)
; RV32-NEXT: sw a5, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo1.i64: ; RV64-LABEL: saddo1.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a3, a0, a1 ; RV64-NEXT: add a3, a0, a1
; RV64-NEXT: slt a0, a3, a0 ; RV64-NEXT: slt a0, a3, a0
; RV64-NEXT: slti a1, a1, 0 ; RV64-NEXT: slti a1, a1, 0
; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: xor a0, a1, a0
; RV64-NEXT: sd a3, 0(a2) ; RV64-NEXT: sd a3, 0(a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64* %res store i64 %val, i64* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) { define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
; RV32-LABEL: saddo2.i64: ; RV32-LABEL: saddo2.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, zero, -1 ; RV32-NEXT: addi a3, a0, 4
; RV32-NEXT: slt a3, a3, a1 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: addi a4, a0, 4 ; RV32-NEXT: add a4, a1, a0
; RV32-NEXT: sltu a0, a4, a0 ; RV32-NEXT: xor a0, a1, a4
; RV32-NEXT: add a5, a1, a0 ; RV32-NEXT: not a1, a1
; RV32-NEXT: slti a0, a5, 0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: slti a1, a1, 0 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: and a0, a3, a0
; RV32-NEXT: sw a4, 0(a2)
; RV32-NEXT: sw a5, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo2.i64: ; RV64-LABEL: saddo2.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, 4 ; RV64-NEXT: addi a2, a0, 4
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4) %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64* %res store i64 %val, i64* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) { define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
; RV32-LABEL: saddo3.i64: ; RV32-LABEL: saddo3.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, -4 ; RV32-NEXT: addi a3, a0, -4
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: addi a4, a0, -1 ; RV32-NEXT: addi a4, a0, -1
; RV32-NEXT: slti a0, a4, 0 ; RV32-NEXT: xor a0, a1, a4
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo3.i64: ; RV64-LABEL: saddo3.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, -4 ; RV64-NEXT: addi a2, a0, -4
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Linesentry:
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: ssubo.i64: ; RV32-LABEL: ssubo.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a6, a0, a2 ; RV32-NEXT: sltu a6, a0, a2
; RV32-NEXT: sub a5, a1, a3 ; RV32-NEXT: sub a5, a1, a3
; RV32-NEXT: sub a7, a5, a6 ; RV32-NEXT: sub a5, a5, a6
; RV32-NEXT: slti a6, a7, 0 ; RV32-NEXT: xor a6, a1, a5
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a5, a1, a6
; RV32-NEXT: snez a5, a5
; RV32-NEXT: slti a3, a3, 0
; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: and a1, a1, a6
; RV32-NEXT: and a1, a1, a5 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: sub a0, a0, a2 ; RV32-NEXT: sub a0, a0, a2
; RV32-NEXT: sw a0, 0(a4) ; RV32-NEXT: sw a0, 0(a4)
; RV32-NEXT: sw a7, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.i64: ; RV64-LABEL: ssubo.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a3, a1 ; RV64-NEXT: sgtz a3, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
▲ Show 20 Lines • Show All 419 Lines • ▼ Show 20 Lines
define i64 @saddo.select.i64(i64 %v1, i64 %v2) { define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.select.i64: ; RV32-LABEL: saddo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a5, a0, a2 ; RV32-NEXT: add a5, a0, a2
; RV32-NEXT: sltu a5, a5, a0 ; RV32-NEXT: sltu a5, a5, a0
; RV32-NEXT: add a4, a4, a5 ; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: slti a4, a4, 0 ; RV32-NEXT: xor a4, a1, a4
; RV32-NEXT: slti a5, a1, 0 ; RV32-NEXT: xor a5, a1, a3
; RV32-NEXT: xor a4, a5, a4 ; RV32-NEXT: not a5, a5
; RV32-NEXT: snez a6, a4 ; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: slti a4, a3, 0 ; RV32-NEXT: bltz a4, .LBB24_2
; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: seqz a4, a4
; RV32-NEXT: and a4, a4, a6
; RV32-NEXT: bnez a4, .LBB24_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB24_2: # %entry ; RV32-NEXT: .LBB24_2: # %entry
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.select.i64: ; RV64-LABEL: saddo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 15 Lines
define i1 @saddo.not.i64(i64 %v1, i64 %v2) { define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.not.i64: ; RV32-LABEL: saddo.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a2, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a0, a4, a0 ; RV32-NEXT: add a0, a4, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: slti a2, a3, 0 ; RV32-NEXT: not a1, a1
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: seqz a1, a1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: addi a1, zero, -1
; RV32-NEXT: slt a0, a1, a0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.not.i64: ; RV64-LABEL: saddo.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: slti a1, a1, 0 ; RV64-NEXT: slti a1, a1, 0
; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: xor a0, a1, a0
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
} }
define i64 @ssubo.select.i64(i64 %v1, i64 %v2) { define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssubo.select.i64: ; RV32-LABEL: ssubo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a4, a0, a2 ; RV32-NEXT: sltu a4, a0, a2
; RV32-NEXT: sub a5, a1, a3 ; RV32-NEXT: sub a5, a1, a3
; RV32-NEXT: sub a4, a5, a4 ; RV32-NEXT: sub a4, a5, a4
; RV32-NEXT: slti a4, a4, 0 ; RV32-NEXT: xor a4, a1, a4
; RV32-NEXT: slti a5, a1, 0 ; RV32-NEXT: xor a5, a1, a3
; RV32-NEXT: xor a4, a5, a4 ; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: snez a6, a4 ; RV32-NEXT: bltz a4, .LBB32_2
; RV32-NEXT: slti a4, a3, 0
; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: snez a4, a4
; RV32-NEXT: and a4, a4, a6
; RV32-NEXT: bnez a4, .LBB32_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB32_2: # %entry ; RV32-NEXT: .LBB32_2: # %entry
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.select.i64: ; RV64-LABEL: ssubo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 14 Lines
} }
define i1 @ssub.not.i64(i64 %v1, i64 %v2) { define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssub.not.i64: ; RV32-LABEL: ssub.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: sub a2, a1, a3 ; RV32-NEXT: sub a2, a1, a3
; RV32-NEXT: sub a0, a2, a0 ; RV32-NEXT: sub a0, a2, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: snez a1, a1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: addi a1, zero, -1
; RV32-NEXT: slt a0, a1, a0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub.not.i64: ; RV64-LABEL: ssub.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a2, a1 ; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
; RV64-NEXT: xor a0, a2, a0 ; RV64-NEXT: xor a0, a2, a0
▲ Show 20 Lines • Show All 471 Lines • ▼ Show 20 Lines
define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.br.i64: ; RV32-LABEL: saddo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a2, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a0, a4, a0 ; RV32-NEXT: add a0, a4, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: slti a2, a3, 0 ; RV32-NEXT: not a1, a1
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: seqz a1, a1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a0, .LBB47_2 ; RV32-NEXT: addi a1, zero, -1
; RV32-NEXT: blt a1, a0, .LBB47_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB47_2: # %continue ; RV32-NEXT: .LBB47_2: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.br.i64: ; RV64-LABEL: saddo.br.i64:
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
} }
define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssubo.br.i64: ; RV32-LABEL: ssubo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: sub a2, a1, a3 ; RV32-NEXT: sub a2, a1, a3
; RV32-NEXT: sub a0, a2, a0 ; RV32-NEXT: sub a0, a2, a0
; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: snez a1, a1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a0, .LBB51_2 ; RV32-NEXT: addi a1, zero, -1
; RV32-NEXT: blt a1, a0, .LBB51_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB51_2: # %continue ; RV32-NEXT: .LBB51_2: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.br.i64: ; RV64-LABEL: ssubo.br.i64:
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
define zeroext i1 @smulo2.br.i64(i64 %v1) { define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV32-LABEL: smulo2.br.i64: ; RV32-LABEL: smulo2.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a2, a0, a0 ; RV32-NEXT: add a2, a0, a0
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a2, a1, a1 ; RV32-NEXT: add a2, a1, a1
; RV32-NEXT: add a0, a2, a0 ; RV32-NEXT: add a0, a2, a0
; RV32-NEXT: slti a0, a0, 0 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: slti a1, a1, 0 ; RV32-NEXT: addi a1, zero, -1
; RV32-NEXT: beq a1, a0, .LBB56_2 ; RV32-NEXT: blt a1, a0, .LBB56_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB56_2: # %continue ; RV32-NEXT: .LBB56_2: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo2.br.i64: ; RV64-LABEL: smulo2.br.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a1, a0, a0 ; RV64-NEXT: add a1, a0, a0
; RV64-NEXT: slt a1, a1, a0 ; RV64-NEXT: slt a1, a1, a0
; RV64-NEXT: slti a0, a0, 0 ; RV64-NEXT: slti a0, a0, 0
; RV64-NEXT: xor a0, a0, a1 ; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: beqz a0, .LBB56_2 ; RV64-NEXT: beqz a0, .LBB56_2
; RV64-NEXT: # %bb.1: # %overflow ; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: mv a0, zero ; RV64-NEXT: mv a0, zero
; RV64-NEXT: ret ; RV64-NEXT: ret
; RV64-NEXT: .LBB56_2: # %continue ; RV64-NEXT: .LBB56_2: # %continue
; RV64-NEXT: addi a0, zero, 1 ; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2) %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2)
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

Well this isn't at all interesting for testing smulo. I'll put a different constant here.

craig.topper: Well this isn't at all interesting for testing smulo. I'll put a different constant here.
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
br i1 %obit, label %overflow, label %continue br i1 %obit, label %overflow, label %continue
overflow: overflow:
ret i1 false ret i1 false
continue: continue:
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll

Show All 28 Lines
entry: entry:
%0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2) %0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: sadd_int64_t: ; CHECK-LABEL: sadd_int64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov lr, s6 ; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r4, s1 ; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: vmov r6, s4 ; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: vmov r7, s0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r3, mi
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: cset r12, eq
; CHECK-NEXT: adds.w r1, r1, lr
; CHECK-NEXT: adcs.w lr, r2, r0
; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: cset r3, ne
; CHECK-NEXT: and.w r3, r3, r12
; CHECK-NEXT: ands r12, r3, #1
; CHECK-NEXT: vmov r3, s5 ; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: eor.w r12, r1, r0
; CHECK-NEXT: adcs r0, r1
; CHECK-NEXT: eors r1, r0
; CHECK-NEXT: bic.w r1, r1, r12
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r12, r1, #1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: asrne.w r1, lr, #31 ; CHECK-NEXT: asrne r2, r0, #31
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: adds r4, r4, r5
; CHECK-NEXT: cset r0, mi ; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: eor.w lr, r1, r3
; CHECK-NEXT: cset r5, mi ; CHECK-NEXT: adcs r3, r1
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: cset r0, eq ; CHECK-NEXT: bic.w r1, r1, lr
; CHECK-NEXT: adds r6, r6, r7 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: adcs r3, r4 ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: cset r4, mi ; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: cmp r5, r4 ; CHECK-NEXT: it ne
; CHECK-NEXT: cset r5, ne ; CHECK-NEXT: asrne r4, r3, #31
; CHECK-NEXT: ands r0, r5 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ands r0, r0, #1 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
; CHECK-NEXT: it ne ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: asrne r6, r3, #31
; CHECK-NEXT: vmov q0[2], q0[0], r6, r1
; CHECK-NEXT: mvn r1, #-2147483648
; CHECK-NEXT: tst.w r2, #1 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: cinv r2, r1, eq ; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp.w r12, #0 ; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r2, r2, lr, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: tst.w r4, #1 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cinv r1, r1, eq ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csel r0, r1, r3, ne ; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-NEXT: csel r1, r2, r3, ne
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2) %0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: uadd_int8_t: ; CHECK-LABEL: uadd_int8_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
entry: entry:
%0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2) %0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: ssub_int64_t: ; CHECK-LABEL: ssub_int64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov lr, s6 ; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r4, s1 ; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: vmov r6, s4 ; CHECK-NEXT: subs r2, r2, r3
; CHECK-NEXT: vmov r7, s0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r3, mi
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: cset r12, ne
; CHECK-NEXT: subs.w r1, r1, lr
; CHECK-NEXT: sbcs.w lr, r2, r0
; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: cset r3, ne
; CHECK-NEXT: and.w r3, r3, r12
; CHECK-NEXT: ands r12, r3, #1
; CHECK-NEXT: vmov r3, s5 ; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: eor.w r12, r1, r0
; CHECK-NEXT: sbc.w r0, r1, r0
; CHECK-NEXT: eors r1, r0
; CHECK-NEXT: ands.w r1, r1, r12
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r12, r1, #1
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: asrne.w r1, lr, #31 ; CHECK-NEXT: asrne r2, r0, #31
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: subs r4, r5, r4
; CHECK-NEXT: cset r0, mi ; CHECK-NEXT: mvn r5, #-2147483648
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: eor.w lr, r1, r3
; CHECK-NEXT: cset r5, mi ; CHECK-NEXT: sbc.w r3, r1, r3
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: eors r1, r3
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: ands.w r1, r1, lr
; CHECK-NEXT: subs r6, r7, r6 ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: sbcs.w r3, r4, r3 ; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: cset r4, mi ; CHECK-NEXT: it ne
; CHECK-NEXT: cmp r5, r4 ; CHECK-NEXT: asrne r4, r3, #31
; CHECK-NEXT: cset r5, ne ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ands r0, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r2
; CHECK-NEXT: ands r0, r0, #1 ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r6, r3, #31
; CHECK-NEXT: vmov q0[2], q0[0], r6, r1
; CHECK-NEXT: mvn r1, #-2147483648
; CHECK-NEXT: tst.w r2, #1 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: cinv r2, r1, eq ; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: cmp.w r12, #0 ; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r2, r2, lr, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: tst.w r4, #1 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cinv r1, r1, eq ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csel r0, r1, r3, ne ; CHECK-NEXT: cinv r2, r5, eq
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-NEXT: csel r1, r2, r3, ne
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2) %0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: usub_int8_t: ; CHECK-LABEL: usub_int8_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines