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Differential D97181

[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO.
ClosedPublic

Authored by craig.topper on Feb 21 2021, 11:53 PM.

Details

Reviewers
RKSimon
spatel
efriedma
luismarques
Commits
rGeb165090bb06: [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without…
Summary

This code creates 3 setccs that need to be expanded. It was
creating a sign bit test as setge X, 0 which is non-canonical.
Canonical would be setgt X, -1. This misses the special case in
IntegerExpandSetCCOperands for sign bit tests that assumes
canonical form. If we don't hit this special case we end up
with a multipart setcc instead of just checking the sign of
the high part.

To fix this I've reversed the polarity of all of the setccs to
setlt X, 0 which is canonical. The rest of the logic should
still work. This seems to produce better code on RISCV which
lacks a setgt instruction.

This probably still isn't the best code sequence we could use here.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 21 2021, 11:53 PM
Herald added subscribers: frasercrmck, apazos, sameer.abuasal and 19 others. · View Herald TranscriptFeb 21 2021, 11:53 PM
craig.topper requested review of this revision.Feb 21 2021, 11:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2021, 11:53 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B90185: Diff 325381.Feb 22 2021, 12:26 AM
craig.topper edited the summary of this revision. (Show Details)Feb 22 2021, 2:49 PM
RKSimon accepted this revision.Feb 23 2021, 5:42 AM

LGTM

This revision is now accepted and ready to land.Feb 23 2021, 5:42 AM
Closed by commit rGeb165090bb06: [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without… (authored by craig.topper). · Explain WhyFeb 23 2021, 9:53 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGeb165090bb06: [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without….

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
12 lines
test/
CodeGen/
AArch64/
28 lines
28 lines
ARM/
43 lines
40 lines
39 lines
63 lines
RISCV/
112 lines
116 lines
112 lines
112 lines
339 lines
Thumb2/
172 lines

Diff 325381

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
Lint: Lint
Inline Actions

clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 3,647 Lines • ▼ Show 20 Lines if (HasCarryOp) {
// non-overflow-checking operation. // non-overflow-checking operation.
SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
ISD::ADD : ISD::SUB, dl, LHS.getValueType(), ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
LHS, RHS); LHS, RHS);
SplitInteger(Sum, Lo, Hi); SplitInteger(Sum, Lo, Hi);
// Compute the overflow. // Compute the overflow.
// //
// LHSSign -> LHS >= 0 // LHSSign -> LHS < 0
// RHSSign -> RHS >= 0 // RHSSign -> RHS < 0
// SumSign -> Sum >= 0 // SumSign -> Sum < 0
// //
// Add: // Add:
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
// Sub: // Sub:
// Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
// //
EVT OType = Node->getValueType(1); EVT OType = Node->getValueType(1);
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETLT);
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETLT);
SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
Node->getOpcode() == ISD::SADDO ? Node->getOpcode() == ISD::SADDO ?
ISD::SETEQ : ISD::SETNE); ISD::SETEQ : ISD::SETNE);
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETLT);
SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
Ovf = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); Ovf = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
} }
// Use the calculated overflow everywhere. // Use the calculated overflow everywhere.
ReplaceValueWith(SDValue(Node, 1), Ovf); ReplaceValueWith(SDValue(Node, 1), Ovf);
} }
▲ Show 20 Lines • Show All 1,229 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Show First 20 Lines • Show All 361 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x7, #0 // =0 ; CHECK-NEXT: cmp x7, #0 // =0
; CHECK-NEXT: cset w9, ge ; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: csinc w9, w9, wzr, ne
; CHECK-NEXT: cmp x3, #0 // =0 ; CHECK-NEXT: cmp x3, #0 // =0
; CHECK-NEXT: cset w10, ge ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: csinc w10, w10, wzr, ne
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, eq ; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: adds x11, x2, x6 ; CHECK-NEXT: adds x11, x2, x6
; CHECK-NEXT: adcs x12, x3, x7 ; CHECK-NEXT: adcs x12, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: csinc w13, w13, wzr, ne ; CHECK-NEXT: cset w15, lt
; CHECK-NEXT: cinv x14, x8, ge ; CHECK-NEXT: cinv x14, x8, ge
; CHECK-NEXT: cmp w10, w13 ; CHECK-NEXT: cmp w10, w15
; CHECK-NEXT: cset w13, ne ; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: asr x10, x12, #63 ; CHECK-NEXT: asr x13, x12, #63
; CHECK-NEXT: tst w9, w13 ; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: csel x2, x13, x11, ne
; CHECK-NEXT: csel x3, x14, x12, ne ; CHECK-NEXT: csel x3, x14, x12, ne
; CHECK-NEXT: csel x2, x10, x11, ne
; CHECK-NEXT: cmp x5, #0 // =0 ; CHECK-NEXT: cmp x5, #0 // =0
; CHECK-NEXT: cset w9, ge ; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: csinc w9, w9, wzr, ne
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cmp x1, #0 // =0
; CHECK-NEXT: cset w10, ge ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: csinc w10, w10, wzr, ne
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, eq ; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: adds x11, x0, x4 ; CHECK-NEXT: adds x11, x0, x4
; CHECK-NEXT: adcs x12, x1, x5 ; CHECK-NEXT: adcs x12, x1, x5
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge ; CHECK-NEXT: cset w13, lt
; CHECK-NEXT: csinc w13, w13, wzr, ne
; CHECK-NEXT: cinv x8, x8, ge ; CHECK-NEXT: cinv x8, x8, ge
; CHECK-NEXT: cmp w10, w13 ; CHECK-NEXT: cmp w10, w13
; CHECK-NEXT: cset w10, ne ; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: tst w9, w10 ; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: asr x9, x12, #63 ; CHECK-NEXT: asr x9, x12, #63
; CHECK-NEXT: csel x9, x9, x11, ne ; CHECK-NEXT: csel x9, x9, x11, ne
; CHECK-NEXT: csel x1, x8, x12, ne ; CHECK-NEXT: csel x1, x8, x12, ne
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

Show First 20 Lines • Show All 364 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: cmp x7, #0 // =0 ; CHECK-NEXT: cmp x7, #0 // =0
; CHECK-NEXT: cset w9, ge ; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: csinc w9, w9, wzr, ne
; CHECK-NEXT: cmp x3, #0 // =0 ; CHECK-NEXT: cmp x3, #0 // =0
; CHECK-NEXT: cset w10, ge ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: csinc w10, w10, wzr, ne
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, ne ; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: subs x11, x2, x6 ; CHECK-NEXT: subs x11, x2, x6
; CHECK-NEXT: sbcs x12, x3, x7 ; CHECK-NEXT: sbcs x12, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: csinc w13, w13, wzr, ne ; CHECK-NEXT: cset w15, lt
; CHECK-NEXT: cinv x14, x8, ge ; CHECK-NEXT: cinv x14, x8, ge
; CHECK-NEXT: cmp w10, w13 ; CHECK-NEXT: cmp w10, w15
; CHECK-NEXT: cset w13, ne ; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: asr x10, x12, #63 ; CHECK-NEXT: asr x13, x12, #63
; CHECK-NEXT: tst w9, w13 ; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: csel x2, x13, x11, ne
; CHECK-NEXT: csel x3, x14, x12, ne ; CHECK-NEXT: csel x3, x14, x12, ne
; CHECK-NEXT: csel x2, x10, x11, ne
; CHECK-NEXT: cmp x5, #0 // =0 ; CHECK-NEXT: cmp x5, #0 // =0
; CHECK-NEXT: cset w9, ge ; CHECK-NEXT: cset w9, lt
; CHECK-NEXT: csinc w9, w9, wzr, ne
; CHECK-NEXT: cmp x1, #0 // =0 ; CHECK-NEXT: cmp x1, #0 // =0
; CHECK-NEXT: cset w10, ge ; CHECK-NEXT: cset w10, lt
; CHECK-NEXT: csinc w10, w10, wzr, ne
; CHECK-NEXT: cmp w10, w9 ; CHECK-NEXT: cmp w10, w9
; CHECK-NEXT: cset w9, ne ; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: subs x11, x0, x4 ; CHECK-NEXT: subs x11, x0, x4
; CHECK-NEXT: sbcs x12, x1, x5 ; CHECK-NEXT: sbcs x12, x1, x5
; CHECK-NEXT: cmp x12, #0 // =0 ; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge ; CHECK-NEXT: cset w13, lt
; CHECK-NEXT: csinc w13, w13, wzr, ne
; CHECK-NEXT: cinv x8, x8, ge ; CHECK-NEXT: cinv x8, x8, ge
; CHECK-NEXT: cmp w10, w13 ; CHECK-NEXT: cmp w10, w13
; CHECK-NEXT: cset w10, ne ; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: tst w9, w10 ; CHECK-NEXT: tst w9, w10
; CHECK-NEXT: asr x9, x12, #63 ; CHECK-NEXT: asr x9, x12, #63
; CHECK-NEXT: csel x9, x9, x11, ne ; CHECK-NEXT: csel x9, x9, x11, ne
; CHECK-NEXT: csel x1, x8, x12, ne ; CHECK-NEXT: csel x1, x8, x12, ne
; CHECK-NEXT: fmov d0, x9 ; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x1 ; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: fmov x0, d0 ; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
ret <2 x i128> %z ret <2 x i128> %z
} }

llvm/test/CodeGen/ARM/sadd_sat.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: .pad #4
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: sub sp, #4
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill ; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: movs r4, #1 ; CHECK-T1-NEXT: movs r4, #1
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: cmp r3, #0 ; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: bge .LBB1_2 ; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r5, r0 ; CHECK-T1-NEXT: mov r5, r0
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r7, r4 ; CHECK-T1-NEXT: mov r7, r4
; CHECK-T1-NEXT: bge .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r7, r0 ; CHECK-T1-NEXT: mov r7, r0
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r6, r7, r5 ; CHECK-T1-NEXT: subs r6, r7, r5
; CHECK-T1-NEXT: rsbs r5, r6, #0 ; CHECK-T1-NEXT: rsbs r5, r6, #0
; CHECK-T1-NEXT: adcs r5, r6 ; CHECK-T1-NEXT: adcs r5, r6
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: adds r6, r2, r6 ; CHECK-T1-NEXT: adds r6, r2, r6
; CHECK-T1-NEXT: adcs r1, r3 ; CHECK-T1-NEXT: adcs r1, r3
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r2, r4 ; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: bge .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r0, r7, r2 ; CHECK-T1-NEXT: subs r0, r7, r2
; CHECK-T1-NEXT: subs r2, r0, #1 ; CHECK-T1-NEXT: subs r2, r0, #1
; CHECK-T1-NEXT: sbcs r0, r2 ; CHECK-T1-NEXT: sbcs r0, r2
; CHECK-T1-NEXT: ands r5, r0 ; CHECK-T1-NEXT: ands r5, r0
; CHECK-T1-NEXT: beq .LBB1_8 ; CHECK-T1-NEXT: beq .LBB1_8
Show All 22 Lines
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.13:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func2: ; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r7, lr} ; CHECK-T2-NEXT: .save {r7, lr}
; CHECK-T2-NEXT: push {r7, lr} ; CHECK-T2-NEXT: push {r7, lr}
; CHECK-T2-NEXT: cmp.w r1, #-1 ; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w lr, #0 ; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt.w lr, #1 ; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: adds r0, r0, r2 ; CHECK-T2-NEXT: adds r0, r0, r2
; CHECK-T2-NEXT: adc.w r2, r1, r3 ; CHECK-T2-NEXT: adcs.w r2, r1, r3
; CHECK-T2-NEXT: movs r1, #0 ; CHECK-T2-NEXT: mov.w r1, #0
; CHECK-T2-NEXT: cmp.w r2, #-1 ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: movmi r1, #1
; CHECK-T2-NEXT: movgt r1, #1
; CHECK-T2-NEXT: subs.w r1, lr, r1
; CHECK-T2-NEXT: mov.w r12, #0 ; CHECK-T2-NEXT: mov.w r12, #0
; CHECK-T2-NEXT: subs.w r1, lr, r1
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1 ; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: cmp.w r3, #-1 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt.w r12, #1 ; CHECK-T2-NEXT: movmi.w r12, #1
; CHECK-T2-NEXT: sub.w r3, lr, r12 ; CHECK-T2-NEXT: sub.w r3, lr, r12
; CHECK-T2-NEXT: clz r3, r3 ; CHECK-T2-NEXT: clz r3, r3
; CHECK-T2-NEXT: lsrs r3, r3, #5 ; CHECK-T2-NEXT: lsrs r3, r3, #5
; CHECK-T2-NEXT: ands r3, r1 ; CHECK-T2-NEXT: ands r3, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r2, #31 ; CHECK-T2-NEXT: asrne r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it eq
; CHECK-T2-NEXT: moveq r1, r2 ; CHECK-T2-NEXT: moveq r1, r2
; CHECK-T2-NEXT: pop {r7, pc} ; CHECK-T2-NEXT: pop {r7, pc}
; ;
; CHECK-ARM-LABEL: func2: ; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r11, lr} ; CHECK-ARM-NEXT: .save {r11, lr}
; CHECK-ARM-NEXT: push {r11, lr} ; CHECK-ARM-NEXT: push {r11, lr}
; CHECK-ARM-NEXT: cmn r1, #1 ; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov lr, #0 ; CHECK-ARM-NEXT: mov lr, #0
; CHECK-ARM-NEXT: movgt lr, #1 ; CHECK-ARM-NEXT: movmi lr, #1
; CHECK-ARM-NEXT: adds r0, r0, r2 ; CHECK-ARM-NEXT: adds r0, r0, r2
; CHECK-ARM-NEXT: adc r2, r1, r3 ; CHECK-ARM-NEXT: adcs r2, r1, r3
; CHECK-ARM-NEXT: mov r1, #0 ; CHECK-ARM-NEXT: mov r1, #0
; CHECK-ARM-NEXT: cmn r2, #1 ; CHECK-ARM-NEXT: movmi r1, #1
; CHECK-ARM-NEXT: mov r12, #0 ; CHECK-ARM-NEXT: mov r12, #0
; CHECK-ARM-NEXT: movgt r1, #1
; CHECK-ARM-NEXT: subs r1, lr, r1 ; CHECK-ARM-NEXT: subs r1, lr, r1
; CHECK-ARM-NEXT: movne r1, #1 ; CHECK-ARM-NEXT: movne r1, #1
; CHECK-ARM-NEXT: cmn r3, #1 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: movgt r12, #1 ; CHECK-ARM-NEXT: movmi r12, #1
; CHECK-ARM-NEXT: sub r3, lr, r12 ; CHECK-ARM-NEXT: sub r3, lr, r12
; CHECK-ARM-NEXT: clz r3, r3 ; CHECK-ARM-NEXT: clz r3, r3
; CHECK-ARM-NEXT: lsr r3, r3, #5 ; CHECK-ARM-NEXT: lsr r3, r3, #5
; CHECK-ARM-NEXT: ands r3, r3, r1 ; CHECK-ARM-NEXT: ands r3, r3, r1
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: asrne r0, r2, #31 ; CHECK-ARM-NEXT: asrne r0, r2, #31
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/sadd_sat_plus.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: .pad #4
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: sub sp, #4
; CHECK-T1-NEXT: ldr r5, [sp, #28] ; CHECK-T1-NEXT: ldr r5, [sp, #28]
; CHECK-T1-NEXT: movs r2, #1 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: movs r4, #0 ; CHECK-T1-NEXT: movs r4, #0
; CHECK-T1-NEXT: cmp r5, #0 ; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: mov r3, r2 ; CHECK-T1-NEXT: mov r3, r2
; CHECK-T1-NEXT: bge .LBB1_2 ; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r3, r4 ; CHECK-T1-NEXT: mov r3, r4
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r6, r2 ; CHECK-T1-NEXT: mov r6, r2
; CHECK-T1-NEXT: bge .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r6, r4 ; CHECK-T1-NEXT: mov r6, r4
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r7, r6, r3 ; CHECK-T1-NEXT: subs r7, r6, r3
; CHECK-T1-NEXT: rsbs r3, r7, #0 ; CHECK-T1-NEXT: rsbs r3, r7, #0
; CHECK-T1-NEXT: adcs r3, r7 ; CHECK-T1-NEXT: adcs r3, r7
; CHECK-T1-NEXT: ldr r7, [sp, #24] ; CHECK-T1-NEXT: ldr r7, [sp, #24]
; CHECK-T1-NEXT: adds r0, r0, r7 ; CHECK-T1-NEXT: adds r0, r0, r7
; CHECK-T1-NEXT: adcs r1, r5 ; CHECK-T1-NEXT: adcs r1, r5
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r5, r2 ; CHECK-T1-NEXT: mov r5, r2
; CHECK-T1-NEXT: bge .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r4, r6, r5 ; CHECK-T1-NEXT: subs r4, r6, r5
; CHECK-T1-NEXT: subs r5, r4, #1 ; CHECK-T1-NEXT: subs r5, r4, #1
; CHECK-T1-NEXT: sbcs r4, r5 ; CHECK-T1-NEXT: sbcs r4, r5
; CHECK-T1-NEXT: ands r3, r4 ; CHECK-T1-NEXT: ands r3, r4
; CHECK-T1-NEXT: beq .LBB1_8 ; CHECK-T1-NEXT: beq .LBB1_8
Show All 22 Lines
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func64: ; CHECK-T2-LABEL: func64:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r7, lr} ; CHECK-T2-NEXT: .save {r7, lr}
; CHECK-T2-NEXT: push {r7, lr} ; CHECK-T2-NEXT: push {r7, lr}
; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8] ; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8]
; CHECK-T2-NEXT: cmp.w r1, #-1 ; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w r3, #0 ; CHECK-T2-NEXT: mov.w r3, #0
; CHECK-T2-NEXT: mov.w lr, #0 ; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt r3, #1 ; CHECK-T2-NEXT: movmi r3, #1
; CHECK-T2-NEXT: adds r0, r0, r2 ; CHECK-T2-NEXT: adds r0, r0, r2
; CHECK-T2-NEXT: adc.w r2, r1, r12 ; CHECK-T2-NEXT: adcs.w r2, r1, r12
; CHECK-T2-NEXT: movs r1, #0 ; CHECK-T2-NEXT: mov.w r1, #0
; CHECK-T2-NEXT: cmp.w r2, #-1 ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: movmi r1, #1
; CHECK-T2-NEXT: movgt r1, #1
; CHECK-T2-NEXT: subs r1, r3, r1 ; CHECK-T2-NEXT: subs r1, r3, r1
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1 ; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: cmp.w r12, #-1 ; CHECK-T2-NEXT: cmp.w r12, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt.w lr, #1 ; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: sub.w r3, r3, lr ; CHECK-T2-NEXT: sub.w r3, r3, lr
; CHECK-T2-NEXT: clz r3, r3 ; CHECK-T2-NEXT: clz r3, r3
; CHECK-T2-NEXT: lsrs r3, r3, #5 ; CHECK-T2-NEXT: lsrs r3, r3, #5
; CHECK-T2-NEXT: ands r3, r1 ; CHECK-T2-NEXT: ands r3, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r2, #31 ; CHECK-T2-NEXT: asrne r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
Show All 9 Lines
; CHECK-ARM-NEXT: .save {r11, lr} ; CHECK-ARM-NEXT: .save {r11, lr}
; CHECK-ARM-NEXT: push {r11, lr} ; CHECK-ARM-NEXT: push {r11, lr}
; CHECK-ARM-NEXT: ldr r2, [sp, #8] ; CHECK-ARM-NEXT: ldr r2, [sp, #8]
; CHECK-ARM-NEXT: mov r3, #0 ; CHECK-ARM-NEXT: mov r3, #0
; CHECK-ARM-NEXT: ldr r12, [sp, #12] ; CHECK-ARM-NEXT: ldr r12, [sp, #12]
; CHECK-ARM-NEXT: adds r0, r0, r2 ; CHECK-ARM-NEXT: adds r0, r0, r2
; CHECK-ARM-NEXT: mov r2, #0 ; CHECK-ARM-NEXT: mov r2, #0
; CHECK-ARM-NEXT: adc lr, r1, r12 ; CHECK-ARM-NEXT: adc lr, r1, r12
; CHECK-ARM-NEXT: cmn r1, #1 ; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r1, #0 ; CHECK-ARM-NEXT: mov r1, #0
; CHECK-ARM-NEXT: movwgt r1, #1 ; CHECK-ARM-NEXT: movwmi r1, #1
; CHECK-ARM-NEXT: cmn lr, #1 ; CHECK-ARM-NEXT: cmp lr, #0
; CHECK-ARM-NEXT: movwgt r2, #1 ; CHECK-ARM-NEXT: movwmi r2, #1
; CHECK-ARM-NEXT: subs r2, r1, r2 ; CHECK-ARM-NEXT: subs r2, r1, r2
; CHECK-ARM-NEXT: movwne r2, #1 ; CHECK-ARM-NEXT: movwne r2, #1
; CHECK-ARM-NEXT: cmn r12, #1 ; CHECK-ARM-NEXT: cmp r12, #0
; CHECK-ARM-NEXT: movwgt r3, #1 ; CHECK-ARM-NEXT: movwmi r3, #1
; CHECK-ARM-NEXT: sub r1, r1, r3 ; CHECK-ARM-NEXT: sub r1, r1, r3
; CHECK-ARM-NEXT: clz r1, r1 ; CHECK-ARM-NEXT: clz r1, r1
; CHECK-ARM-NEXT: lsr r1, r1, #5 ; CHECK-ARM-NEXT: lsr r1, r1, #5
; CHECK-ARM-NEXT: ands r2, r1, r2 ; CHECK-ARM-NEXT: ands r2, r1, r2
; CHECK-ARM-NEXT: asrne r0, lr, #31 ; CHECK-ARM-NEXT: asrne r0, lr, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp lr, #0 ; CHECK-ARM-NEXT: cmp lr, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ssub_sat.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: .pad #4
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: sub sp, #4
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill ; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: movs r4, #1 ; CHECK-T1-NEXT: movs r4, #1
; CHECK-T1-NEXT: movs r0, #0 ; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: cmp r3, #0 ; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: bge .LBB1_2 ; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r5, r0 ; CHECK-T1-NEXT: mov r5, r0
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r7, r4 ; CHECK-T1-NEXT: mov r7, r4
; CHECK-T1-NEXT: bge .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r7, r0 ; CHECK-T1-NEXT: mov r7, r0
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r5, r7, r5 ; CHECK-T1-NEXT: subs r5, r7, r5
; CHECK-T1-NEXT: subs r6, r5, #1 ; CHECK-T1-NEXT: subs r6, r5, #1
; CHECK-T1-NEXT: sbcs r5, r6 ; CHECK-T1-NEXT: sbcs r5, r6
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: subs r6, r2, r6 ; CHECK-T1-NEXT: subs r6, r2, r6
; CHECK-T1-NEXT: sbcs r1, r3 ; CHECK-T1-NEXT: sbcs r1, r3
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r2, r4 ; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: bge .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: mov r2, r0 ; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r0, r7, r2 ; CHECK-T1-NEXT: subs r0, r7, r2
; CHECK-T1-NEXT: subs r2, r0, #1 ; CHECK-T1-NEXT: subs r2, r0, #1
; CHECK-T1-NEXT: sbcs r0, r2 ; CHECK-T1-NEXT: sbcs r0, r2
; CHECK-T1-NEXT: ands r5, r0 ; CHECK-T1-NEXT: ands r5, r0
; CHECK-T1-NEXT: beq .LBB1_8 ; CHECK-T1-NEXT: beq .LBB1_8
Show All 22 Lines
; CHECK-T1-NEXT: @ %bb.13: ; CHECK-T1-NEXT: @ %bb.13:
; CHECK-T1-NEXT: .LCPI1_0: ; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; CHECK-T2-LABEL: func2: ; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr} ; CHECK-T2-NEXT: .save {r4, lr}
; CHECK-T2-NEXT: push {r4, lr} ; CHECK-T2-NEXT: push {r4, lr}
; CHECK-T2-NEXT: cmp.w r3, #-1 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: mov.w lr, #0 ; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt.w lr, #1 ; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: cmp.w r1, #-1 ; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: mov.w r4, #0 ; CHECK-T2-NEXT: mov.w r4, #0
; CHECK-T2-NEXT: mov.w r12, #0 ; CHECK-T2-NEXT: mov.w r12, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt r4, #1 ; CHECK-T2-NEXT: movmi r4, #1
; CHECK-T2-NEXT: subs.w lr, r4, lr ; CHECK-T2-NEXT: subs.w lr, r4, lr
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne.w lr, #1 ; CHECK-T2-NEXT: movne.w lr, #1
; CHECK-T2-NEXT: subs r0, r0, r2 ; CHECK-T2-NEXT: subs r0, r0, r2
; CHECK-T2-NEXT: sbc.w r2, r1, r3 ; CHECK-T2-NEXT: sbcs.w r2, r1, r3
; CHECK-T2-NEXT: cmp.w r2, #-1 ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: movmi.w r12, #1
; CHECK-T2-NEXT: movgt.w r12, #1
; CHECK-T2-NEXT: subs.w r1, r4, r12 ; CHECK-T2-NEXT: subs.w r1, r4, r12
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1 ; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: ands.w r3, lr, r1 ; CHECK-T2-NEXT: ands.w r3, lr, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r2, #31 ; CHECK-T2-NEXT: asrne r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0 ; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it eq
; CHECK-T2-NEXT: moveq r1, r2 ; CHECK-T2-NEXT: moveq r1, r2
; CHECK-T2-NEXT: pop {r4, pc} ; CHECK-T2-NEXT: pop {r4, pc}
; ;
; CHECK-ARM-LABEL: func2: ; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, lr} ; CHECK-ARM-NEXT: .save {r4, lr}
; CHECK-ARM-NEXT: push {r4, lr} ; CHECK-ARM-NEXT: push {r4, lr}
; CHECK-ARM-NEXT: cmn r3, #1 ; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: mov lr, #0 ; CHECK-ARM-NEXT: mov lr, #0
; CHECK-ARM-NEXT: movgt lr, #1 ; CHECK-ARM-NEXT: movmi lr, #1
; CHECK-ARM-NEXT: cmn r1, #1 ; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r4, #0 ; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: mov r12, #0 ; CHECK-ARM-NEXT: mov r12, #0
; CHECK-ARM-NEXT: movgt r4, #1 ; CHECK-ARM-NEXT: movmi r4, #1
; CHECK-ARM-NEXT: subs lr, r4, lr ; CHECK-ARM-NEXT: subs lr, r4, lr
; CHECK-ARM-NEXT: movne lr, #1 ; CHECK-ARM-NEXT: movne lr, #1
; CHECK-ARM-NEXT: subs r0, r0, r2 ; CHECK-ARM-NEXT: subs r0, r0, r2
; CHECK-ARM-NEXT: sbc r2, r1, r3 ; CHECK-ARM-NEXT: sbcs r2, r1, r3
; CHECK-ARM-NEXT: cmn r2, #1 ; CHECK-ARM-NEXT: movmi r12, #1
; CHECK-ARM-NEXT: movgt r12, #1
; CHECK-ARM-NEXT: subs r1, r4, r12 ; CHECK-ARM-NEXT: subs r1, r4, r12
; CHECK-ARM-NEXT: movne r1, #1 ; CHECK-ARM-NEXT: movne r1, #1
; CHECK-ARM-NEXT: ands r3, lr, r1 ; CHECK-ARM-NEXT: ands r3, lr, r1
; CHECK-ARM-NEXT: asrne r0, r2, #31 ; CHECK-ARM-NEXT: asrne r0, r2, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0 ; CHECK-ARM-NEXT: cmp r3, #0
▲ Show 20 Lines • Show All 456 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ssub_sat_plus.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: .pad #4 ; CHECK-T1-NEXT: .pad #4
; CHECK-T1-NEXT: sub sp, #4 ; CHECK-T1-NEXT: sub sp, #4
; CHECK-T1-NEXT: ldr r5, [sp, #28] ; CHECK-T1-NEXT: ldr r5, [sp, #28]
; CHECK-T1-NEXT: movs r2, #1 ; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: movs r4, #0 ; CHECK-T1-NEXT: movs r4, #0
; CHECK-T1-NEXT: cmp r5, #0 ; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: mov r3, r2 ; CHECK-T1-NEXT: mov r3, r2
; CHECK-T1-NEXT: bge .LBB1_2 ; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: @ %bb.1: ; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r3, r4 ; CHECK-T1-NEXT: mov r3, r4
; CHECK-T1-NEXT: .LBB1_2: ; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0 ; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r6, r2 ; CHECK-T1-NEXT: mov r6, r2
; CHECK-T1-NEXT: bge .LBB1_4 ; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3: ; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r6, r4 ; CHECK-T1-NEXT: mov r6, r4
; CHECK-T1-NEXT: .LBB1_4: ; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r3, r6, r3 ; CHECK-T1-NEXT: subs r3, r6, r3
; CHECK-T1-NEXT: subs r7, r3, #1 ; CHECK-T1-NEXT: subs r7, r3, #1
; CHECK-T1-NEXT: sbcs r3, r7 ; CHECK-T1-NEXT: sbcs r3, r7
; CHECK-T1-NEXT: ldr r7, [sp, #24] ; CHECK-T1-NEXT: ldr r7, [sp, #24]
; CHECK-T1-NEXT: subs r0, r0, r7 ; CHECK-T1-NEXT: subs r0, r0, r7
; CHECK-T1-NEXT: sbcs r1, r5 ; CHECK-T1-NEXT: sbcs r1, r5
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r5, r2 ; CHECK-T1-NEXT: mov r5, r2
; CHECK-T1-NEXT: bge .LBB1_6 ; CHECK-T1-NEXT: bmi .LBB1_6
; CHECK-T1-NEXT: @ %bb.5: ; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: mov r5, r4 ; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: .LBB1_6: ; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r4, r6, r5 ; CHECK-T1-NEXT: subs r4, r6, r5
; CHECK-T1-NEXT: subs r5, r4, #1 ; CHECK-T1-NEXT: subs r5, r4, #1
; CHECK-T1-NEXT: sbcs r4, r5 ; CHECK-T1-NEXT: sbcs r4, r5
; CHECK-T1-NEXT: ands r3, r4 ; CHECK-T1-NEXT: ands r3, r4
; CHECK-T1-NEXT: beq .LBB1_8 ; CHECK-T1-NEXT: beq .LBB1_8
Show All 25 Lines
; CHECK-T2-LABEL: func64: ; CHECK-T2-LABEL: func64:
; CHECK-T2: @ %bb.0: ; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr} ; CHECK-T2-NEXT: .save {r4, lr}
; CHECK-T2-NEXT: push {r4, lr} ; CHECK-T2-NEXT: push {r4, lr}
; CHECK-T2-NEXT: ldr.w r12, [sp, #12] ; CHECK-T2-NEXT: ldr.w r12, [sp, #12]
; CHECK-T2-NEXT: movs r2, #0 ; CHECK-T2-NEXT: movs r2, #0
; CHECK-T2-NEXT: movs r3, #0 ; CHECK-T2-NEXT: movs r3, #0
; CHECK-T2-NEXT: ldr r4, [sp, #8] ; CHECK-T2-NEXT: ldr r4, [sp, #8]
; CHECK-T2-NEXT: cmp.w r12, #-1 ; CHECK-T2-NEXT: cmp.w r12, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt r2, #1 ; CHECK-T2-NEXT: movmi r2, #1
; CHECK-T2-NEXT: cmp.w r1, #-1 ; CHECK-T2-NEXT: cmp r1, #0
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movgt r3, #1 ; CHECK-T2-NEXT: movmi r3, #1
; CHECK-T2-NEXT: subs r2, r3, r2 ; CHECK-T2-NEXT: subs r2, r3, r2
; CHECK-T2-NEXT: mov.w lr, #0 ; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r2, #1 ; CHECK-T2-NEXT: movne r2, #1
; CHECK-T2-NEXT: subs r0, r0, r4 ; CHECK-T2-NEXT: subs r0, r0, r4
; CHECK-T2-NEXT: sbc.w r4, r1, r12 ; CHECK-T2-NEXT: sbcs.w r4, r1, r12
; CHECK-T2-NEXT: cmp.w r4, #-1 ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: it gt ; CHECK-T2-NEXT: movmi.w lr, #1
; CHECK-T2-NEXT: movgt.w lr, #1
; CHECK-T2-NEXT: subs.w r1, r3, lr ; CHECK-T2-NEXT: subs.w r1, r3, lr
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1 ; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: ands r2, r1 ; CHECK-T2-NEXT: ands r2, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne ; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r4, #31 ; CHECK-T2-NEXT: asrne r0, r4, #31
; CHECK-T2-NEXT: cmp r4, #0 ; CHECK-T2-NEXT: cmp r4, #0
; CHECK-T2-NEXT: it mi ; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r2, #0 ; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it eq ; CHECK-T2-NEXT: it eq
; CHECK-T2-NEXT: moveq r1, r4 ; CHECK-T2-NEXT: moveq r1, r4
; CHECK-T2-NEXT: pop {r4, pc} ; CHECK-T2-NEXT: pop {r4, pc}
; ;
; CHECK-ARM-LABEL: func64: ; CHECK-ARM-LABEL: func64:
; CHECK-ARM: @ %bb.0: ; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, r5, r11, lr} ; CHECK-ARM-NEXT: .save {r4, lr}
; CHECK-ARM-NEXT: push {r4, r5, r11, lr} ; CHECK-ARM-NEXT: push {r4, lr}
; CHECK-ARM-NEXT: ldr lr, [sp, #20] ; CHECK-ARM-NEXT: ldr lr, [sp, #12]
; CHECK-ARM-NEXT: cmn r1, #1 ; CHECK-ARM-NEXT: cmp r1, #0
; CHECK-ARM-NEXT: mov r3, #0 ; CHECK-ARM-NEXT: mov r3, #0
; CHECK-ARM-NEXT: mov r4, #0 ; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: movwgt r3, #1 ; CHECK-ARM-NEXT: movwmi r3, #1
; CHECK-ARM-NEXT: cmn lr, #1 ; CHECK-ARM-NEXT: cmp lr, #0
; CHECK-ARM-NEXT: movwgt r4, #1 ; CHECK-ARM-NEXT: movwmi r4, #1
; CHECK-ARM-NEXT: ldr r12, [sp, #16] ; CHECK-ARM-NEXT: ldr r12, [sp, #8]
; CHECK-ARM-NEXT: subs r4, r3, r4 ; CHECK-ARM-NEXT: subs r4, r3, r4
; CHECK-ARM-NEXT: mov r5, #0 ; CHECK-ARM-NEXT: mov r2, #0
; CHECK-ARM-NEXT: movwne r4, #1 ; CHECK-ARM-NEXT: movwne r4, #1
; CHECK-ARM-NEXT: subs r0, r0, r12 ; CHECK-ARM-NEXT: subs r0, r0, r12
; CHECK-ARM-NEXT: sbc r2, r1, lr ; CHECK-ARM-NEXT: sbcs r12, r1, lr
; CHECK-ARM-NEXT: cmn r2, #1 ; CHECK-ARM-NEXT: movwmi r2, #1
; CHECK-ARM-NEXT: movwgt r5, #1 ; CHECK-ARM-NEXT: subs r1, r3, r2
; CHECK-ARM-NEXT: subs r1, r3, r5
; CHECK-ARM-NEXT: movwne r1, #1 ; CHECK-ARM-NEXT: movwne r1, #1
; CHECK-ARM-NEXT: ands r3, r4, r1 ; CHECK-ARM-NEXT: ands r2, r4, r1
; CHECK-ARM-NEXT: asrne r0, r2, #31 ; CHECK-ARM-NEXT: asrne r0, r12, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648 ; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp r2, #0 ; CHECK-ARM-NEXT: cmp r12, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0 ; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: moveq r1, r2 ; CHECK-ARM-NEXT: moveq r1, r12
; CHECK-ARM-NEXT: pop {r4, r5, r11, pc} ; CHECK-ARM-NEXT: pop {r4, pc}
%a = mul i64 %y, %z %a = mul i64 %y, %z
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z) %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
ret i64 %tmp ret i64 %tmp
} }
define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind { define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
; CHECK-T1-LABEL: func16: ; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0: ; CHECK-T1: @ %bb.0:
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/sadd_sat.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y); %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
ret i32 %tmp; ret i32 %tmp;
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: func2: ; RV32I-LABEL: func2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: add a5, a1, a3 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: add a5, a4, a3
; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: sltu a2, a0, a4 ; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: add a2, a5, a2 ; RV32I-NEXT: add a2, a5, a1
; RV32I-NEXT: addi a6, zero, -1 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a7, zero, 1 ; RV32I-NEXT: bgez a2, .LBB1_2
; RV32I-NEXT: addi a4, zero, 1
; RV32I-NEXT: beqz a2, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a4, a6, a2 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: addi a5, zero, 1 ; RV32I-NEXT: slti a5, a2, 0
; RV32I-NEXT: beqz a1, .LBB1_4 ; RV32I-NEXT: slti a4, a4, 0
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: xor a5, a4, a5
; RV32I-NEXT: slt a5, a6, a1 ; RV32I-NEXT: snez a5, a5
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: slti a3, a3, 0
; RV32I-NEXT: xor a1, a5, a4 ; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: beqz a3, .LBB1_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: slt a7, a6, a3
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: xor a3, a5, a7
; RV32I-NEXT: seqz a3, a3 ; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: and a3, a3, a1 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: bnez a3, .LBB1_10 ; RV32I-NEXT: bnez a3, .LBB1_4
; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: bltz a2, .LBB1_11
; RV32I-NEXT: .LBB1_8:
; RV32I-NEXT: beqz a3, .LBB1_12
; RV32I-NEXT: .LBB1_9:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_10: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, a2, 31 ; RV32I-NEXT: srai a0, a2, 31
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez a2, .LBB1_8
; RV32I-NEXT: .LBB1_11:
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: bnez a3, .LBB1_9
; RV32I-NEXT: .LBB1_12:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func2: ; RV64I-LABEL: func2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: add a3, a0, a1 ; RV64I-NEXT: add a3, a0, a1
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bgez a3, .LBB1_2 ; RV64I-NEXT: bgez a3, .LBB1_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: slt a2, a3, a2 ; RV64I-NEXT: slt a2, a3, a2
; RV64I-NEXT: slti a1, a1, 0 ; RV64I-NEXT: slti a1, a1, 0
; RV64I-NEXT: xor a1, a1, a2 ; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: bnez a1, .LBB1_4 ; RV64I-NEXT: bnez a1, .LBB1_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func2: ; RV32IZbb-LABEL: func2:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: mv a4, a0 ; RV32IZbb-NEXT: mv a4, a1
; RV32IZbb-NEXT: add a5, a1, a3 ; RV32IZbb-NEXT: mv a1, a0
; RV32IZbb-NEXT: add a5, a4, a3
; RV32IZbb-NEXT: add a0, a0, a2 ; RV32IZbb-NEXT: add a0, a0, a2
; RV32IZbb-NEXT: sltu a2, a0, a4 ; RV32IZbb-NEXT: sltu a1, a0, a1
; RV32IZbb-NEXT: add a2, a5, a2 ; RV32IZbb-NEXT: add a2, a5, a1
; RV32IZbb-NEXT: addi a6, zero, -1 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: addi a7, zero, 1 ; RV32IZbb-NEXT: bgez a2, .LBB1_2
; RV32IZbb-NEXT: addi a4, zero, 1
; RV32IZbb-NEXT: beqz a2, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: slt a4, a6, a2 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: addi a5, zero, 1 ; RV32IZbb-NEXT: slti a5, a2, 0
; RV32IZbb-NEXT: beqz a1, .LBB1_4 ; RV32IZbb-NEXT: slti a4, a4, 0
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: xor a5, a4, a5
; RV32IZbb-NEXT: slt a5, a6, a1 ; RV32IZbb-NEXT: snez a5, a5
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: slti a3, a3, 0
; RV32IZbb-NEXT: xor a1, a5, a4 ; RV32IZbb-NEXT: xor a3, a4, a3
; RV32IZbb-NEXT: snez a1, a1
; RV32IZbb-NEXT: beqz a3, .LBB1_6
; RV32IZbb-NEXT: # %bb.5:
; RV32IZbb-NEXT: slt a7, a6, a3
; RV32IZbb-NEXT: .LBB1_6:
; RV32IZbb-NEXT: xor a3, a5, a7
; RV32IZbb-NEXT: seqz a3, a3 ; RV32IZbb-NEXT: seqz a3, a3
; RV32IZbb-NEXT: and a3, a3, a1 ; RV32IZbb-NEXT: and a3, a3, a5
; RV32IZbb-NEXT: bnez a3, .LBB1_10 ; RV32IZbb-NEXT: bnez a3, .LBB1_4
; RV32IZbb-NEXT: # %bb.7: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: lui a1, 524288 ; RV32IZbb-NEXT: mv a1, a2
; RV32IZbb-NEXT: bltz a2, .LBB1_11
; RV32IZbb-NEXT: .LBB1_8:
; RV32IZbb-NEXT: beqz a3, .LBB1_12
; RV32IZbb-NEXT: .LBB1_9:
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_10: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, a2, 31 ; RV32IZbb-NEXT: srai a0, a2, 31
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez a2, .LBB1_8
; RV32IZbb-NEXT: .LBB1_11:
; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: bnez a3, .LBB1_9
; RV32IZbb-NEXT: .LBB1_12:
; RV32IZbb-NEXT: mv a1, a2
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func2: ; RV64IZbb-LABEL: func2:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: mv a2, a0 ; RV64IZbb-NEXT: mv a2, a0
; RV64IZbb-NEXT: add a3, a0, a1 ; RV64IZbb-NEXT: add a3, a0, a1
; RV64IZbb-NEXT: addi a0, zero, -1 ; RV64IZbb-NEXT: addi a0, zero, -1
; RV64IZbb-NEXT: slli a0, a0, 63 ; RV64IZbb-NEXT: slli a0, a0, 63
▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64IZbb-NEXT: ret
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32I-LABEL: func64: ; RV32I-LABEL: func64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: add a3, a1, a5 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: add a3, a2, a5
; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: add a0, a0, a4
; RV32I-NEXT: sltu a2, a0, a2 ; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: add a2, a3, a2 ; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: addi a6, zero, -1 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a7, zero, 1 ; RV32I-NEXT: bgez a3, .LBB1_2
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: beqz a2, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a3, a6, a2 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: addi a4, zero, 1 ; RV32I-NEXT: slti a4, a3, 0
; RV32I-NEXT: beqz a1, .LBB1_4 ; RV32I-NEXT: slti a2, a2, 0
; RV32I-NEXT: xor a4, a2, a4
; RV32I-NEXT: snez a4, a4
; RV32I-NEXT: slti a5, a5, 0
; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: bnez a2, .LBB1_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: slt a4, a6, a1 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: xor a1, a4, a3
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: beqz a5, .LBB1_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: slt a7, a6, a5
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: xor a3, a4, a7
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: and a3, a3, a1
; RV32I-NEXT: bnez a3, .LBB1_10
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bltz a2, .LBB1_11
; RV32I-NEXT: .LBB1_8:
; RV32I-NEXT: beqz a3, .LBB1_12
; RV32I-NEXT: .LBB1_9:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_10: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, a2, 31 ; RV32I-NEXT: srai a0, a3, 31
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez a2, .LBB1_8
; RV32I-NEXT: .LBB1_11:
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: bnez a3, .LBB1_9
; RV32I-NEXT: .LBB1_12:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func64: ; RV64I-LABEL: func64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: add a3, a0, a2 ; RV64I-NEXT: add a3, a0, a2
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bgez a3, .LBB1_2 ; RV64I-NEXT: bgez a3, .LBB1_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: slt a1, a3, a1 ; RV64I-NEXT: slt a1, a3, a1
; RV64I-NEXT: slti a2, a2, 0 ; RV64I-NEXT: slti a2, a2, 0
; RV64I-NEXT: xor a1, a2, a1 ; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: bnez a1, .LBB1_4 ; RV64I-NEXT: bnez a1, .LBB1_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func64: ; RV32IZbb-LABEL: func64:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: mv a2, a0 ; RV32IZbb-NEXT: mv a2, a1
; RV32IZbb-NEXT: add a3, a1, a5 ; RV32IZbb-NEXT: mv a1, a0
; RV32IZbb-NEXT: add a3, a2, a5
; RV32IZbb-NEXT: add a0, a0, a4 ; RV32IZbb-NEXT: add a0, a0, a4
; RV32IZbb-NEXT: sltu a2, a0, a2 ; RV32IZbb-NEXT: sltu a1, a0, a1
; RV32IZbb-NEXT: add a2, a3, a2 ; RV32IZbb-NEXT: add a3, a3, a1
; RV32IZbb-NEXT: addi a6, zero, -1 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: addi a7, zero, 1 ; RV32IZbb-NEXT: bgez a3, .LBB1_2
; RV32IZbb-NEXT: addi a3, zero, 1
; RV32IZbb-NEXT: beqz a2, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: slt a3, a6, a2 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: addi a4, zero, 1 ; RV32IZbb-NEXT: slti a4, a3, 0
; RV32IZbb-NEXT: beqz a1, .LBB1_4 ; RV32IZbb-NEXT: slti a2, a2, 0
; RV32IZbb-NEXT: xor a4, a2, a4
; RV32IZbb-NEXT: snez a4, a4
; RV32IZbb-NEXT: slti a5, a5, 0
; RV32IZbb-NEXT: xor a2, a2, a5
; RV32IZbb-NEXT: seqz a2, a2
; RV32IZbb-NEXT: and a2, a2, a4
; RV32IZbb-NEXT: bnez a2, .LBB1_4
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: slt a4, a6, a1 ; RV32IZbb-NEXT: mv a1, a3
; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: xor a1, a4, a3
; RV32IZbb-NEXT: snez a1, a1
; RV32IZbb-NEXT: beqz a5, .LBB1_6
; RV32IZbb-NEXT: # %bb.5:
; RV32IZbb-NEXT: slt a7, a6, a5
; RV32IZbb-NEXT: .LBB1_6:
; RV32IZbb-NEXT: xor a3, a4, a7
; RV32IZbb-NEXT: seqz a3, a3
; RV32IZbb-NEXT: and a3, a3, a1
; RV32IZbb-NEXT: bnez a3, .LBB1_10
; RV32IZbb-NEXT: # %bb.7:
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bltz a2, .LBB1_11
; RV32IZbb-NEXT: .LBB1_8:
; RV32IZbb-NEXT: beqz a3, .LBB1_12
; RV32IZbb-NEXT: .LBB1_9:
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_10: ; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, a2, 31 ; RV32IZbb-NEXT: srai a0, a3, 31
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez a2, .LBB1_8
; RV32IZbb-NEXT: .LBB1_11:
; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: bnez a3, .LBB1_9
; RV32IZbb-NEXT: .LBB1_12:
; RV32IZbb-NEXT: mv a1, a2
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func64: ; RV64IZbb-LABEL: func64:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: mv a1, a0 ; RV64IZbb-NEXT: mv a1, a0
; RV64IZbb-NEXT: add a3, a0, a2 ; RV64IZbb-NEXT: add a3, a0, a2
; RV64IZbb-NEXT: addi a0, zero, -1 ; RV64IZbb-NEXT: addi a0, zero, -1
; RV64IZbb-NEXT: slli a0, a0, 63 ; RV64IZbb-NEXT: slli a0, a0, 63
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; RV64IZbb-NEXT: ret ; RV64IZbb-NEXT: ret
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y); %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
ret i32 %tmp; ret i32 %tmp;
} }
define i64 @func2(i64 %x, i64 %y) nounwind { define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: func2: ; RV32I-LABEL: func2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a4, a0, a2 ; RV32I-NEXT: mv a6, a1
; RV32I-NEXT: sub a5, a1, a3 ; RV32I-NEXT: sltu a1, a0, a2
; RV32I-NEXT: sub t0, a5, a4 ; RV32I-NEXT: sub a5, a6, a3
; RV32I-NEXT: addi a6, zero, -1 ; RV32I-NEXT: sub t0, a5, a1
; RV32I-NEXT: addi a7, zero, 1 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a4, zero, 1 ; RV32I-NEXT: bgez t0, .LBB1_2
; RV32I-NEXT: beqz t0, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a4, a6, t0 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: addi a5, zero, 1 ; RV32I-NEXT: slti a7, t0, 0
; RV32I-NEXT: beqz a1, .LBB1_4 ; RV32I-NEXT: slti a4, a6, 0
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: xor a5, a4, a7
; RV32I-NEXT: slt a5, a6, a1 ; RV32I-NEXT: snez a5, a5
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: slti a3, a3, 0
; RV32I-NEXT: xor a1, a5, a4 ; RV32I-NEXT: xor a3, a4, a3
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: beqz a3, .LBB1_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: slt a7, a6, a3
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: xor a3, a5, a7
; RV32I-NEXT: snez a3, a3 ; RV32I-NEXT: snez a3, a3
; RV32I-NEXT: and a3, a3, a1 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: bnez a3, .LBB1_8 ; RV32I-NEXT: bnez a3, .LBB1_4
; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bltz t0, .LBB1_9
; RV32I-NEXT: j .LBB1_10
; RV32I-NEXT: .LBB1_8:
; RV32I-NEXT: srai a0, t0, 31
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez t0, .LBB1_10
; RV32I-NEXT: .LBB1_9:
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_10:
; RV32I-NEXT: beqz a3, .LBB1_12
; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_12:
; RV32I-NEXT: mv a1, t0 ; RV32I-NEXT: mv a1, t0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, t0, 31
; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func2: ; RV64I-LABEL: func2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sgtz a2, a1 ; RV64I-NEXT: sgtz a2, a1
; RV64I-NEXT: sub a1, a0, a1 ; RV64I-NEXT: sub a1, a0, a1
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: xor a2, a2, a0 ; RV64I-NEXT: xor a2, a2, a0
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bltz a1, .LBB1_3 ; RV64I-NEXT: bltz a1, .LBB1_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: beqz a2, .LBB1_4 ; RV64I-NEXT: beqz a2, .LBB1_4
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB1_3: ; RV64I-NEXT: .LBB1_3:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a2, .LBB1_2 ; RV64I-NEXT: bnez a2, .LBB1_2
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func2: ; RV32IZbb-LABEL: func2:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: sltu a4, a0, a2 ; RV32IZbb-NEXT: mv a6, a1
; RV32IZbb-NEXT: sub a5, a1, a3 ; RV32IZbb-NEXT: sltu a1, a0, a2
; RV32IZbb-NEXT: sub t0, a5, a4 ; RV32IZbb-NEXT: sub a5, a6, a3
; RV32IZbb-NEXT: addi a6, zero, -1 ; RV32IZbb-NEXT: sub t0, a5, a1
; RV32IZbb-NEXT: addi a7, zero, 1 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: addi a4, zero, 1 ; RV32IZbb-NEXT: bgez t0, .LBB1_2
; RV32IZbb-NEXT: beqz t0, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: slt a4, a6, t0 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: addi a5, zero, 1 ; RV32IZbb-NEXT: slti a7, t0, 0
; RV32IZbb-NEXT: beqz a1, .LBB1_4 ; RV32IZbb-NEXT: slti a4, a6, 0
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: xor a5, a4, a7
; RV32IZbb-NEXT: slt a5, a6, a1 ; RV32IZbb-NEXT: snez a5, a5
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: slti a3, a3, 0
; RV32IZbb-NEXT: xor a1, a5, a4 ; RV32IZbb-NEXT: xor a3, a4, a3
; RV32IZbb-NEXT: snez a1, a1
; RV32IZbb-NEXT: beqz a3, .LBB1_6
; RV32IZbb-NEXT: # %bb.5:
; RV32IZbb-NEXT: slt a7, a6, a3
; RV32IZbb-NEXT: .LBB1_6:
; RV32IZbb-NEXT: xor a3, a5, a7
; RV32IZbb-NEXT: snez a3, a3 ; RV32IZbb-NEXT: snez a3, a3
; RV32IZbb-NEXT: and a3, a3, a1 ; RV32IZbb-NEXT: and a3, a3, a5
; RV32IZbb-NEXT: bnez a3, .LBB1_8 ; RV32IZbb-NEXT: bnez a3, .LBB1_4
; RV32IZbb-NEXT: # %bb.7: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: sub a0, a0, a2 ; RV32IZbb-NEXT: sub a0, a0, a2
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bltz t0, .LBB1_9
; RV32IZbb-NEXT: j .LBB1_10
; RV32IZbb-NEXT: .LBB1_8:
; RV32IZbb-NEXT: srai a0, t0, 31
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez t0, .LBB1_10
; RV32IZbb-NEXT: .LBB1_9:
; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_10:
; RV32IZbb-NEXT: beqz a3, .LBB1_12
; RV32IZbb-NEXT: # %bb.11:
; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_12:
; RV32IZbb-NEXT: mv a1, t0 ; RV32IZbb-NEXT: mv a1, t0
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, t0, 31
; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func2: ; RV64IZbb-LABEL: func2:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sgtz a2, a1 ; RV64IZbb-NEXT: sgtz a2, a1
; RV64IZbb-NEXT: sub a1, a0, a1 ; RV64IZbb-NEXT: sub a1, a0, a1
; RV64IZbb-NEXT: slt a0, a1, a0 ; RV64IZbb-NEXT: slt a0, a1, a0
; RV64IZbb-NEXT: xor a2, a2, a0 ; RV64IZbb-NEXT: xor a2, a2, a0
; RV64IZbb-NEXT: addi a0, zero, -1 ; RV64IZbb-NEXT: addi a0, zero, -1
▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; RV64IZbb-NEXT: ret
%a = mul i32 %y, %z %a = mul i32 %y, %z
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a) %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
ret i32 %tmp ret i32 %tmp
} }
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32I-LABEL: func64: ; RV32I-LABEL: func64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: sltu a2, a0, a4 ; RV32I-NEXT: mv a6, a1
; RV32I-NEXT: sub a3, a1, a5 ; RV32I-NEXT: sltu a1, a0, a4
; RV32I-NEXT: sub t0, a3, a2 ; RV32I-NEXT: sub a3, a6, a5
; RV32I-NEXT: addi a6, zero, -1 ; RV32I-NEXT: sub t0, a3, a1
; RV32I-NEXT: addi a7, zero, 1 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: bgez t0, .LBB1_2
; RV32I-NEXT: beqz t0, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a6, t0 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: addi a3, zero, 1 ; RV32I-NEXT: slti a7, t0, 0
; RV32I-NEXT: beqz a1, .LBB1_4 ; RV32I-NEXT: slti a2, a6, 0
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: xor a3, a2, a7
; RV32I-NEXT: slt a3, a6, a1 ; RV32I-NEXT: snez a3, a3
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: slti a5, a5, 0
; RV32I-NEXT: xor a1, a3, a2 ; RV32I-NEXT: xor a2, a2, a5
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: beqz a5, .LBB1_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: slt a7, a6, a5
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: xor a2, a3, a7
; RV32I-NEXT: snez a2, a2 ; RV32I-NEXT: snez a2, a2
; RV32I-NEXT: and a3, a2, a1 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: bnez a3, .LBB1_8 ; RV32I-NEXT: bnez a2, .LBB1_4
; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sub a0, a0, a4 ; RV32I-NEXT: sub a0, a0, a4
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bltz t0, .LBB1_9
; RV32I-NEXT: j .LBB1_10
; RV32I-NEXT: .LBB1_8:
; RV32I-NEXT: srai a0, t0, 31
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez t0, .LBB1_10
; RV32I-NEXT: .LBB1_9:
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: .LBB1_10:
; RV32I-NEXT: beqz a3, .LBB1_12
; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_12:
; RV32I-NEXT: mv a1, t0 ; RV32I-NEXT: mv a1, t0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: srai a0, t0, 31
; RV32I-NEXT: ret
; ;
; RV64I-LABEL: func64: ; RV64I-LABEL: func64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sgtz a3, a2 ; RV64I-NEXT: sgtz a3, a2
; RV64I-NEXT: sub a1, a0, a2 ; RV64I-NEXT: sub a1, a0, a2
; RV64I-NEXT: slt a0, a1, a0 ; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: xor a2, a3, a0 ; RV64I-NEXT: xor a2, a3, a0
; RV64I-NEXT: addi a0, zero, -1 ; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bltz a1, .LBB1_3 ; RV64I-NEXT: bltz a1, .LBB1_3
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: beqz a2, .LBB1_4 ; RV64I-NEXT: beqz a2, .LBB1_4
; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB1_3: ; RV64I-NEXT: .LBB1_3:
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a2, .LBB1_2 ; RV64I-NEXT: bnez a2, .LBB1_2
; RV64I-NEXT: .LBB1_4: ; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32IZbb-LABEL: func64: ; RV32IZbb-LABEL: func64:
; RV32IZbb: # %bb.0: ; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: sltu a2, a0, a4 ; RV32IZbb-NEXT: mv a6, a1
; RV32IZbb-NEXT: sub a3, a1, a5 ; RV32IZbb-NEXT: sltu a1, a0, a4
; RV32IZbb-NEXT: sub t0, a3, a2 ; RV32IZbb-NEXT: sub a3, a6, a5
; RV32IZbb-NEXT: addi a6, zero, -1 ; RV32IZbb-NEXT: sub t0, a3, a1
; RV32IZbb-NEXT: addi a7, zero, 1 ; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: addi a2, zero, 1 ; RV32IZbb-NEXT: bgez t0, .LBB1_2
; RV32IZbb-NEXT: beqz t0, .LBB1_2
; RV32IZbb-NEXT: # %bb.1: ; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: slt a2, a6, t0 ; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: .LBB1_2:
; RV32IZbb-NEXT: addi a3, zero, 1 ; RV32IZbb-NEXT: slti a7, t0, 0
; RV32IZbb-NEXT: beqz a1, .LBB1_4 ; RV32IZbb-NEXT: slti a2, a6, 0
; RV32IZbb-NEXT: # %bb.3: ; RV32IZbb-NEXT: xor a3, a2, a7
; RV32IZbb-NEXT: slt a3, a6, a1 ; RV32IZbb-NEXT: snez a3, a3
; RV32IZbb-NEXT: .LBB1_4: ; RV32IZbb-NEXT: slti a5, a5, 0
; RV32IZbb-NEXT: xor a1, a3, a2 ; RV32IZbb-NEXT: xor a2, a2, a5
; RV32IZbb-NEXT: snez a1, a1
; RV32IZbb-NEXT: beqz a5, .LBB1_6
; RV32IZbb-NEXT: # %bb.5:
; RV32IZbb-NEXT: slt a7, a6, a5
; RV32IZbb-NEXT: .LBB1_6:
; RV32IZbb-NEXT: xor a2, a3, a7
; RV32IZbb-NEXT: snez a2, a2 ; RV32IZbb-NEXT: snez a2, a2
; RV32IZbb-NEXT: and a3, a2, a1 ; RV32IZbb-NEXT: and a2, a2, a3
; RV32IZbb-NEXT: bnez a3, .LBB1_8 ; RV32IZbb-NEXT: bnez a2, .LBB1_4
; RV32IZbb-NEXT: # %bb.7: ; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: sub a0, a0, a4 ; RV32IZbb-NEXT: sub a0, a0, a4
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bltz t0, .LBB1_9
; RV32IZbb-NEXT: j .LBB1_10
; RV32IZbb-NEXT: .LBB1_8:
; RV32IZbb-NEXT: srai a0, t0, 31
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez t0, .LBB1_10
; RV32IZbb-NEXT: .LBB1_9:
; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: .LBB1_10:
; RV32IZbb-NEXT: beqz a3, .LBB1_12
; RV32IZbb-NEXT: # %bb.11:
; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_12:
; RV32IZbb-NEXT: mv a1, t0 ; RV32IZbb-NEXT: mv a1, t0
; RV32IZbb-NEXT: ret ; RV32IZbb-NEXT: ret
; RV32IZbb-NEXT: .LBB1_4:
; RV32IZbb-NEXT: srai a0, t0, 31
; RV32IZbb-NEXT: ret
; ;
; RV64IZbb-LABEL: func64: ; RV64IZbb-LABEL: func64:
; RV64IZbb: # %bb.0: ; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sgtz a3, a2 ; RV64IZbb-NEXT: sgtz a3, a2
; RV64IZbb-NEXT: sub a1, a0, a2 ; RV64IZbb-NEXT: sub a1, a0, a2
; RV64IZbb-NEXT: slt a0, a1, a0 ; RV64IZbb-NEXT: slt a0, a1, a0
; RV64IZbb-NEXT: xor a2, a3, a0 ; RV64IZbb-NEXT: xor a2, a3, a0
; RV64IZbb-NEXT: addi a0, zero, -1 ; RV64IZbb-NEXT: addi a0, zero, -1
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/xaluo.ll

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Linesentry:
store i32 %val, i32* %res store i32 %val, i32* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: saddo1.i64: ; RV32-LABEL: saddo1.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a5, a1, a3 ; RV32-NEXT: add a5, a1, a3
; RV32-NEXT: add t0, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, t0, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a5, a5, a0 ; RV32-NEXT: add a5, a5, a0
; RV32-NEXT: addi a6, zero, -1 ; RV32-NEXT: slti a0, a5, 0
; RV32-NEXT: addi a7, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a2, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a5, .LBB4_2 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a3, a3, 0
; RV32-NEXT: slt a2, a6, a5 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: .LBB4_2: # %entry ; RV32-NEXT: seqz a1, a1
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a1, .LBB4_4 ; RV32-NEXT: sw a2, 0(a4)
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a0, a6, a1
; RV32-NEXT: .LBB4_4: # %entry
; RV32-NEXT: xor a1, a0, a2
; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB4_6
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a7, a6, a3
; RV32-NEXT: .LBB4_6: # %entry
; RV32-NEXT: xor a0, a0, a7
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: sw t0, 0(a4)
; RV32-NEXT: sw a5, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo1.i64: ; RV64-LABEL: saddo1.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a3, a0, a1 ; RV64-NEXT: add a3, a0, a1
; RV64-NEXT: slt a0, a3, a0 ; RV64-NEXT: slt a0, a3, a0
; RV64-NEXT: slti a1, a1, 0 ; RV64-NEXT: slti a1, a1, 0
; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: xor a0, a1, a0
; RV64-NEXT: sd a3, 0(a2) ; RV64-NEXT: sd a3, 0(a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64* %res store i64 %val, i64* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) { define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
; RV32-LABEL: saddo2.i64: ; RV32-LABEL: saddo2.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 4 ; RV32-NEXT: addi a3, zero, -1
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: slt a3, a3, a1
; RV32-NEXT: add a4, a1, a0 ; RV32-NEXT: addi a4, a0, 4
; RV32-NEXT: addi a6, zero, -1 ; RV32-NEXT: sltu a0, a4, a0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: add a5, a1, a0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: slti a0, a5, 0
; RV32-NEXT: beqz a4, .LBB5_2 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: slt a5, a6, a4
; RV32-NEXT: .LBB5_2: # %entry
; RV32-NEXT: beqz a1, .LBB5_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a0, a6, a1
; RV32-NEXT: .LBB5_4: # %entry
; RV32-NEXT: xor a1, a0, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: and a0, a3, a0
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a5, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo2.i64: ; RV64-LABEL: saddo2.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, 4 ; RV64-NEXT: addi a2, a0, 4
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4) %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64* %res store i64 %val, i64* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) { define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
; RV32-LABEL: saddo3.i64: ; RV32-LABEL: saddo3.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, -4 ; RV32-NEXT: addi a3, a0, -4
; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: sltu a0, a3, a0
; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: addi a4, a0, -1 ; RV32-NEXT: addi a4, a0, -1
; RV32-NEXT: addi a6, zero, -1 ; RV32-NEXT: slti a0, a4, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a4, .LBB6_2 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: slt a5, a6, a4
; RV32-NEXT: .LBB6_2: # %entry
; RV32-NEXT: beqz a1, .LBB6_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a0, a6, a1
; RV32-NEXT: .LBB6_4: # %entry
; RV32-NEXT: xor a1, a0, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo3.i64: ; RV64-LABEL: saddo3.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi a2, a0, -4 ; RV64-NEXT: addi a2, a0, -4
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Linesentry:
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: ssubo.i64: ; RV32-LABEL: ssubo.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a6, a0, a2 ; RV32-NEXT: sltu a6, a0, a2
; RV32-NEXT: sub a5, a1, a3 ; RV32-NEXT: sub a5, a1, a3
; RV32-NEXT: sub t0, a5, a6 ; RV32-NEXT: sub a7, a5, a6
; RV32-NEXT: addi a7, zero, -1 ; RV32-NEXT: slti a6, a7, 0
; RV32-NEXT: addi a6, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi t1, zero, 1 ; RV32-NEXT: xor a5, a1, a6
; RV32-NEXT: beqz t0, .LBB11_2 ; RV32-NEXT: snez a5, a5
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a3, a3, 0
; RV32-NEXT: slt t1, a7, t0 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: .LBB11_2: # %entry
; RV32-NEXT: addi a5, zero, 1
; RV32-NEXT: beqz a1, .LBB11_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a5, a7, a1
; RV32-NEXT: .LBB11_4: # %entry
; RV32-NEXT: xor a1, a5, t1
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB11_6 ; RV32-NEXT: and a1, a1, a5
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a6, a7, a3
; RV32-NEXT: .LBB11_6: # %entry
; RV32-NEXT: xor a3, a5, a6
; RV32-NEXT: snez a3, a3
; RV32-NEXT: and a1, a3, a1
; RV32-NEXT: sub a0, a0, a2 ; RV32-NEXT: sub a0, a0, a2
; RV32-NEXT: sw a0, 0(a4) ; RV32-NEXT: sw a0, 0(a4)
; RV32-NEXT: sw t0, 4(a4) ; RV32-NEXT: sw a7, 4(a4)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.i64: ; RV64-LABEL: ssubo.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a3, a1 ; RV64-NEXT: sgtz a3, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
▲ Show 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
} }
define i64 @saddo.select.i64(i64 %v1, i64 %v2) { define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.select.i64: ; RV32-LABEL: saddo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a5, a0, a2 ; RV32-NEXT: add a5, a0, a2
; RV32-NEXT: sltu a5, a5, a0 ; RV32-NEXT: sltu a5, a5, a0
; RV32-NEXT: add a5, a4, a5 ; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: addi a6, zero, -1 ; RV32-NEXT: slti a4, a4, 0
; RV32-NEXT: addi a7, zero, 1 ; RV32-NEXT: slti a5, a1, 0
; RV32-NEXT: addi a4, zero, 1
; RV32-NEXT: beqz a5, .LBB24_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: slt a4, a6, a5
; RV32-NEXT: .LBB24_2: # %entry
; RV32-NEXT: addi a5, zero, 1
; RV32-NEXT: beqz a1, .LBB24_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a5, a6, a1
; RV32-NEXT: .LBB24_4: # %entry
; RV32-NEXT: xor a4, a5, a4 ; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: snez a4, a4 ; RV32-NEXT: snez a6, a4
; RV32-NEXT: beqz a3, .LBB24_6 ; RV32-NEXT: slti a4, a3, 0
; RV32-NEXT: # %bb.5: # %entry ; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: slt a7, a6, a3 ; RV32-NEXT: seqz a4, a4
; RV32-NEXT: .LBB24_6: # %entry ; RV32-NEXT: and a4, a4, a6
; RV32-NEXT: xor a5, a5, a7 ; RV32-NEXT: bnez a4, .LBB24_2
; RV32-NEXT: seqz a5, a5 ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: bnez a4, .LBB24_8
; RV32-NEXT: # %bb.7: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB24_8: # %entry ; RV32-NEXT: .LBB24_2: # %entry
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.select.i64: ; RV64-LABEL: saddo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a2, a2, a0 ; RV64-NEXT: slt a2, a2, a0
; RV64-NEXT: slti a3, a1, 0 ; RV64-NEXT: slti a3, a1, 0
; RV64-NEXT: xor a2, a3, a2 ; RV64-NEXT: xor a2, a3, a2
Show All 10 Lines
} }
define i1 @saddo.not.i64(i64 %v1, i64 %v2) { define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.not.i64: ; RV32-LABEL: saddo.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a2, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a4, a4, a0 ; RV32-NEXT: add a0, a4, a0
; RV32-NEXT: addi a2, zero, -1 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a4, .LBB25_2 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: slt a5, a2, a4 ; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: .LBB25_2: # %entry ; RV32-NEXT: seqz a1, a1
; RV32-NEXT: addi a4, zero, 1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a1, .LBB25_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a4, a2, a1
; RV32-NEXT: .LBB25_4: # %entry
; RV32-NEXT: xor a1, a4, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB25_6
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a0, a2, a3
; RV32-NEXT: .LBB25_6: # %entry
; RV32-NEXT: xor a0, a4, a0
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.not.i64: ; RV64-LABEL: saddo.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: slti a1, a1, 0 ; RV64-NEXT: slti a1, a1, 0
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Linesentry:
ret i1 %ret ret i1 %ret
} }
define i64 @ssubo.select.i64(i64 %v1, i64 %v2) { define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssubo.select.i64: ; RV32-LABEL: ssubo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a4, a0, a2 ; RV32-NEXT: sltu a4, a0, a2
; RV32-NEXT: sub a5, a1, a3 ; RV32-NEXT: sub a5, a1, a3
; RV32-NEXT: sub a5, a5, a4 ; RV32-NEXT: sub a4, a5, a4
; RV32-NEXT: addi a6, zero, -1 ; RV32-NEXT: slti a4, a4, 0
; RV32-NEXT: addi a7, zero, 1 ; RV32-NEXT: slti a5, a1, 0
; RV32-NEXT: addi a4, zero, 1 ; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: beqz a5, .LBB32_2 ; RV32-NEXT: snez a6, a4
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a4, a3, 0
; RV32-NEXT: slt a4, a6, a5
; RV32-NEXT: .LBB32_2: # %entry
; RV32-NEXT: addi a5, zero, 1
; RV32-NEXT: beqz a1, .LBB32_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a5, a6, a1
; RV32-NEXT: .LBB32_4: # %entry
; RV32-NEXT: xor a4, a5, a4 ; RV32-NEXT: xor a4, a5, a4
; RV32-NEXT: snez a4, a4 ; RV32-NEXT: snez a4, a4
; RV32-NEXT: beqz a3, .LBB32_6 ; RV32-NEXT: and a4, a4, a6
; RV32-NEXT: # %bb.5: # %entry ; RV32-NEXT: bnez a4, .LBB32_2
; RV32-NEXT: slt a7, a6, a3 ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: .LBB32_6: # %entry
; RV32-NEXT: xor a5, a5, a7
; RV32-NEXT: snez a5, a5
; RV32-NEXT: and a4, a5, a4
; RV32-NEXT: bnez a4, .LBB32_8
; RV32-NEXT: # %bb.7: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB32_8: # %entry ; RV32-NEXT: .LBB32_2: # %entry
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.select.i64: ; RV64-LABEL: ssubo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a2, a1 ; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a3, a0, a1 ; RV64-NEXT: sub a3, a0, a1
; RV64-NEXT: slt a3, a3, a0 ; RV64-NEXT: slt a3, a3, a0
; RV64-NEXT: xor a2, a2, a3 ; RV64-NEXT: xor a2, a2, a3
Show All 9 Linesentry:
ret i64 %ret ret i64 %ret
} }
define i1 @ssub.not.i64(i64 %v1, i64 %v2) { define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssub.not.i64: ; RV32-LABEL: ssub.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: sub a2, a1, a3 ; RV32-NEXT: sub a2, a1, a3
; RV32-NEXT: sub a4, a2, a0 ; RV32-NEXT: sub a0, a2, a0
; RV32-NEXT: addi a2, zero, -1 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a4, .LBB33_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: slt a5, a2, a4
; RV32-NEXT: .LBB33_2: # %entry
; RV32-NEXT: addi a4, zero, 1
; RV32-NEXT: beqz a1, .LBB33_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a4, a2, a1
; RV32-NEXT: .LBB33_4: # %entry
; RV32-NEXT: xor a1, a4, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB33_6
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a0, a2, a3
; RV32-NEXT: .LBB33_6: # %entry
; RV32-NEXT: xor a0, a4, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: snez a1, a1
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub.not.i64: ; RV64-LABEL: ssub.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a2, a1 ; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
▲ Show 20 Lines • Show All 471 Lines • ▼ Show 20 Lines
} }
define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: saddo.br.i64: ; RV32-LABEL: saddo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a4, a1, a3 ; RV32-NEXT: add a4, a1, a3
; RV32-NEXT: add a2, a0, a2 ; RV32-NEXT: add a2, a0, a2
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a4, a4, a0 ; RV32-NEXT: add a0, a4, a0
; RV32-NEXT: addi a2, zero, -1 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a4, .LBB47_2 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: slt a5, a2, a4 ; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: .LBB47_2: # %entry ; RV32-NEXT: seqz a1, a1
; RV32-NEXT: addi a4, zero, 1 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a1, .LBB47_4 ; RV32-NEXT: beqz a0, .LBB47_2
; RV32-NEXT: # %bb.3: # %entry ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: slt a4, a2, a1
; RV32-NEXT: .LBB47_4: # %entry
; RV32-NEXT: xor a1, a4, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB47_6
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a0, a2, a3
; RV32-NEXT: .LBB47_6: # %entry
; RV32-NEXT: xor a0, a4, a0
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: beqz a0, .LBB47_8
; RV32-NEXT: # %bb.7: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB47_8: # %continue ; RV32-NEXT: .LBB47_2: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: saddo.br.i64: ; RV64-LABEL: saddo.br.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: add a2, a0, a1
; RV64-NEXT: slt a0, a2, a0 ; RV64-NEXT: slt a0, a2, a0
; RV64-NEXT: slti a1, a1, 0 ; RV64-NEXT: slti a1, a1, 0
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ret i1 true ret i1 true
} }
define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: ssubo.br.i64: ; RV32-LABEL: ssubo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: sub a2, a1, a3 ; RV32-NEXT: sub a2, a1, a3
; RV32-NEXT: sub a4, a2, a0 ; RV32-NEXT: sub a0, a2, a0
; RV32-NEXT: addi a2, zero, -1 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a5, zero, 1 ; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: beqz a4, .LBB51_2
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: slt a5, a2, a4
; RV32-NEXT: .LBB51_2: # %entry
; RV32-NEXT: addi a4, zero, 1
; RV32-NEXT: beqz a1, .LBB51_4
; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: slt a4, a2, a1
; RV32-NEXT: .LBB51_4: # %entry
; RV32-NEXT: xor a1, a4, a5
; RV32-NEXT: snez a1, a1
; RV32-NEXT: beqz a3, .LBB51_6
; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: slt a0, a2, a3
; RV32-NEXT: .LBB51_6: # %entry
; RV32-NEXT: xor a0, a4, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: slti a2, a3, 0
; RV32-NEXT: beqz a0, .LBB51_8 ; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: # %bb.7: # %overflow ; RV32-NEXT: snez a1, a1
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: beqz a0, .LBB51_2
; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB51_8: # %continue ; RV32-NEXT: .LBB51_2: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.br.i64: ; RV64-LABEL: ssubo.br.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a2, a1 ; RV64-NEXT: sgtz a2, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
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} }
define zeroext i1 @smulo2.br.i64(i64 %v1) { define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV32-LABEL: smulo2.br.i64: ; RV32-LABEL: smulo2.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: add a2, a0, a0 ; RV32-NEXT: add a2, a0, a0
; RV32-NEXT: sltu a0, a2, a0 ; RV32-NEXT: sltu a0, a2, a0
; RV32-NEXT: add a2, a1, a1 ; RV32-NEXT: add a2, a1, a1
; RV32-NEXT: add a4, a2, a0 ; RV32-NEXT: add a0, a2, a0
; RV32-NEXT: addi a2, zero, -1 ; RV32-NEXT: slti a0, a0, 0
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: addi a3, zero, 1 ; RV32-NEXT: beq a1, a0, .LBB56_2
; RV32-NEXT: bnez a4, .LBB56_4 ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: bnez a1, .LBB56_5
; RV32-NEXT: .LBB56_2: # %entry
; RV32-NEXT: beq a0, a3, .LBB56_6
; RV32-NEXT: .LBB56_3: # %overflow
; RV32-NEXT: mv a0, zero ; RV32-NEXT: mv a0, zero
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB56_4: # %entry ; RV32-NEXT: .LBB56_2: # %continue
; RV32-NEXT: slt a3, a2, a4
; RV32-NEXT: beqz a1, .LBB56_2
; RV32-NEXT: .LBB56_5: # %entry
; RV32-NEXT: slt a0, a2, a1
; RV32-NEXT: bne a0, a3, .LBB56_3
; RV32-NEXT: .LBB56_6: # %continue
; RV32-NEXT: addi a0, zero, 1 ; RV32-NEXT: addi a0, zero, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo2.br.i64: ; RV64-LABEL: smulo2.br.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: add a1, a0, a0 ; RV64-NEXT: add a1, a0, a0
; RV64-NEXT: slt a1, a1, a0 ; RV64-NEXT: slt a1, a1, a0
; RV64-NEXT: slti a0, a0, 0 ; RV64-NEXT: slti a0, a0, 0
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llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll

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entry: entry:
%0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2) %0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: sadd_int64_t: ; CHECK-LABEL: sadd_int64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: vmov lr, s6 ; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vmov r5, s4 ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov r6, s0 ; CHECK-NEXT: vmov r6, s4
; CHECK-NEXT: cmp.w r0, #-1 ; CHECK-NEXT: vmov r7, s0
; CHECK-NEXT: cset r1, gt ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp.w r2, #-1 ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: cset r3, gt ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r3, mi
; CHECK-NEXT: cmp r3, r1 ; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: cset r12, eq ; CHECK-NEXT: cset r12, eq
; CHECK-NEXT: adds.w r1, r1, lr ; CHECK-NEXT: adds.w r1, r1, lr
; CHECK-NEXT: adcs r0, r2 ; CHECK-NEXT: adcs.w lr, r2, r0
; CHECK-NEXT: cmp.w r0, #-1 ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cset r2, gt
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: and.w r2, r2, r12
; CHECK-NEXT: ands r12, r2, #1
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r1, r0, #31
; CHECK-NEXT: cmp.w r3, #-1
; CHECK-NEXT: cset lr, gt
; CHECK-NEXT: cmp.w r2, #-1
; CHECK-NEXT: cset r4, gt
; CHECK-NEXT: cmp r4, lr
; CHECK-NEXT: cset lr, eq
; CHECK-NEXT: adds r5, r5, r6
; CHECK-NEXT: adcs r2, r3
; CHECK-NEXT: mvn r6, #-2147483648
; CHECK-NEXT: cmp.w r2, #-1
; CHECK-NEXT: cset r3, gt
; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: cset r3, ne
; CHECK-NEXT: and.w r3, r3, lr ; CHECK-NEXT: and.w r3, r3, r12
; CHECK-NEXT: ands r3, r3, #1 ; CHECK-NEXT: ands r12, r3, #1
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r5, r2, #31 ; CHECK-NEXT: asrne.w r1, lr, #31
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q0[2], q0[0], r5, r1
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: tst.w r1, #1
; CHECK-NEXT: cinv r1, r6, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r1, r0, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: tst.w r1, #1
; CHECK-NEXT: cinv r1, r6, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r1, r1, r2, ne ; CHECK-NEXT: cset r0, mi
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: cset r5, mi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: adds r6, r6, r7
; CHECK-NEXT: adcs r3, r4
; CHECK-NEXT: cset r4, mi
; CHECK-NEXT: cmp r5, r4
; CHECK-NEXT: cset r5, ne
; CHECK-NEXT: ands r0, r5
; CHECK-NEXT: ands r0, r0, #1
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r6, r3, #31
; CHECK-NEXT: vmov q0[2], q0[0], r6, r1
; CHECK-NEXT: mvn r1, #-2147483648
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: cinv r2, r1, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r2, r2, lr, ne
; CHECK-NEXT: tst.w r4, #1
; CHECK-NEXT: cinv r1, r1, eq
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, r1, r3, ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry: entry:
%0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2) %0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: uadd_int8_t: ; CHECK-LABEL: uadd_int8_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2) %0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: ssub_int64_t: ; CHECK-LABEL: ssub_int64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: vmov lr, s6 ; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vmov r5, s4 ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov r6, s0 ; CHECK-NEXT: vmov r6, s4
; CHECK-NEXT: cmp.w r0, #-1 ; CHECK-NEXT: vmov r7, s0
; CHECK-NEXT: cset r1, gt ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp.w r2, #-1 ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: cset r3, gt ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r3, mi
; CHECK-NEXT: cmp r3, r1 ; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: cset r12, ne ; CHECK-NEXT: cset r12, ne
; CHECK-NEXT: subs.w r1, r1, lr ; CHECK-NEXT: subs.w r1, r1, lr
; CHECK-NEXT: sbc.w r0, r2, r0 ; CHECK-NEXT: sbcs.w lr, r2, r0
; CHECK-NEXT: cmp.w r0, #-1 ; CHECK-NEXT: cset r2, mi
; CHECK-NEXT: cset r2, gt
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: and.w r2, r2, r12
; CHECK-NEXT: ands r12, r2, #1
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r1, r0, #31
; CHECK-NEXT: cmp.w r3, #-1
; CHECK-NEXT: cset lr, gt
; CHECK-NEXT: cmp.w r2, #-1
; CHECK-NEXT: cset r4, gt
; CHECK-NEXT: cmp r4, lr
; CHECK-NEXT: cset lr, ne
; CHECK-NEXT: subs r5, r6, r5
; CHECK-NEXT: sbcs r2, r3
; CHECK-NEXT: mvn r6, #-2147483648
; CHECK-NEXT: cmp.w r2, #-1
; CHECK-NEXT: cset r3, gt
; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r3, ne ; CHECK-NEXT: cset r3, ne
; CHECK-NEXT: and.w r3, r3, lr ; CHECK-NEXT: and.w r3, r3, r12
; CHECK-NEXT: ands r3, r3, #1 ; CHECK-NEXT: ands r12, r3, #1
; CHECK-NEXT: vmov r3, s5
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r5, r2, #31 ; CHECK-NEXT: asrne.w r1, lr, #31
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q0[2], q0[0], r5, r1
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: tst.w r1, #1
; CHECK-NEXT: cinv r1, r6, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r1, r0, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: tst.w r1, #1
; CHECK-NEXT: cinv r1, r6, eq
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r1, r1, r2, ne ; CHECK-NEXT: cset r0, mi
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: cset r5, mi
; CHECK-NEXT: cmp r5, r0
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: subs r6, r7, r6
; CHECK-NEXT: sbcs.w r3, r4, r3
; CHECK-NEXT: cset r4, mi
; CHECK-NEXT: cmp r5, r4
; CHECK-NEXT: cset r5, ne
; CHECK-NEXT: ands r0, r5
; CHECK-NEXT: ands r0, r0, #1
; CHECK-NEXT: it ne
; CHECK-NEXT: asrne r6, r3, #31
; CHECK-NEXT: vmov q0[2], q0[0], r6, r1
; CHECK-NEXT: mvn r1, #-2147483648
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: cinv r2, r1, eq
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r2, r2, lr, ne
; CHECK-NEXT: tst.w r4, #1
; CHECK-NEXT: cinv r1, r1, eq
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csel r0, r1, r3, ne
; CHECK-NEXT: vmov q0[3], q0[1], r0, r2
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry: entry:
%0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2) %0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: usub_int8_t: ; CHECK-LABEL: usub_int8_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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