[KnownBits][RISCV] Improve known bits for srem.

[craig.topper]

Summary

The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.

[craig.topper]

Improve the comment about why this is valid.

[craig.topper]

Improve the comment again

[RKSimon]

llvm/lib/Support/KnownBits.cpp

480

I don't suppose this lets us make the KnownBitsTest exhaustive srem test more accurate? Most binops we still only checks for common subset bits when we might be able to check for exact equality now.

[craig.topper]

llvm/lib/Support/KnownBits.cpp

480

I tried equality. It failed for both zeros and ones. We don't infer ones unless all bits of the RHS are known. For zeros we're only calculating an upper bound on the result.

[RKSimon]

LGTM

llvm/lib/Support/KnownBits.cpp

480

Fair enough, thanks for trying.

llvm/lib/Support/KnownBits.cpp

if (RHS.isConstant() && RHS.getConstant().isPowerOf2()) {
     // If the first operand is negative and not all low bits are zero, then
     // the upper bits are all one.
     if (LHS.isNegative() && LowBits.intersects(LHS.One))
       Known.One |= ~LowBits;
     return Known;
   }
 
   // The sign bit is the LHS's sign bit, except when the result of the
-  // remainder is zero. If it's known zero, our sign bit is also zero.
-  if (LHS.isNonNegative())
-    Known.makeNonNegative();
+  // remainder is zero. The magnitude of the result should be less than or
+  // equal to the magnitude of the LHS. Therefore any leading zeros that exist
+  // in the left hand side must also exist in the result.
+  Known.Zero.setHighBits(LHS.countMinLeadingZeros());
   return Known;
 }
 
 KnownBits &KnownBits::operator&=(const KnownBits &RHS) {
   // Result bit is 0 if either operand bit is 0.
   Zero |= RHS.Zero;
   // Result bit is 1 if both operand bits are 1.
   One &= RHS.One;

llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

; RV64IM-NEXT:    ret
   %1 = srem i16 %a, %b
   ret i16 %1
 }
 
 define signext i32 @sext_i32_remw_zext_sext_i16(i16 zeroext %0, i16 signext %1) nounwind {
 ; RV64IM-LABEL: sext_i32_remw_zext_sext_i16:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    rem a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %3 = sext i16 %1 to i32
   %4 = zext i16 %0 to i32
   %5 = srem i32 %4, %3
   ret i32 %5
 }
 
 define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b) nounwind {