[RISCV] Fix bugs in pseudo instructions for masked segment load.

[HsiangKai]

Summary

For masked segment load, the destination register should not overlap with mask register. It could not be V0.

In the original implementation, there is no segment load/store register class without V0. In this patch, I added these register classes and modify GetVRegNoV0 to get the correct one.

[rogfer01]

Thanks @HsiangKai. LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

495–506

Now that we're here, is it possible to replace !eq(1, 1) with true?

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

495–506

I will do it. Thanks.

[foad]

I'm seeing:

$ ninja -C ~/llvm-release/ check-llvm-codegen-amdgpu
ninja: Entering directory `/home/jayfoad2/llvm-release/'
[125/1115] Building RISCVGenAsmMatcher.inc...
FAILED: lib/Target/RISCV/RISCVGenAsmMatcher.inc 
cd /home/jayfoad2/llvm-release && /home/jayfoad2/llvm-release/bin/llvm-tblgen -gen-asm-matcher -I /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV -I/home/jayfoad2/llvm-release/include -I/home/jayfoad2/git/llvm-project/llvm/include -I /home/jayfoad2/git/llvm-project/llvm/lib/Target /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o lib/Target/RISCV/RISCVGenAsmMatcher.inc -d lib/Target/RISCV/RISCVGenAsmMatcher.inc.d
Included from /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCV.td:234:
Included from /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:1262:
Included from /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1166:
Included from /home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4439:
/home/jayfoad2/git/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:388:13: error: Value specified for template argument 'VPatUSLoadStoreWholeVRSDNode::type' (#0) is of type ValueType; expected type LLVMType: vti.Vector
  defm "" : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.SEW, vti.LMul,
            ^
[150/1042] Building AMDGPUGenInstrInfo.inc...
ninja: build stopped: subcommand failed.

Could this be caused by your patch? Or maybe it's D96416?

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 // overlap the source mask register (v0), unless the destination vector register
 // is being written with a mask value (e.g., comparisons) or the scalar result
 // of a reduction.
 class GetVRegNoV0<VReg VRegClass> {
   VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
                  !eq(VRegClass, VRM2) : VRM2NoV0,
                  !eq(VRegClass, VRM4) : VRM4NoV0,
                  !eq(VRegClass, VRM8) : VRM8NoV0,
-                 !eq(1, 1) : VRegClass);
+                 !eq(VRegClass, VRN2M1) : VRN2M1NoV0,
+                 !eq(VRegClass, VRN2M2) : VRN2M2NoV0,
+                 !eq(VRegClass, VRN2M4) : VRN2M4NoV0,
+                 !eq(VRegClass, VRN3M1) : VRN3M1NoV0,
+                 !eq(VRegClass, VRN3M2) : VRN3M2NoV0,
+                 !eq(VRegClass, VRN4M1) : VRN4M1NoV0,
+                 !eq(VRegClass, VRN4M2) : VRN4M2NoV0,
+                 !eq(VRegClass, VRN5M1) : VRN5M1NoV0,
+                 !eq(VRegClass, VRN6M1) : VRN6M1NoV0,
+                 !eq(VRegClass, VRN7M1) : VRN7M1NoV0,
+                 !eq(VRegClass, VRN8M1) : VRN8M1NoV0,
+                 true : VRegClass);
 }
 
 // Join strings in list using separator and ignoring empty elements
 class Join<list<string> strings, string separator> {
   string ret = !foldl(!head(strings), !tail(strings), a, b,
                       !cond(
                         !and(!empty(a), !empty(b)) : "",
                         !empty(a) : b,

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

!foldl([]<int>,
               !listconcat(L,
                           !if(!and(
                                 !le(!mul(index, lmul), !mul(i, lmul)),
                                 !le(!mul(i, lmul),
                                     !sub(!add(32, !mul(index, lmul)), !mul(nf, lmul)))
                               ), [!mul(i, lmul)], [])));
 }
 
-class VRegList<list<dag> LIn, int start, int nf, int lmul> {
+class VRegList<list<dag> LIn, int start, int nf, int lmul, bit NoV0> {
   list<dag> L =
     !if(!ge(start, nf),
         LIn,
         !listconcat(
           [!dag(add,
-                !foreach(i, IndexSet<start, nf, lmul>.R,
-                         !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2",
-                                                         !eq(lmul, 4): "M4",
-                                                         true: ""))),
-                !listsplat("", !size(IndexSet<start, nf, lmul>.R)))],
-          VRegList<LIn, !add(start, 1), nf, lmul>.L));
+                !foreach(i,
+                  !if(NoV0,
+                    !tail(IndexSet<start, nf, lmul>.R),
+                    [!head(IndexSet<start, nf, lmul>.R)]),
+                !listsplat("",
+                  !if(NoV0,
+                    !size(!tail(IndexSet<start, nf, lmul>.R)),
+                    !size([!head(IndexSet<start, nf, lmul>.R)]))))],
+          VRegList<LIn, !add(start, 1), nf, lmul, NoV0>.L));
 }
 
 // Vector registers
 let RegAltNameIndices = [ABIRegAltName] in {
   foreach Index = 0-31 in {
     def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>;
   }
 
let RegAltNameIndices = [ABIRegAltName] in {
   def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
   def VL     : RISCVReg<0, "vl", ["vl"]>;
   def VXSAT  : RISCVReg<0, "vxsat", ["vxsat"]>;
   def VXRM   : RISCVReg<0, "vxrm", ["vxrm"]>;
 }
 
 foreach m = [1, 2, 4] in {
   foreach n = NFList<m>.L in {
-    def "VN" # n # "M" # m: RegisterTuples<SubRegSet<[], 0, n, m>.L,
-                                           VRegList<[], 0, n, m>.L>;
+    def "VN" # n # "M" # m # "NoV0": RegisterTuples<
+                                       SubRegSet<[], 0, n, m>.L,
+                                       VRegList<[], 0, n, m, 1>.L>;
+    def "VN" # n # "M" # m # "V0" : RegisterTuples<
+                                       SubRegSet<[], 0, n, m>.L,
+                                       VRegList<[], 0, n, m, 0>.L>;
   }
 }
 
 class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
   : RegisterClass<"RISCV",
                   regTypes,
                   64, // The maximum supported ELEN is 64.
                   regList> {
defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t,
                    vbool4_t, vbool2_t, vbool1_t];
 
 def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
   let Size = 64;
 }
 
 foreach m = LMULList.m in {
   foreach nf = NFList<m>.L in {
-    def "VRN" # nf # "M" # m : VReg<[untyped],
-                               (add !cast<RegisterTuples>("VN" # nf # "M" # m)),
+    def "VRN" # nf # "M" # m: VReg<[untyped],
+                               (add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
+                                    !mul(nf, m)>;
+    def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
+                               (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
                                     !mul(nf, m)>;
   }
 }