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Differential D96048

[AMDGPU][GlobalISel] Fix v2s16 right shifts
ClosedPublic

Authored by foad on Feb 4 2021, 8:35 AM.

Details

Reviewers
arsenm
Petar.Avramovic
mbrkusanin
Commits
rGd84e5fdac1a6: [AMDGPU][GlobalISel] Fix v2s16 right shifts
Summary

When widening, each half of the v2s16 operands needs to be sign extended
for G_ASHR or zero extended for G_LSHR.

Diff Detail

Unit TestsFailed

TimeTest
330 msx64 debian > libarcher.races::task-dependency.c
340 msx64 debian > libarcher.races::task-taskgroup-unrelated.c
310 msx64 debian > libarcher.races::task-taskwait-nested.c
240 msx64 debian > libarcher.races::task-two.c
330 msx64 debian > libarcher.task::task-barrier.c
View Full Test Results (13 Failed)

Event Timeline

foad created this revision.Feb 4 2021, 8:35 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptFeb 4 2021, 8:35 AM
foad requested review of this revision.Feb 4 2021, 8:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 4 2021, 8:35 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad added a parent revision: D96047: [AMDGPU][GlobalISel] Use scalar min/max instructions.Feb 4 2021, 8:35 AM
arsenm accepted this revision.Feb 4 2021, 8:52 AM
This revision is now accepted and ready to land.Feb 4 2021, 8:52 AM
This revision was landed with ongoing or failed builds.Feb 4 2021, 9:05 AM
Closed by commit rGd84e5fdac1a6: [AMDGPU][GlobalISel] Fix v2s16 right shifts (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGd84e5fdac1a6: [AMDGPU][GlobalISel] Fix v2s16 right shifts.
Harbormaster completed remote builds in B87920: Diff 321450.Feb 4 2021, 10:39 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
66 lines
33 lines
12 lines
10 lines

Diff 321450

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 1,558 Lines • ▼ Show 20 Linesbool AMDGPURegisterBankInfo::applyMappingBFEIntrinsic(
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
// Return a suitable opcode for extending the operands of Opc when widening. // Return a suitable opcode for extending the operands of Opc when widening.
static unsigned getExtendOp(unsigned Opc) { static unsigned getExtendOp(unsigned Opc) {
switch (Opc) { switch (Opc) {
case TargetOpcode::G_ASHR:
case TargetOpcode::G_SMIN: case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX: case TargetOpcode::G_SMAX:
return TargetOpcode::G_SEXT; return TargetOpcode::G_SEXT;
case TargetOpcode::G_LSHR:
case TargetOpcode::G_UMIN: case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX: case TargetOpcode::G_UMAX:
return TargetOpcode::G_ZEXT; return TargetOpcode::G_ZEXT;
default: default:
return TargetOpcode::G_ANYEXT; return TargetOpcode::G_ANYEXT;
} }
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

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; GFX8-NEXT: s_ashr_i32 s1, s2, s3 ; GFX8-NEXT: s_ashr_i32 s1, s2, s3
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_and_b32 s0, s0, 0xffff ; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
; GFX8-NEXT: s_or_b32 s0, s1, s0 ; GFX8-NEXT: s_or_b32 s0, s1, s0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ashr_v2i16: ; GFX9-LABEL: s_ashr_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s2, s0, 16 ; GFX9-NEXT: s_sext_i32_i16 s2, s0
; GFX9-NEXT: s_lshr_b32 s3, s1, 16 ; GFX9-NEXT: s_sext_i32_i16 s3, s1
; GFX9-NEXT: s_ashr_i32 s0, s0, 16
; GFX9-NEXT: s_ashr_i32 s1, s1, 16
; GFX9-NEXT: s_ashr_i32 s2, s2, s3
; GFX9-NEXT: s_ashr_i32 s0, s0, s1 ; GFX9-NEXT: s_ashr_i32 s0, s0, s1
; GFX9-NEXT: s_ashr_i32 s1, s2, s3 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s0
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = ashr <2 x i16> %value, %amount %result = ashr <2 x i16> %value, %amount
%cast = bitcast <2 x i16> %result to i32 %cast = bitcast <2 x i16> %result to i32
ret i32 %cast ret i32 %cast
} }
define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { define amdgpu_ps float @ashr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
; GFX6-LABEL: ashr_v2i16_sv: ; GFX6-LABEL: ashr_v2i16_sv:
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; GFX8-NEXT: s_or_b32 s0, s2, s0 ; GFX8-NEXT: s_or_b32 s0, s2, s0
; GFX8-NEXT: s_lshl_b32 s2, s3, 16 ; GFX8-NEXT: s_lshl_b32 s2, s3, 16
; GFX8-NEXT: s_and_b32 s1, s1, s4 ; GFX8-NEXT: s_and_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s1, s2, s1 ; GFX8-NEXT: s_or_b32 s1, s2, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ashr_v4i16: ; GFX9-LABEL: s_ashr_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s4, s0, 16 ; GFX9-NEXT: s_sext_i32_i16 s4, s0
; GFX9-NEXT: s_lshr_b32 s5, s2, 16 ; GFX9-NEXT: s_sext_i32_i16 s5, s2
; GFX9-NEXT: s_ashr_i32 s0, s0, 16
; GFX9-NEXT: s_ashr_i32 s2, s2, 16
; GFX9-NEXT: s_ashr_i32 s0, s0, s2 ; GFX9-NEXT: s_ashr_i32 s0, s0, s2
; GFX9-NEXT: s_ashr_i32 s2, s4, s5 ; GFX9-NEXT: s_ashr_i32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s0
; GFX9-NEXT: s_lshr_b32 s2, s1, 16 ; GFX9-NEXT: s_sext_i32_i16 s2, s1
; GFX9-NEXT: s_lshr_b32 s4, s3, 16 ; GFX9-NEXT: s_sext_i32_i16 s4, s3
; GFX9-NEXT: s_ashr_i32 s1, s1, s3 ; GFX9-NEXT: s_ashr_i32 s1, s1, 16
; GFX9-NEXT: s_ashr_i32 s3, s3, 16
; GFX9-NEXT: s_ashr_i32 s2, s2, s4 ; GFX9-NEXT: s_ashr_i32 s2, s2, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 ; GFX9-NEXT: s_ashr_i32 s1, s1, s3
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = ashr <4 x i16> %value, %amount %result = ashr <4 x i16> %value, %amount
%cast = bitcast <4 x i16> %result to <2 x i32> %cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast ret <2 x i32> %cast
} }
; FIXME ; FIXME
; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) { ; define <5 x i16> @v_ashr_v5i16(<5 x i16> %value, <5 x i16> %amount) {
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; GFX8-NEXT: s_or_b32 s2, s4, s2 ; GFX8-NEXT: s_or_b32 s2, s4, s2
; GFX8-NEXT: s_lshl_b32 s4, s7, 16 ; GFX8-NEXT: s_lshl_b32 s4, s7, 16
; GFX8-NEXT: s_and_b32 s3, s3, s8 ; GFX8-NEXT: s_and_b32 s3, s3, s8
; GFX8-NEXT: s_or_b32 s3, s4, s3 ; GFX8-NEXT: s_or_b32 s3, s4, s3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ashr_v8i16: ; GFX9-LABEL: s_ashr_v8i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s8, s0, 16 ; GFX9-NEXT: s_sext_i32_i16 s8, s0
; GFX9-NEXT: s_lshr_b32 s9, s4, 16 ; GFX9-NEXT: s_sext_i32_i16 s9, s4
; GFX9-NEXT: s_ashr_i32 s0, s0, 16
; GFX9-NEXT: s_ashr_i32 s4, s4, 16
; GFX9-NEXT: s_ashr_i32 s0, s0, s4 ; GFX9-NEXT: s_ashr_i32 s0, s0, s4
; GFX9-NEXT: s_ashr_i32 s4, s8, s9 ; GFX9-NEXT: s_ashr_i32 s8, s8, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s8, s0
; GFX9-NEXT: s_lshr_b32 s4, s1, 16 ; GFX9-NEXT: s_sext_i32_i16 s4, s1
; GFX9-NEXT: s_lshr_b32 s8, s5, 16 ; GFX9-NEXT: s_sext_i32_i16 s8, s5
; GFX9-NEXT: s_ashr_i32 s1, s1, 16
; GFX9-NEXT: s_ashr_i32 s5, s5, 16
; GFX9-NEXT: s_ashr_i32 s1, s1, s5 ; GFX9-NEXT: s_ashr_i32 s1, s1, s5
; GFX9-NEXT: s_ashr_i32 s4, s4, s8 ; GFX9-NEXT: s_ashr_i32 s4, s4, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s1
; GFX9-NEXT: s_lshr_b32 s4, s2, 16 ; GFX9-NEXT: s_sext_i32_i16 s4, s2
; GFX9-NEXT: s_lshr_b32 s5, s6, 16 ; GFX9-NEXT: s_sext_i32_i16 s5, s6
; GFX9-NEXT: s_ashr_i32 s2, s2, 16
; GFX9-NEXT: s_ashr_i32 s6, s6, 16
; GFX9-NEXT: s_ashr_i32 s4, s4, s5 ; GFX9-NEXT: s_ashr_i32 s4, s4, s5
; GFX9-NEXT: s_ashr_i32 s2, s2, s6 ; GFX9-NEXT: s_ashr_i32 s2, s2, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2
; GFX9-NEXT: s_lshr_b32 s4, s3, 16 ; GFX9-NEXT: s_sext_i32_i16 s4, s3
; GFX9-NEXT: s_lshr_b32 s5, s7, 16 ; GFX9-NEXT: s_sext_i32_i16 s5, s7
; GFX9-NEXT: s_ashr_i32 s3, s3, s7 ; GFX9-NEXT: s_ashr_i32 s3, s3, 16
; GFX9-NEXT: s_ashr_i32 s6, s7, 16
; GFX9-NEXT: s_ashr_i32 s4, s4, s5 ; GFX9-NEXT: s_ashr_i32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 ; GFX9-NEXT: s_ashr_i32 s3, s3, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = ashr <8 x i16> %value, %amount %result = ashr <8 x i16> %value, %amount
%cast = bitcast <8 x i16> %result to <4 x i32> %cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast ret <4 x i32> %cast
} }
define i64 @v_ashr_i64(i64 %value, i64 %amount) { define i64 @v_ashr_i64(i64 %value, i64 %amount) {
; GFX6-LABEL: v_ashr_i64: ; GFX6-LABEL: v_ashr_i64:
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llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

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; GFX8-NEXT: s_lshr_b32 s1, s2, s4 ; GFX8-NEXT: s_lshr_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_and_b32 s0, s0, s3 ; GFX8-NEXT: s_and_b32 s0, s0, s3
; GFX8-NEXT: s_or_b32 s0, s1, s0 ; GFX8-NEXT: s_or_b32 s0, s1, s0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_lshr_v2i16: ; GFX9-LABEL: s_lshr_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s3, 0xffff
; GFX9-NEXT: s_lshr_b32 s2, s0, 16 ; GFX9-NEXT: s_lshr_b32 s2, s0, 16
; GFX9-NEXT: s_lshr_b32 s3, s1, 16 ; GFX9-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-NEXT: s_and_b32 s0, s0, s3
; GFX9-NEXT: s_and_b32 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s0, s0, s1 ; GFX9-NEXT: s_lshr_b32 s0, s0, s1
; GFX9-NEXT: s_lshr_b32 s1, s2, s3 ; GFX9-NEXT: s_lshr_b32 s1, s2, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = lshr <2 x i16> %value, %amount %result = lshr <2 x i16> %value, %amount
%cast = bitcast <2 x i16> %result to i32 %cast = bitcast <2 x i16> %result to i32
ret i32 %cast ret i32 %cast
} }
define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) { define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
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; GFX8-NEXT: s_or_b32 s0, s2, s0 ; GFX8-NEXT: s_or_b32 s0, s2, s0
; GFX8-NEXT: s_lshl_b32 s2, s3, 16 ; GFX8-NEXT: s_lshl_b32 s2, s3, 16
; GFX8-NEXT: s_and_b32 s1, s1, s6 ; GFX8-NEXT: s_and_b32 s1, s1, s6
; GFX8-NEXT: s_or_b32 s1, s2, s1 ; GFX8-NEXT: s_or_b32 s1, s2, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_lshr_v4i16: ; GFX9-LABEL: s_lshr_v4i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s5, 0xffff
; GFX9-NEXT: s_lshr_b32 s4, s0, 16 ; GFX9-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-NEXT: s_lshr_b32 s5, s2, 16 ; GFX9-NEXT: s_lshr_b32 s6, s2, 16
; GFX9-NEXT: s_and_b32 s0, s0, s5
; GFX9-NEXT: s_and_b32 s2, s2, s5
; GFX9-NEXT: s_lshr_b32 s0, s0, s2 ; GFX9-NEXT: s_lshr_b32 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s2, s4, s5 ; GFX9-NEXT: s_lshr_b32 s2, s4, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s2, s1, 16 ; GFX9-NEXT: s_lshr_b32 s2, s1, 16
; GFX9-NEXT: s_lshr_b32 s4, s3, 16 ; GFX9-NEXT: s_lshr_b32 s4, s3, 16
; GFX9-NEXT: s_and_b32 s1, s1, s5
; GFX9-NEXT: s_and_b32 s3, s3, s5
; GFX9-NEXT: s_lshr_b32 s1, s1, s3 ; GFX9-NEXT: s_lshr_b32 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s2, s2, s4 ; GFX9-NEXT: s_lshr_b32 s2, s2, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = lshr <4 x i16> %value, %amount %result = lshr <4 x i16> %value, %amount
%cast = bitcast <4 x i16> %result to <2 x i32> %cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast ret <2 x i32> %cast
} }
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; GFX8-NEXT: s_or_b32 s2, s4, s2 ; GFX8-NEXT: s_or_b32 s2, s4, s2
; GFX8-NEXT: s_lshl_b32 s4, s7, 16 ; GFX8-NEXT: s_lshl_b32 s4, s7, 16
; GFX8-NEXT: s_and_b32 s3, s3, s12 ; GFX8-NEXT: s_and_b32 s3, s3, s12
; GFX8-NEXT: s_or_b32 s3, s4, s3 ; GFX8-NEXT: s_or_b32 s3, s4, s3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_lshr_v8i16: ; GFX9-LABEL: s_lshr_v8i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s9, 0xffff
; GFX9-NEXT: s_lshr_b32 s8, s0, 16 ; GFX9-NEXT: s_lshr_b32 s8, s0, 16
; GFX9-NEXT: s_lshr_b32 s9, s4, 16 ; GFX9-NEXT: s_lshr_b32 s10, s4, 16
; GFX9-NEXT: s_and_b32 s0, s0, s9
; GFX9-NEXT: s_and_b32 s4, s4, s9
; GFX9-NEXT: s_lshr_b32 s0, s0, s4 ; GFX9-NEXT: s_lshr_b32 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s4, s8, s9 ; GFX9-NEXT: s_lshr_b32 s4, s8, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s4, s1, 16 ; GFX9-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-NEXT: s_lshr_b32 s8, s5, 16 ; GFX9-NEXT: s_lshr_b32 s8, s5, 16
; GFX9-NEXT: s_and_b32 s1, s1, s9
; GFX9-NEXT: s_and_b32 s5, s5, s9
; GFX9-NEXT: s_lshr_b32 s1, s1, s5 ; GFX9-NEXT: s_lshr_b32 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s4, s4, s8 ; GFX9-NEXT: s_lshr_b32 s4, s4, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s4, s2, 16 ; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_lshr_b32 s5, s6, 16 ; GFX9-NEXT: s_lshr_b32 s5, s6, 16
; GFX9-NEXT: s_lshr_b32 s4, s4, s5 ; GFX9-NEXT: s_and_b32 s2, s2, s9
; GFX9-NEXT: s_and_b32 s6, s6, s9
; GFX9-NEXT: s_lshr_b32 s2, s2, s6 ; GFX9-NEXT: s_lshr_b32 s2, s2, s6
; GFX9-NEXT: s_lshr_b32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX9-NEXT: s_lshr_b32 s4, s3, 16 ; GFX9-NEXT: s_lshr_b32 s4, s3, 16
; GFX9-NEXT: s_lshr_b32 s5, s7, 16 ; GFX9-NEXT: s_lshr_b32 s5, s7, 16
; GFX9-NEXT: s_lshr_b32 s3, s3, s7 ; GFX9-NEXT: s_and_b32 s3, s3, s9
; GFX9-NEXT: s_and_b32 s6, s7, s9
; GFX9-NEXT: s_lshr_b32 s3, s3, s6
; GFX9-NEXT: s_lshr_b32 s4, s4, s5 ; GFX9-NEXT: s_lshr_b32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
%result = lshr <8 x i16> %value, %amount %result = lshr <8 x i16> %value, %amount
%cast = bitcast <8 x i16> %result to <4 x i32> %cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast ret <4 x i32> %cast
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir

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body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: ashr_v2s16_ss ; CHECK-LABEL: name: ashr_v2s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C1]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[BITCAST1]](s32) ; CHECK: [[ASHR2:%[0-9]+]]:sgpr(s32) = G_ASHR [[SEXT_INREG]], [[SEXT_INREG1]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[LSHR]], [[LSHR1]](s32) ; CHECK: [[ASHR3:%[0-9]+]]:sgpr(s32) = G_ASHR [[ASHR]], [[ASHR1]](s32)
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ASHR]](s32), [[ASHR1]](s32) ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ASHR2]](s32), [[ASHR3]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_ASHR %0, %1 %2:_(<2 x s16>) = G_ASHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir

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bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: lshr_v2s16_ss ; CHECK-LABEL: name: lshr_v2s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C1]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[BITCAST1]](s32) ; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]]
; CHECK: [[LSHR2:%[0-9]+]]:sgpr(s32) = G_LSHR [[AND]], [[AND1]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:sgpr(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:sgpr(s32) = G_LSHR [[LSHR]], [[LSHR1]](s32)
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32) ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_LSHR %0, %1 %2:_(<2 x s16>) = G_LSHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
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