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Differential D96047

[AMDGPU][GlobalISel] Use scalar min/max instructions
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Authored by foad on Feb 4 2021, 8:35 AM.

Details

Reviewers
arsenm
Petar.Avramovic
mbrkusanin
Commits
rGb3bb5c3efc97: [AMDGPU][GlobalISel] Use scalar min/max instructions
Summary

SALU min/max s32 instructions exist so use them. This means that
regbankselect can handle min/max much like add/sub/mul/shifts.

Diff Detail

Event Timeline

foad created this revision.Feb 4 2021, 8:35 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptFeb 4 2021, 8:35 AM
foad requested review of this revision.Feb 4 2021, 8:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 4 2021, 8:35 AM
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foad added a child revision: D96048: [AMDGPU][GlobalISel] Fix v2s16 right shifts.Feb 4 2021, 8:35 AM
arsenm accepted this revision.Feb 4 2021, 8:53 AM

I thought I fixed this already

This revision is now accepted and ready to land.Feb 4 2021, 8:53 AM
This revision was landed with ongoing or failed builds.Feb 4 2021, 9:04 AM
Closed by commit rGb3bb5c3efc97: [AMDGPU][GlobalISel] Use scalar min/max instructions (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGb3bb5c3efc97: [AMDGPU][GlobalISel] Use scalar min/max instructions.
Harbormaster completed remote builds in B87919: Diff 321449.Feb 4 2021, 10:33 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
138 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
26 lines
30 lines
28 lines
28 lines
1890 lines
1748 lines
257 lines
225 lines

Diff 321472

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linespublic:
applyMappingImage(MachineInstr &MI, applyMappingImage(MachineInstr &MI,
const OperandsMapper &OpdMapper, const OperandsMapper &OpdMapper,
MachineRegisterInfo &MRI, int RSrcIdx) const; MachineRegisterInfo &MRI, int RSrcIdx) const;
bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const;
bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper, bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper,
bool Signed) const; bool Signed) const;
void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
Register Reg) const; Register Reg) const;
std::pair<Register, unsigned> std::pair<Register, unsigned>
splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B, MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
MachineInstr &MI) const; MachineInstr &MI) const;
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 585 Lines • ▼ Show 20 Lines const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}), AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands 4); // Num Operands
AltMappings.push_back(&VVMapping); AltMappings.push_back(&VVMapping);
return AltMappings; return AltMappings;
} }
case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX:
case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX: {
static const OpRegBankEntry<3> Table[2] = {
{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 },
// Scalar requires cmp+select, and extends if 16-bit.
// FIXME: Should there be separate costs for 32 and 16-bit
{ { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 3 }
};
const std::array<unsigned, 3> RegSrcOpIdx = { { 0, 1, 2 } };
return addMappingFromTable<3>(MI, MRI, RegSrcOpIdx, makeArrayRef(Table));
}
case TargetOpcode::G_UADDE: case TargetOpcode::G_UADDE:
case TargetOpcode::G_USUBE: case TargetOpcode::G_USUBE:
case TargetOpcode::G_SADDE: case TargetOpcode::G_SADDE:
case TargetOpcode::G_SSUBE: { case TargetOpcode::G_SSUBE: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1, const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping( getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
▲ Show 20 Lines • Show All 954 Lines • ▼ Show 20 Linesbool AMDGPURegisterBankInfo::applyMappingBFEIntrinsic(
auto MIB = B.buildInstr(Opc, {DstReg}, {SrcReg, MergedInputs}); auto MIB = B.buildInstr(Opc, {DstReg}, {SrcReg, MergedInputs});
if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
llvm_unreachable("failed to constrain BFE"); llvm_unreachable("failed to constrain BFE");
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
// FIXME: Duplicated from LegalizerHelper // Return a suitable opcode for extending the operands of Opc when widening.
static CmpInst::Predicate minMaxToCompare(unsigned Opc) { static unsigned getExtendOp(unsigned Opc) {
switch (Opc) {
case TargetOpcode::G_SMIN:
return CmpInst::ICMP_SLT;
case TargetOpcode::G_SMAX:
return CmpInst::ICMP_SGT;
case TargetOpcode::G_UMIN:
return CmpInst::ICMP_ULT;
case TargetOpcode::G_UMAX:
return CmpInst::ICMP_UGT;
default:
llvm_unreachable("not in integer min/max");
}
}
static unsigned minMaxToExtend(unsigned Opc) {
switch (Opc) { switch (Opc) {
case TargetOpcode::G_SMIN: case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX: case TargetOpcode::G_SMAX:
return TargetOpcode::G_SEXT; return TargetOpcode::G_SEXT;
case TargetOpcode::G_UMIN: case TargetOpcode::G_UMIN:
case TargetOpcode::G_UMAX: case TargetOpcode::G_UMAX:
return TargetOpcode::G_ZEXT; return TargetOpcode::G_ZEXT;
default: default:
llvm_unreachable("not in integer min/max"); return TargetOpcode::G_ANYEXT;
} }
} }
// Emit a legalized extension from <2 x s16> to 2 32-bit components, avoiding // Emit a legalized extension from <2 x s16> to 2 32-bit components, avoiding
// any illegal vector extend or unmerge operations. // any illegal vector extend or unmerge operations.
static std::pair<Register, Register> static std::pair<Register, Register>
unpackV2S16ToS32(MachineIRBuilder &B, Register Src, unsigned ExtOpcode) { unpackV2S16ToS32(MachineIRBuilder &B, Register Src, unsigned ExtOpcode) {
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
Show All 10 Lines if (ExtOpcode == TargetOpcode::G_ZEXT) {
auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff));
return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0)); return std::make_pair(ExtLo.getReg(0), ShiftHi.getReg(0));
} }
assert(ExtOpcode == TargetOpcode::G_ANYEXT); assert(ExtOpcode == TargetOpcode::G_ANYEXT);
return std::make_pair(Bitcast.getReg(0), ShiftHi.getReg(0)); return std::make_pair(Bitcast.getReg(0), ShiftHi.getReg(0));
} }
static MachineInstr *buildExpandedScalarMinMax(MachineIRBuilder &B,
CmpInst::Predicate Pred,
Register Dst, Register Src0,
Register Src1) {
const LLT CmpType = LLT::scalar(32);
auto Cmp = B.buildICmp(Pred, CmpType, Src0, Src1);
return B.buildSelect(Dst, Cmp, Src0, Src1);
}
// FIXME: Duplicated from LegalizerHelper, except changing the boolean type.
void AMDGPURegisterBankInfo::lowerScalarMinMax(MachineIRBuilder &B,
MachineInstr &MI) const {
Register Dst = MI.getOperand(0).getReg();
Register Src0 = MI.getOperand(1).getReg();
Register Src1 = MI.getOperand(2).getReg();
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
MachineInstr *Sel = buildExpandedScalarMinMax(B, Pred, Dst, Src0, Src1);
Register CmpReg = Sel->getOperand(1).getReg();
B.getMRI()->setRegBank(CmpReg, AMDGPU::SGPRRegBank);
MI.eraseFromParent();
}
// For cases where only a single copy is inserted for matching register banks. // For cases where only a single copy is inserted for matching register banks.
// Replace the register in the instruction operand // Replace the register in the instruction operand
static bool substituteSimpleCopyRegs( static bool substituteSimpleCopyRegs(
const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx) { const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx) {
SmallVector<unsigned, 1> SrcReg(OpdMapper.getVRegs(OpIdx)); SmallVector<unsigned, 1> SrcReg(OpdMapper.getVRegs(OpIdx));
if (!SrcReg.empty()) { if (!SrcReg.empty()) {
assert(SrcReg.size() == 1); assert(SrcReg.size() == 1);
OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]); OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
▲ Show 20 Lines • Show All 673 Lines • ▼ Show 20 Lines case AMDGPU::G_XOR: {
MI.eraseFromParent(); MI.eraseFromParent();
return; return;
} }
case AMDGPU::G_ADD: case AMDGPU::G_ADD:
case AMDGPU::G_SUB: case AMDGPU::G_SUB:
case AMDGPU::G_MUL: case AMDGPU::G_MUL:
case AMDGPU::G_SHL: case AMDGPU::G_SHL:
case AMDGPU::G_LSHR: case AMDGPU::G_LSHR:
case AMDGPU::G_ASHR: { case AMDGPU::G_ASHR:
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX: {
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
// 16-bit operations are VALU only, but can be promoted to 32-bit SALU. // 16-bit operations are VALU only, but can be promoted to 32-bit SALU.
// Packed 16-bit operations need to be scalarized and promoted. // Packed 16-bit operations need to be scalarized and promoted.
if (DstTy != LLT::scalar(16) && DstTy != LLT::vector(2, 16)) if (DstTy != LLT::scalar(16) && DstTy != LLT::vector(2, 16))
break; break;
const RegisterBank *DstBank = const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::VGPRRegBank) if (DstBank == &AMDGPU::VGPRRegBank)
break; break;
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock *MBB = MI.getParent();
MachineFunction *MF = MBB->getParent(); MachineFunction *MF = MBB->getParent();
ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank);
MachineIRBuilder B(MI, ApplySALU); MachineIRBuilder B(MI, ApplySALU);
if (DstTy.isVector()) { if (DstTy.isVector()) {
Register WideSrc0Lo, WideSrc0Hi; Register WideSrc0Lo, WideSrc0Hi;
Register WideSrc1Lo, WideSrc1Hi; Register WideSrc1Lo, WideSrc1Hi;
unsigned ExtendOp = getExtendOp(MI.getOpcode());
std::tie(WideSrc0Lo, WideSrc0Hi) std::tie(WideSrc0Lo, WideSrc0Hi)
= unpackV2S16ToS32(B, MI.getOperand(1).getReg(), AMDGPU::G_ANYEXT); = unpackV2S16ToS32(B, MI.getOperand(1).getReg(), ExtendOp);
std::tie(WideSrc1Lo, WideSrc1Hi) std::tie(WideSrc1Lo, WideSrc1Hi)
= unpackV2S16ToS32(B, MI.getOperand(2).getReg(), AMDGPU::G_ANYEXT); = unpackV2S16ToS32(B, MI.getOperand(2).getReg(), ExtendOp);
auto Lo = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Lo, WideSrc1Lo}); auto Lo = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Lo, WideSrc1Lo});
auto Hi = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Hi, WideSrc1Hi}); auto Hi = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Hi, WideSrc1Hi});
B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)}); B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)});
MI.eraseFromParent(); MI.eraseFromParent();
} else { } else {
LegalizerHelper Helper(*MF, ApplySALU, B); LegalizerHelper Helper(*MF, ApplySALU, B);
if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
llvm_unreachable("widen scalar should have succeeded"); llvm_unreachable("widen scalar should have succeeded");
// FIXME: s16 shift amounts should be legal. // FIXME: s16 shift amounts should be legal.
if (Opc == AMDGPU::G_SHL || Opc == AMDGPU::G_LSHR || if (Opc == AMDGPU::G_SHL || Opc == AMDGPU::G_LSHR ||
Opc == AMDGPU::G_ASHR) { Opc == AMDGPU::G_ASHR) {
B.setInsertPt(*MBB, MI.getIterator()); B.setInsertPt(*MBB, MI.getIterator());
if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized) if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized)
llvm_unreachable("widen scalar should have succeeded"); llvm_unreachable("widen scalar should have succeeded");
} }
} }
return; return;
} }
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX: {
Register DstReg = MI.getOperand(0).getReg();
const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::VGPRRegBank)
break;
MachineFunction *MF = MI.getParent()->getParent();
MachineIRBuilder B(MI);
// Turn scalar min/max into a compare and select.
LLT Ty = MRI.getType(DstReg);
const LLT S32 = LLT::scalar(32);
const LLT S16 = LLT::scalar(16);
const LLT V2S16 = LLT::vector(2, 16);
if (Ty == V2S16) {
ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank);
B.setChangeObserver(ApplySALU);
// Need to widen to s32, and expand as cmp + select, and avoid producing
// illegal vector extends or unmerges that would need further
// legalization.
//
// TODO: Should we just readfirstlane? That should probably be handled
// with a UniformVGPR register bank that wouldn't need special
// consideration here.
Register Dst = MI.getOperand(0).getReg();
Register Src0 = MI.getOperand(1).getReg();
Register Src1 = MI.getOperand(2).getReg();
Register WideSrc0Lo, WideSrc0Hi;
Register WideSrc1Lo, WideSrc1Hi;
unsigned ExtendOp = minMaxToExtend(MI.getOpcode());
std::tie(WideSrc0Lo, WideSrc0Hi) = unpackV2S16ToS32(B, Src0, ExtendOp);
std::tie(WideSrc1Lo, WideSrc1Hi) = unpackV2S16ToS32(B, Src1, ExtendOp);
Register Lo = MRI.createGenericVirtualRegister(S32);
Register Hi = MRI.createGenericVirtualRegister(S32);
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
buildExpandedScalarMinMax(B, Pred, Lo, WideSrc0Lo, WideSrc1Lo);
buildExpandedScalarMinMax(B, Pred, Hi, WideSrc0Hi, WideSrc1Hi);
B.buildBuildVectorTrunc(Dst, {Lo, Hi});
MI.eraseFromParent();
} else if (Ty == S16) {
ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank);
B.setChangeObserver(ApplySALU);
LegalizerHelper Helper(*MF, ApplySALU, B);
// Need to widen to s32, and expand as cmp + select.
if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
llvm_unreachable("widenScalar should have succeeded");
// FIXME: This is relying on widenScalar leaving MI in place.
lowerScalarMinMax(B, MI);
} else
lowerScalarMinMax(B, MI);
return;
}
case AMDGPU::G_SEXT_INREG: { case AMDGPU::G_SEXT_INREG: {
SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
if (SrcRegs.empty()) if (SrcRegs.empty())
break; // Nothing to repair break; // Nothing to repair
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
MachineIRBuilder B(MI); MachineIRBuilder B(MI);
ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
▲ Show 20 Lines • Show All 2,000 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
--- ---
name: smax_s32_ss name: smax_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smax_s32_ss ; CHECK-LABEL: name: smax_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMAX %0, %1 %2:_(s32) = G_SMAX %0, %1
... ...
--- ---
name: smax_s32_sv name: smax_s32_sv
legalized: true legalized: true
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smax_s32_ss_vgpr_use ; CHECK-LABEL: name: smax_s32_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]] ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $vgpr0 = COPY [[SMAX]](s32)
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMAX %0, %1 %2:_(s32) = G_SMAX %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: smax_s16_ss name: smax_s16_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smax_s16_ss ; CHECK-LABEL: name: smax_s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16) ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16) ; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[SEXT]], [[SEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMAX]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $sgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $sgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SMAX %2, %3 %4:_(s16) = G_SMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 11 Lines bb.0:
; CHECK-LABEL: name: smax_s16_ss_vgpr_use ; CHECK-LABEL: name: smax_s16_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16) ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16) ; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[SEXT]], [[SEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMAX]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SMAX %2, %3 %4:_(s16) = G_SMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 15 Lines bb.0:
; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16 ; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT_INREG]](s32), [[SEXT_INREG1]] ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT_INREG]], [[SEXT_INREG1]] ; CHECK: [[SMAX1:%[0-9]+]]:sgpr(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]] ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SMAX]](s32), [[SMAX1]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP1]](s32), [[ASHR]], [[ASHR1]]
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_SMAX %0, %1 %2:_(<2 x s16>) = G_SMAX %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s
# XUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
--- ---
name: smin_s32_ss name: smin_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smin_s32_ss ; CHECK-LABEL: name: smin_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $sgpr0 = COPY [[SMIN]](s32)
; CHECK: $sgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMIN %0, %1 %2:_(s32) = G_SMIN %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
name: smin_s32_sv name: smin_s32_sv
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smin_s32_ss_vgpr_use ; CHECK-LABEL: name: smin_s32_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $vgpr0 = COPY [[SMIN]](s32)
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_SMIN %0, %1 %2:_(s32) = G_SMIN %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: smin_s16_ss name: smin_s16_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: smin_s16_ss ; CHECK-LABEL: name: smin_s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16) ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16) ; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SEXT]], [[SEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMIN]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $sgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $sgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SMIN %2, %3 %4:_(s16) = G_SMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 11 Lines bb.0:
; CHECK-LABEL: name: smin_s16_ss_vgpr_use ; CHECK-LABEL: name: smin_s16_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16) ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16) ; CHECK: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SEXT]], [[SEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMIN]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SMIN %2, %3 %4:_(s16) = G_SMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 15 Lines bb.0:
; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16 ; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]] ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT_INREG]], [[SEXT_INREG1]] ; CHECK: [[SMIN1:%[0-9]+]]:sgpr(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SMIN]](s32), [[SMIN1]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP1]](s32), [[ASHR]], [[ASHR1]]
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_SMIN %0, %1 %2:_(<2 x s16>) = G_SMIN %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
--- ---
name: umax_s32_ss name: umax_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umax_s32_ss ; CHECK-LABEL: name: umax_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]] ; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $sgpr0 = COPY [[UMAX]](s32)
; CHECK: $sgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMAX %0, %1 %2:_(s32) = G_UMAX %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
name: umax_s32_sv name: umax_s32_sv
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umax_s32_ss_vgpr_use ; CHECK-LABEL: name: umax_s32_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]] ; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $vgpr0 = COPY [[UMAX]](s32)
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMAX %0, %1 %2:_(s32) = G_UMAX %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: umax_s16_ss name: umax_s16_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umax_s16_ss ; CHECK-LABEL: name: umax_s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[ZEXT]], [[ZEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[UMAX]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $sgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $sgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_UMAX %2, %3 %4:_(s16) = G_UMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 11 Lines bb.0:
; CHECK-LABEL: name: umax_s16_ss_vgpr_use ; CHECK-LABEL: name: umax_s16_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[ZEXT]], [[ZEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[UMAX]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_UMAX %2, %3 %4:_(s16) = G_UMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 17 Lines bb.0:
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535 ; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[AND1]] ; CHECK: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[AND]], [[AND1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[AND]], [[AND1]] ; CHECK: [[UMAX1:%[0-9]+]]:sgpr(s32) = G_UMAX [[LSHR]], [[LSHR1]]
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[LSHR]](s32), [[LSHR1]] ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UMAX]](s32), [[UMAX1]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP1]](s32), [[LSHR]], [[LSHR1]]
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_UMAX %0, %1 %2:_(<2 x s16>) = G_UMAX %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
--- ---
name: umin_s32_ss name: umin_s32_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umin_s32_ss ; CHECK-LABEL: name: umin_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] ; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $sgpr0 = COPY [[UMIN]](s32)
; CHECK: $sgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMIN %0, %1 %2:_(s32) = G_UMIN %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umin_s32_ss_vgpr_use ; CHECK-LABEL: name: umin_s32_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]] ; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]] ; CHECK: $vgpr0 = COPY [[UMIN]](s32)
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s32) = G_UMIN %0, %1 %2:_(s32) = G_UMIN %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: umin_s16_ss name: umin_s16_ss
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: umin_s16_ss ; CHECK-LABEL: name: umin_s16_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[ZEXT]], [[ZEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[UMIN]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $sgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $sgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_UMIN %2, %3 %4:_(s16) = G_UMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 11 Lines bb.0:
; CHECK-LABEL: name: umin_s16_ss_vgpr_use ; CHECK-LABEL: name: umin_s16_ss_vgpr_use
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32) ; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[ZEXT]], [[ZEXT1]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]] ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[UMIN]](s32)
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1 %1:_(s32) = COPY $sgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_UMIN %2, %3 %4:_(s16) = G_UMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 17 Lines bb.0:
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 ; CHECK: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535 ; CHECK: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
; CHECK: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[BITCAST1]], [[C3]]
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] ; CHECK: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[AND]], [[AND1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[AND]], [[AND1]] ; CHECK: [[UMIN1:%[0-9]+]]:sgpr(s32) = G_UMIN [[LSHR]], [[LSHR1]]
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[LSHR]](s32), [[LSHR1]] ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UMIN]](s32), [[UMIN1]](s32)
; CHECK: [[SELECT1:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP1]](s32), [[LSHR]], [[LSHR1]]
; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) ; CHECK: $sgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $sgpr0 %0:_(<2 x s16>) = COPY $sgpr0
%1:_(<2 x s16>) = COPY $sgpr1 %1:_(<2 x s16>) = COPY $sgpr1
%2:_(<2 x s16>) = G_UMIN %0, %1 %2:_(<2 x s16>) = G_UMIN %0, %1
$sgpr0 = COPY %2 $sgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs) %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result ret i7 %result
} }
define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) { define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i7: ; GFX6-LABEL: s_saddsat_i7:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25 ; GFX6-NEXT: s_lshl_b32 s0, s0, 25
; GFX6-NEXT: s_min_i32 s3, s0, 0
; GFX6-NEXT: s_max_i32 s2, s0, 0
; GFX6-NEXT: s_lshl_b32 s1, s1, 25 ; GFX6-NEXT: s_lshl_b32 s1, s1, 25
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1 ; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cselect_b32 s1, s3, s1 ; GFX6-NEXT: s_max_i32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2 ; GFX6-NEXT: s_min_i32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 25 ; GFX6-NEXT: s_ashr_i32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_i7: ; GFX8-LABEL: s_saddsat_i7:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0 ; GFX8-NEXT: s_sext_i32_i16 s3, s0
; GFX8-NEXT: s_sext_i32_i16 s4, 0 ; GFX8-NEXT: s_sext_i32_i16 s4, 0
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_cselect_b32 s5, s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s5, 0x7fff, s5 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_cmp_lt_i32 s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s3, 0xffff8000, s3 ; GFX8-NEXT: s_sub_i32 s3, 0xffff8000, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s1 ; GFX8-NEXT: s_max_i32 s1, s3, s1
; GFX8-NEXT: s_cselect_b32 s1, s3, s1 ; GFX8-NEXT: s_sub_i32 s5, 0x7fff, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s5 ; GFX8-NEXT: s_sext_i32_i16 s3, s5
; GFX8-NEXT: s_cmp_lt_i32 s1, s3 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_i7: ; GFX9-LABEL: s_saddsat_i7:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs) %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result ret i8 %result
} }
define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) { define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i8: ; GFX6-LABEL: s_saddsat_i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_min_i32 s3, s0, 0
; GFX6-NEXT: s_max_i32 s2, s0, 0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1 ; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cselect_b32 s1, s3, s1 ; GFX6-NEXT: s_max_i32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2 ; GFX6-NEXT: s_min_i32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 24 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_i8: ; GFX8-LABEL: s_saddsat_i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0 ; GFX8-NEXT: s_sext_i32_i16 s3, s0
; GFX8-NEXT: s_sext_i32_i16 s4, 0 ; GFX8-NEXT: s_sext_i32_i16 s4, 0
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_cselect_b32 s5, s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s5, 0x7fff, s5 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_cmp_lt_i32 s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s3, 0xffff8000, s3 ; GFX8-NEXT: s_sub_i32 s3, 0xffff8000, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s1 ; GFX8-NEXT: s_max_i32 s1, s3, s1
; GFX8-NEXT: s_cselect_b32 s1, s3, s1 ; GFX8-NEXT: s_sub_i32 s5, 0x7fff, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s5 ; GFX8-NEXT: s_sext_i32_i16 s3, s5
; GFX8-NEXT: s_cmp_lt_i32 s1, s3 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_i8: ; GFX9-LABEL: s_saddsat_i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_saddsat_v2i8: ; GFX6-LABEL: s_saddsat_v2i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_min_i32 s7, s0, 0
; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, 0 ; GFX6-NEXT: s_max_i32 s6, s0, 0
; GFX6-NEXT: s_sub_i32 s6, s4, s6 ; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s1, s7, s1
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_min_i32 s1, s1, s6
; GFX6-NEXT: s_cselect_b32 s7, s0, 0
; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s1
; GFX6-NEXT: s_cselect_b32 s1, s7, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s6
; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s3, s1, 0
; GFX6-NEXT: s_cselect_b32 s3, s1, 0
; GFX6-NEXT: s_sub_i32 s3, s4, s3 ; GFX6-NEXT: s_sub_i32 s3, s4, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, 0 ; GFX6-NEXT: s_min_i32 s4, s1, 0
; GFX6-NEXT: s_cselect_b32 s4, s1, 0
; GFX6-NEXT: s_sub_i32 s4, s5, s4 ; GFX6-NEXT: s_sub_i32 s4, s5, s4
; GFX6-NEXT: s_cmp_gt_i32 s4, s2 ; GFX6-NEXT: s_max_i32 s2, s4, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, s3
; GFX6-NEXT: s_cselect_b32 s2, s2, s3
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s1, s1, 24 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_and_b32 s1, s1, s2 ; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v2i8: ; GFX8-LABEL: s_saddsat_v2i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8 ; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s4 ; GFX8-NEXT: s_lshl_b32 s0, s0, s4
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_sext_i32_i16 s7, s0 ; GFX8-NEXT: s_sext_i32_i16 s7, s0
; GFX8-NEXT: s_sext_i32_i16 s8, 0 ; GFX8-NEXT: s_sext_i32_i16 s8, 0
; GFX8-NEXT: s_cmp_gt_i32 s7, s8 ; GFX8-NEXT: s_max_i32 s9, s7, s8
; GFX8-NEXT: s_movk_i32 s5, 0x7fff
; GFX8-NEXT: s_cselect_b32 s9, s7, s8
; GFX8-NEXT: s_sub_i32 s9, s5, s9
; GFX8-NEXT: s_cmp_lt_i32 s7, s8
; GFX8-NEXT: s_movk_i32 s6, 0x8000 ; GFX8-NEXT: s_movk_i32 s6, 0x8000
; GFX8-NEXT: s_cselect_b32 s7, s7, s8 ; GFX8-NEXT: s_min_i32 s7, s7, s8
; GFX8-NEXT: s_sub_i32 s7, s6, s7 ; GFX8-NEXT: s_sub_i32 s7, s6, s7
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_movk_i32 s5, 0x7fff
; GFX8-NEXT: s_sext_i32_i16 s7, s7 ; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s7, s1 ; GFX8-NEXT: s_max_i32 s1, s7, s1
; GFX8-NEXT: s_cselect_b32 s1, s7, s1 ; GFX8-NEXT: s_sub_i32 s9, s5, s9
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s7, s9 ; GFX8-NEXT: s_sext_i32_i16 s7, s9
; GFX8-NEXT: s_cmp_lt_i32 s1, s7 ; GFX8-NEXT: s_min_i32 s1, s1, s7
; GFX8-NEXT: s_cselect_b32 s1, s1, s7
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_lshl_b32 s1, s2, s4 ; GFX8-NEXT: s_lshl_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s2, s3, s4 ; GFX8-NEXT: s_lshl_b32 s2, s3, s4
; GFX8-NEXT: s_ashr_i32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s1 ; GFX8-NEXT: s_sext_i32_i16 s3, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s8 ; GFX8-NEXT: s_max_i32 s7, s3, s8
; GFX8-NEXT: s_cselect_b32 s7, s3, s8 ; GFX8-NEXT: s_min_i32 s3, s3, s8
; GFX8-NEXT: s_sub_i32 s5, s5, s7
; GFX8-NEXT: s_cmp_lt_i32 s3, s8
; GFX8-NEXT: s_cselect_b32 s3, s3, s8
; GFX8-NEXT: s_sub_i32 s3, s6, s3 ; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s3, s2 ; GFX8-NEXT: s_max_i32 s2, s3, s2
; GFX8-NEXT: s_cselect_b32 s2, s3, s2 ; GFX8-NEXT: s_sub_i32 s5, s5, s7
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s5 ; GFX8-NEXT: s_sext_i32_i16 s3, s5
; GFX8-NEXT: s_cmp_lt_i32 s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_movk_i32 s2, 0xff ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s1, s1, s4 ; GFX8-NEXT: s_ashr_i32 s1, s1, s4
; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_ashr_i32 s0, s0, s4
; GFX8-NEXT: s_and_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s0, s0, s2 ; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v2i8: ; GFX9-LABEL: s_saddsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
} }
define amdgpu_ps i32 @s_saddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) { define amdgpu_ps i32 @s_saddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-LABEL: s_saddsat_v4i8: ; GFX6-LABEL: s_saddsat_v4i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24 ; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_min_i32 s11, s0, 0
; GFX6-NEXT: s_lshr_b32 s5, s1, 8 ; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16 ; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24 ; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_brev_b32 s8, -2 ; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, 0 ; GFX6-NEXT: s_max_i32 s10, s0, 0
; GFX6-NEXT: s_sub_i32 s10, s8, s10 ; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s1, s11, s1
; GFX6-NEXT: s_brev_b32 s9, 1 ; GFX6-NEXT: s_min_i32 s1, s1, s10
; GFX6-NEXT: s_cselect_b32 s11, s0, 0
; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_cmp_gt_i32 s11, s1
; GFX6-NEXT: s_cselect_b32 s1, s11, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s10
; GFX6-NEXT: s_cselect_b32 s1, s1, s10
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_ashr_i32 s0, s0, 24 ; GFX6-NEXT: s_min_i32 s10, s1, 0
; GFX6-NEXT: s_lshl_b32 s2, s5, 24 ; GFX6-NEXT: s_lshl_b32 s2, s5, 24
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s5, s1, 0
; GFX6-NEXT: s_cselect_b32 s5, s1, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s10, s1, 0
; GFX6-NEXT: s_sub_i32 s10, s9, s10 ; GFX6-NEXT: s_sub_i32 s10, s9, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s2 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s2, s10, s2 ; GFX6-NEXT: s_max_i32 s2, s10, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s5 ; GFX6-NEXT: s_min_i32 s2, s2, s5
; GFX6-NEXT: s_cselect_b32 s2, s2, s5
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_lshl_b32 s3, s6, 24 ; GFX6-NEXT: s_lshl_b32 s3, s6, 24
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_min_i32 s6, s2, 0
; GFX6-NEXT: s_cselect_b32 s5, s2, 0 ; GFX6-NEXT: s_max_i32 s5, s2, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s2, 0
; GFX6-NEXT: s_cselect_b32 s6, s2, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6 ; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s3 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s3, s6, s3 ; GFX6-NEXT: s_max_i32 s3, s6, s3
; GFX6-NEXT: s_cmp_lt_i32 s3, s5 ; GFX6-NEXT: s_min_i32 s3, s3, s5
; GFX6-NEXT: s_cselect_b32 s3, s3, s5
; GFX6-NEXT: s_add_i32 s2, s2, s3 ; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24 ; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_ashr_i32 s2, s2, 24 ; GFX6-NEXT: s_min_i32 s6, s3, 0
; GFX6-NEXT: s_max_i32 s5, s3, 0
; GFX6-NEXT: s_lshl_b32 s4, s7, 24 ; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s6, s3, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6 ; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s4 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s4, s6, s4 ; GFX6-NEXT: s_max_i32 s4, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5 ; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_movk_i32 s4, 0xff ; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_and_b32 s1, s1, s4 ; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 24
; GFX6-NEXT: s_and_b32 s0, s0, s4 ; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4 ; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 24 ; GFX6-NEXT: s_ashr_i32 s3, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s3, s4 ; GFX6-NEXT: s_and_b32 s1, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v4i8: ; GFX8-LABEL: s_saddsat_v4i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8 ; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshr_b32 s3, s0, 16 ; GFX8-NEXT: s_lshr_b32 s3, s0, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 24 ; GFX8-NEXT: s_lshr_b32 s4, s0, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, s8 ; GFX8-NEXT: s_lshl_b32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s11, s0
; GFX8-NEXT: s_sext_i32_i16 s12, 0
; GFX8-NEXT: s_max_i32 s13, s11, s12
; GFX8-NEXT: s_movk_i32 s10, 0x8000
; GFX8-NEXT: s_min_i32 s11, s11, s12
; GFX8-NEXT: s_sub_i32 s11, s10, s11
; GFX8-NEXT: s_lshr_b32 s5, s1, 8 ; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16 ; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24 ; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8 ; GFX8-NEXT: s_lshl_b32 s1, s1, s8
; GFX8-NEXT: s_sext_i32_i16 s11, s0
; GFX8-NEXT: s_sext_i32_i16 s12, 0
; GFX8-NEXT: s_cmp_gt_i32 s11, s12
; GFX8-NEXT: s_movk_i32 s9, 0x7fff ; GFX8-NEXT: s_movk_i32 s9, 0x7fff
; GFX8-NEXT: s_cselect_b32 s13, s11, s12
; GFX8-NEXT: s_sub_i32 s13, s9, s13
; GFX8-NEXT: s_cmp_lt_i32 s11, s12
; GFX8-NEXT: s_movk_i32 s10, 0x8000
; GFX8-NEXT: s_cselect_b32 s11, s11, s12
; GFX8-NEXT: s_sub_i32 s11, s10, s11
; GFX8-NEXT: s_sext_i32_i16 s11, s11 ; GFX8-NEXT: s_sext_i32_i16 s11, s11
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s11, s1 ; GFX8-NEXT: s_max_i32 s1, s11, s1
; GFX8-NEXT: s_cselect_b32 s1, s11, s1 ; GFX8-NEXT: s_sub_i32 s13, s9, s13
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s11, s13 ; GFX8-NEXT: s_sext_i32_i16 s11, s13
; GFX8-NEXT: s_cmp_lt_i32 s1, s11 ; GFX8-NEXT: s_min_i32 s1, s1, s11
; GFX8-NEXT: s_cselect_b32 s1, s1, s11
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_lshl_b32 s1, s2, s8 ; GFX8-NEXT: s_lshl_b32 s1, s2, s8
; GFX8-NEXT: s_lshl_b32 s2, s5, s8 ; GFX8-NEXT: s_lshl_b32 s2, s5, s8
; GFX8-NEXT: s_ashr_i32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s1 ; GFX8-NEXT: s_sext_i32_i16 s5, s1
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_max_i32 s11, s5, s12
; GFX8-NEXT: s_cselect_b32 s11, s5, s12 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s11, s9, s11
; GFX8-NEXT: s_cmp_lt_i32 s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s5, s2 ; GFX8-NEXT: s_max_i32 s2, s5, s2
; GFX8-NEXT: s_cselect_b32 s2, s5, s2 ; GFX8-NEXT: s_sub_i32 s11, s9, s11
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s5, s11 ; GFX8-NEXT: s_sext_i32_i16 s5, s11
; GFX8-NEXT: s_cmp_lt_i32 s2, s5 ; GFX8-NEXT: s_min_i32 s2, s2, s5
; GFX8-NEXT: s_cselect_b32 s2, s2, s5
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_lshl_b32 s2, s3, s8 ; GFX8-NEXT: s_lshl_b32 s2, s3, s8
; GFX8-NEXT: s_lshl_b32 s3, s6, s8
; GFX8-NEXT: s_ashr_i32 s1, s1, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s2 ; GFX8-NEXT: s_sext_i32_i16 s5, s2
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_lshl_b32 s3, s6, s8
; GFX8-NEXT: s_cselect_b32 s6, s5, s12 ; GFX8-NEXT: s_max_i32 s6, s5, s12
; GFX8-NEXT: s_sub_i32 s6, s9, s6 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_cmp_lt_i32 s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s5, s3 ; GFX8-NEXT: s_max_i32 s3, s5, s3
; GFX8-NEXT: s_cselect_b32 s3, s5, s3 ; GFX8-NEXT: s_sub_i32 s6, s9, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s5, s6 ; GFX8-NEXT: s_sext_i32_i16 s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s3, s5 ; GFX8-NEXT: s_min_i32 s3, s3, s5
; GFX8-NEXT: s_cselect_b32 s3, s3, s5
; GFX8-NEXT: s_add_i32 s2, s2, s3 ; GFX8-NEXT: s_add_i32 s2, s2, s3
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_lshl_b32 s3, s4, s8 ; GFX8-NEXT: s_lshl_b32 s3, s4, s8
; GFX8-NEXT: s_lshl_b32 s4, s7, s8
; GFX8-NEXT: s_ashr_i32 s2, s2, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s3 ; GFX8-NEXT: s_sext_i32_i16 s5, s3
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_max_i32 s6, s5, s12
; GFX8-NEXT: s_cselect_b32 s6, s5, s12 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s6, s9, s6 ; GFX8-NEXT: s_lshl_b32 s4, s7, s8
; GFX8-NEXT: s_cmp_lt_i32 s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s5, s4 ; GFX8-NEXT: s_max_i32 s4, s5, s4
; GFX8-NEXT: s_cselect_b32 s4, s5, s4 ; GFX8-NEXT: s_sub_i32 s6, s9, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s6 ; GFX8-NEXT: s_sext_i32_i16 s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s3, s3, s4 ; GFX8-NEXT: s_add_i32 s3, s3, s4
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s1, s1, s8
; GFX8-NEXT: s_movk_i32 s4, 0xff ; GFX8-NEXT: s_movk_i32 s4, 0xff
; GFX8-NEXT: s_ashr_i32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_and_b32 s1, s1, s4 ; GFX8-NEXT: s_and_b32 s1, s1, s4
; GFX8-NEXT: s_ashr_i32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s0, s0, s4 ; GFX8-NEXT: s_and_b32 s0, s0, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s2, s4 ; GFX8-NEXT: s_and_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_ashr_i32 s3, s3, s8 ; GFX8-NEXT: s_ashr_i32 s3, s3, s8
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs) %result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result ret i24 %result
} }
define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) { define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i24: ; GFX6-LABEL: s_saddsat_i24:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8 ; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_min_i32 s3, s0, 0
; GFX6-NEXT: s_max_i32 s2, s0, 0
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1 ; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cselect_b32 s1, s3, s1 ; GFX6-NEXT: s_max_i32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2 ; GFX6-NEXT: s_min_i32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 8 ; GFX6-NEXT: s_ashr_i32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_i24: ; GFX8-LABEL: s_saddsat_i24:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_i32 s2, s0, s1 ; GFX8-NEXT: s_add_i32 s2, s0, s1
; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000 ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_cmp_gt_i32 s3, s1 ; GCN-NEXT: s_cmp_gt_i32 s3, s1
; GCN-NEXT: s_cselect_b32 s1, s3, s1 ; GCN-NEXT: s_cselect_b32 s1, s3, s1
; GCN-NEXT: s_cmp_lt_i32 s1, s2 ; GCN-NEXT: s_cmp_lt_i32 s1, s2
; GCN-NEXT: s_cselect_b32 s1, s1, s2 ; GCN-NEXT: s_cselect_b32 s1, s1, s2
; GCN-NEXT: s_add_i32 s0, s0, s1 ; GCN-NEXT: s_add_i32 s0, s0, s1
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; GFX6-LABEL: s_saddsat_i32: ; GFX6-LABEL: s_saddsat_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_min_i32 s3, s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0 ; GFX6-NEXT: s_max_i32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1 ; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cselect_b32 s1, s3, s1 ; GFX6-NEXT: s_max_i32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2 ; GFX6-NEXT: s_min_i32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_i32: ; GFX8-LABEL: s_saddsat_i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0 ; GFX8-NEXT: s_min_i32 s3, s0, 0
; GFX8-NEXT: s_cselect_b32 s2, s0, 0 ; GFX8-NEXT: s_max_i32 s2, s0, 0
; GFX8-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_cselect_b32 s3, s0, 0
; GFX8-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX8-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX8-NEXT: s_cmp_gt_i32 s3, s1 ; GFX8-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX8-NEXT: s_cselect_b32 s1, s3, s1 ; GFX8-NEXT: s_max_i32 s1, s3, s1
; GFX8-NEXT: s_cmp_lt_i32 s1, s2 ; GFX8-NEXT: s_min_i32 s1, s1, s2
; GFX8-NEXT: s_cselect_b32 s1, s1, s2
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_i32: ; GFX9-LABEL: s_saddsat_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_saddsat_i32: ; GFX10-LABEL: s_saddsat_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp ; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result ret i32 %result
} }
define amdgpu_ps float @saddsat_i32_sv(i32 inreg %lhs, i32 %rhs) { define amdgpu_ps float @saddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX6-LABEL: saddsat_i32_sv: ; GFX6-LABEL: saddsat_i32_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_min_i32 s2, s0, 0
; GFX6-NEXT: s_cselect_b32 s1, s0, 0 ; GFX6-NEXT: s_max_i32 s1, s0, 0
; GFX6-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x80000000, s2 ; GFX6-NEXT: s_sub_i32 s2, 0x80000000, s2
; GFX6-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX6-NEXT: v_max_i32_e32 v0, s2, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s2, v0
; GFX6-NEXT: v_min_i32_e32 v0, s1, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: saddsat_i32_sv: ; GFX8-LABEL: saddsat_i32_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0 ; GFX8-NEXT: s_min_i32 s2, s0, 0
; GFX8-NEXT: s_cselect_b32 s1, s0, 0 ; GFX8-NEXT: s_max_i32 s1, s0, 0
; GFX8-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_cselect_b32 s2, s0, 0
; GFX8-NEXT: s_sub_i32 s2, 0x80000000, s2 ; GFX8-NEXT: s_sub_i32 s2, 0x80000000, s2
; GFX8-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX8-NEXT: v_max_i32_e32 v0, s2, v0 ; GFX8-NEXT: v_max_i32_e32 v0, s2, v0
; GFX8-NEXT: v_min_i32_e32 v0, s1, v0 ; GFX8-NEXT: v_min_i32_e32 v0, s1, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: saddsat_i32_sv: ; GFX9-LABEL: saddsat_i32_sv:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result ret <2 x i32> %result
} }
define amdgpu_ps <2 x i32> @s_saddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) { define amdgpu_ps <2 x i32> @s_saddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v2i32: ; GFX6-LABEL: s_saddsat_v2i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, 0
; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, 0 ; GFX6-NEXT: s_min_i32 s7, s0, 0
; GFX6-NEXT: s_sub_i32 s7, s5, s7 ; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s2, s7, s2 ; GFX6-NEXT: s_max_i32 s6, s0, 0
; GFX6-NEXT: s_cmp_lt_i32 s2, s6 ; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cselect_b32 s2, s2, s6 ; GFX6-NEXT: s_max_i32 s2, s7, s2
; GFX6-NEXT: s_min_i32 s2, s2, s6
; GFX6-NEXT: s_add_i32 s0, s0, s2 ; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s2, s1, 0
; GFX6-NEXT: s_cselect_b32 s2, s1, 0
; GFX6-NEXT: s_sub_i32 s2, s4, s2 ; GFX6-NEXT: s_sub_i32 s2, s4, s2
; GFX6-NEXT: s_cmp_lt_i32 s1, 0 ; GFX6-NEXT: s_min_i32 s4, s1, 0
; GFX6-NEXT: s_cselect_b32 s4, s1, 0
; GFX6-NEXT: s_sub_i32 s4, s5, s4 ; GFX6-NEXT: s_sub_i32 s4, s5, s4
; GFX6-NEXT: s_cmp_gt_i32 s4, s3 ; GFX6-NEXT: s_max_i32 s3, s4, s3
; GFX6-NEXT: s_cselect_b32 s3, s4, s3 ; GFX6-NEXT: s_min_i32 s2, s3, s2
; GFX6-NEXT: s_cmp_lt_i32 s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v2i32: ; GFX8-LABEL: s_saddsat_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: s_cselect_b32 s6, s0, 0
; GFX8-NEXT: s_sub_i32 s6, s4, s6
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s5, 1 ; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: s_cselect_b32 s7, s0, 0 ; GFX8-NEXT: s_min_i32 s7, s0, 0
; GFX8-NEXT: s_sub_i32 s7, s5, s7 ; GFX8-NEXT: s_sub_i32 s7, s5, s7
; GFX8-NEXT: s_cmp_gt_i32 s7, s2 ; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: s_cselect_b32 s2, s7, s2 ; GFX8-NEXT: s_max_i32 s6, s0, 0
; GFX8-NEXT: s_cmp_lt_i32 s2, s6 ; GFX8-NEXT: s_sub_i32 s6, s4, s6
; GFX8-NEXT: s_cselect_b32 s2, s2, s6 ; GFX8-NEXT: s_max_i32 s2, s7, s2
; GFX8-NEXT: s_min_i32 s2, s2, s6
; GFX8-NEXT: s_add_i32 s0, s0, s2 ; GFX8-NEXT: s_add_i32 s0, s0, s2
; GFX8-NEXT: s_cmp_gt_i32 s1, 0 ; GFX8-NEXT: s_max_i32 s2, s1, 0
; GFX8-NEXT: s_cselect_b32 s2, s1, 0
; GFX8-NEXT: s_sub_i32 s2, s4, s2 ; GFX8-NEXT: s_sub_i32 s2, s4, s2
; GFX8-NEXT: s_cmp_lt_i32 s1, 0 ; GFX8-NEXT: s_min_i32 s4, s1, 0
; GFX8-NEXT: s_cselect_b32 s4, s1, 0
; GFX8-NEXT: s_sub_i32 s4, s5, s4 ; GFX8-NEXT: s_sub_i32 s4, s5, s4
; GFX8-NEXT: s_cmp_gt_i32 s4, s3 ; GFX8-NEXT: s_max_i32 s3, s4, s3
; GFX8-NEXT: s_cselect_b32 s3, s4, s3 ; GFX8-NEXT: s_min_i32 s2, s3, s2
; GFX8-NEXT: s_cmp_lt_i32 s3, s2
; GFX8-NEXT: s_cselect_b32 s2, s3, s2
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v2i32: ; GFX9-LABEL: s_saddsat_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp ; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) %result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result ret <3 x i32> %result
} }
define amdgpu_ps <3 x i32> @s_saddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) { define amdgpu_ps <3 x i32> @s_saddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v3i32: ; GFX6-LABEL: s_saddsat_v3i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s6, -2
; GFX6-NEXT: s_cselect_b32 s8, s0, 0
; GFX6-NEXT: s_sub_i32 s8, s6, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s7, 1 ; GFX6-NEXT: s_brev_b32 s7, 1
; GFX6-NEXT: s_cselect_b32 s9, s0, 0 ; GFX6-NEXT: s_min_i32 s9, s0, 0
; GFX6-NEXT: s_sub_i32 s9, s7, s9 ; GFX6-NEXT: s_sub_i32 s9, s7, s9
; GFX6-NEXT: s_cmp_gt_i32 s9, s3 ; GFX6-NEXT: s_brev_b32 s6, -2
; GFX6-NEXT: s_cselect_b32 s3, s9, s3 ; GFX6-NEXT: s_max_i32 s8, s0, 0
; GFX6-NEXT: s_cmp_lt_i32 s3, s8 ; GFX6-NEXT: s_sub_i32 s8, s6, s8
; GFX6-NEXT: s_cselect_b32 s3, s3, s8 ; GFX6-NEXT: s_max_i32 s3, s9, s3
; GFX6-NEXT: s_min_i32 s3, s3, s8
; GFX6-NEXT: s_min_i32 s8, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s3 ; GFX6-NEXT: s_add_i32 s0, s0, s3
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s3, s1, 0
; GFX6-NEXT: s_cselect_b32 s3, s1, 0
; GFX6-NEXT: s_sub_i32 s3, s6, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s8, s1, 0
; GFX6-NEXT: s_sub_i32 s8, s7, s8 ; GFX6-NEXT: s_sub_i32 s8, s7, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s4
; GFX6-NEXT: s_cselect_b32 s4, s8, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s3
; GFX6-NEXT: s_cselect_b32 s3, s4, s3
; GFX6-NEXT: s_add_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_gt_i32 s2, 0
; GFX6-NEXT: s_cselect_b32 s3, s2, 0
; GFX6-NEXT: s_sub_i32 s3, s6, s3 ; GFX6-NEXT: s_sub_i32 s3, s6, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s4, s8, s4
; GFX6-NEXT: s_cselect_b32 s4, s2, 0 ; GFX6-NEXT: s_min_i32 s3, s4, s3
; GFX6-NEXT: s_min_i32 s4, s2, 0
; GFX6-NEXT: s_sub_i32 s4, s7, s4 ; GFX6-NEXT: s_sub_i32 s4, s7, s4
; GFX6-NEXT: s_cmp_gt_i32 s4, s5 ; GFX6-NEXT: s_add_i32 s1, s1, s3
; GFX6-NEXT: s_cselect_b32 s4, s4, s5 ; GFX6-NEXT: s_max_i32 s3, s2, 0
; GFX6-NEXT: s_cmp_lt_i32 s4, s3 ; GFX6-NEXT: s_sub_i32 s3, s6, s3
; GFX6-NEXT: s_cselect_b32 s3, s4, s3 ; GFX6-NEXT: s_max_i32 s4, s4, s5
; GFX6-NEXT: s_min_i32 s3, s4, s3
; GFX6-NEXT: s_add_i32 s2, s2, s3 ; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v3i32: ; GFX8-LABEL: s_saddsat_v3i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s6, -2
; GFX8-NEXT: s_cselect_b32 s8, s0, 0
; GFX8-NEXT: s_sub_i32 s8, s6, s8
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s7, 1 ; GFX8-NEXT: s_brev_b32 s7, 1
; GFX8-NEXT: s_cselect_b32 s9, s0, 0 ; GFX8-NEXT: s_min_i32 s9, s0, 0
; GFX8-NEXT: s_sub_i32 s9, s7, s9 ; GFX8-NEXT: s_sub_i32 s9, s7, s9
; GFX8-NEXT: s_cmp_gt_i32 s9, s3 ; GFX8-NEXT: s_brev_b32 s6, -2
; GFX8-NEXT: s_cselect_b32 s3, s9, s3 ; GFX8-NEXT: s_max_i32 s8, s0, 0
; GFX8-NEXT: s_cmp_lt_i32 s3, s8 ; GFX8-NEXT: s_sub_i32 s8, s6, s8
; GFX8-NEXT: s_cselect_b32 s3, s3, s8 ; GFX8-NEXT: s_max_i32 s3, s9, s3
; GFX8-NEXT: s_min_i32 s3, s3, s8
; GFX8-NEXT: s_min_i32 s8, s1, 0
; GFX8-NEXT: s_add_i32 s0, s0, s3 ; GFX8-NEXT: s_add_i32 s0, s0, s3
; GFX8-NEXT: s_cmp_gt_i32 s1, 0 ; GFX8-NEXT: s_max_i32 s3, s1, 0
; GFX8-NEXT: s_cselect_b32 s3, s1, 0
; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_cmp_lt_i32 s1, 0
; GFX8-NEXT: s_cselect_b32 s8, s1, 0
; GFX8-NEXT: s_sub_i32 s8, s7, s8 ; GFX8-NEXT: s_sub_i32 s8, s7, s8
; GFX8-NEXT: s_cmp_gt_i32 s8, s4
; GFX8-NEXT: s_cselect_b32 s4, s8, s4
; GFX8-NEXT: s_cmp_lt_i32 s4, s3
; GFX8-NEXT: s_cselect_b32 s3, s4, s3
; GFX8-NEXT: s_add_i32 s1, s1, s3
; GFX8-NEXT: s_cmp_gt_i32 s2, 0
; GFX8-NEXT: s_cselect_b32 s3, s2, 0
; GFX8-NEXT: s_sub_i32 s3, s6, s3 ; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_cmp_lt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s4, s8, s4
; GFX8-NEXT: s_cselect_b32 s4, s2, 0 ; GFX8-NEXT: s_min_i32 s3, s4, s3
; GFX8-NEXT: s_min_i32 s4, s2, 0
; GFX8-NEXT: s_sub_i32 s4, s7, s4 ; GFX8-NEXT: s_sub_i32 s4, s7, s4
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_add_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_max_i32 s3, s2, 0
; GFX8-NEXT: s_cmp_lt_i32 s4, s3 ; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_cselect_b32 s3, s4, s3 ; GFX8-NEXT: s_max_i32 s4, s4, s5
; GFX8-NEXT: s_min_i32 s3, s4, s3
; GFX8-NEXT: s_add_i32 s2, s2, s3 ; GFX8-NEXT: s_add_i32 s2, s2, s3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v3i32: ; GFX9-LABEL: s_saddsat_v3i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s5
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) %result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result ret <4 x i32> %result
} }
define amdgpu_ps <4 x i32> @s_saddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) { define amdgpu_ps <4 x i32> @s_saddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v4i32: ; GFX6-LABEL: s_saddsat_v4i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, 0
; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s9, 1 ; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, 0 ; GFX6-NEXT: s_min_i32 s11, s0, 0
; GFX6-NEXT: s_sub_i32 s11, s9, s11 ; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_cmp_gt_i32 s11, s4 ; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s4, s11, s4 ; GFX6-NEXT: s_max_i32 s10, s0, 0
; GFX6-NEXT: s_cmp_lt_i32 s4, s10 ; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s10 ; GFX6-NEXT: s_max_i32 s4, s11, s4
; GFX6-NEXT: s_min_i32 s4, s4, s10
; GFX6-NEXT: s_min_i32 s10, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s4 ; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s4, s1, 0
; GFX6-NEXT: s_cselect_b32 s4, s1, 0
; GFX6-NEXT: s_sub_i32 s4, s8, s4
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s10, s1, 0
; GFX6-NEXT: s_sub_i32 s10, s9, s10 ; GFX6-NEXT: s_sub_i32 s10, s9, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s5 ; GFX6-NEXT: s_sub_i32 s4, s8, s4
; GFX6-NEXT: s_cselect_b32 s5, s10, s5 ; GFX6-NEXT: s_max_i32 s5, s10, s5
; GFX6-NEXT: s_cmp_lt_i32 s5, s4 ; GFX6-NEXT: s_min_i32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4 ; GFX6-NEXT: s_min_i32 s5, s2, 0
; GFX6-NEXT: s_sub_i32 s5, s9, s5
; GFX6-NEXT: s_add_i32 s1, s1, s4 ; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s4, s2, 0
; GFX6-NEXT: s_cselect_b32 s4, s2, 0
; GFX6-NEXT: s_sub_i32 s4, s8, s4 ; GFX6-NEXT: s_sub_i32 s4, s8, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s5, s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s2, 0 ; GFX6-NEXT: s_min_i32 s4, s5, s4
; GFX6-NEXT: s_min_i32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s9, s5 ; GFX6-NEXT: s_sub_i32 s5, s9, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_gt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s4, s3, 0
; GFX6-NEXT: s_cselect_b32 s4, s3, 0
; GFX6-NEXT: s_sub_i32 s4, s8, s4 ; GFX6-NEXT: s_sub_i32 s4, s8, s4
; GFX6-NEXT: s_cmp_lt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s5, s5, s7
; GFX6-NEXT: s_cselect_b32 s5, s3, 0 ; GFX6-NEXT: s_min_i32 s4, s5, s4
; GFX6-NEXT: s_sub_i32 s5, s9, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s7
; GFX6-NEXT: s_cselect_b32 s5, s5, s7
; GFX6-NEXT: s_cmp_lt_i32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v4i32: ; GFX8-LABEL: s_saddsat_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s8, -2
; GFX8-NEXT: s_cselect_b32 s10, s0, 0
; GFX8-NEXT: s_sub_i32 s10, s8, s10
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s9, 1 ; GFX8-NEXT: s_brev_b32 s9, 1
; GFX8-NEXT: s_cselect_b32 s11, s0, 0 ; GFX8-NEXT: s_min_i32 s11, s0, 0
; GFX8-NEXT: s_sub_i32 s11, s9, s11 ; GFX8-NEXT: s_sub_i32 s11, s9, s11
; GFX8-NEXT: s_cmp_gt_i32 s11, s4 ; GFX8-NEXT: s_brev_b32 s8, -2
; GFX8-NEXT: s_cselect_b32 s4, s11, s4 ; GFX8-NEXT: s_max_i32 s10, s0, 0
; GFX8-NEXT: s_cmp_lt_i32 s4, s10 ; GFX8-NEXT: s_sub_i32 s10, s8, s10
; GFX8-NEXT: s_cselect_b32 s4, s4, s10 ; GFX8-NEXT: s_max_i32 s4, s11, s4
; GFX8-NEXT: s_min_i32 s4, s4, s10
; GFX8-NEXT: s_min_i32 s10, s1, 0
; GFX8-NEXT: s_add_i32 s0, s0, s4 ; GFX8-NEXT: s_add_i32 s0, s0, s4
; GFX8-NEXT: s_cmp_gt_i32 s1, 0 ; GFX8-NEXT: s_max_i32 s4, s1, 0
; GFX8-NEXT: s_cselect_b32 s4, s1, 0
; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_cmp_lt_i32 s1, 0
; GFX8-NEXT: s_cselect_b32 s10, s1, 0
; GFX8-NEXT: s_sub_i32 s10, s9, s10 ; GFX8-NEXT: s_sub_i32 s10, s9, s10
; GFX8-NEXT: s_cmp_gt_i32 s10, s5 ; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_cselect_b32 s5, s10, s5 ; GFX8-NEXT: s_max_i32 s5, s10, s5
; GFX8-NEXT: s_cmp_lt_i32 s5, s4 ; GFX8-NEXT: s_min_i32 s4, s5, s4
; GFX8-NEXT: s_cselect_b32 s4, s5, s4 ; GFX8-NEXT: s_min_i32 s5, s2, 0
; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_add_i32 s1, s1, s4 ; GFX8-NEXT: s_add_i32 s1, s1, s4
; GFX8-NEXT: s_cmp_gt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s4, s2, 0
; GFX8-NEXT: s_cselect_b32 s4, s2, 0
; GFX8-NEXT: s_sub_i32 s4, s8, s4 ; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_cmp_lt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s5, s5, s6
; GFX8-NEXT: s_cselect_b32 s5, s2, 0 ; GFX8-NEXT: s_min_i32 s4, s5, s4
; GFX8-NEXT: s_min_i32 s5, s3, 0
; GFX8-NEXT: s_sub_i32 s5, s9, s5 ; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_cmp_gt_i32 s5, s6
; GFX8-NEXT: s_cselect_b32 s5, s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s4
; GFX8-NEXT: s_cselect_b32 s4, s5, s4
; GFX8-NEXT: s_add_i32 s2, s2, s4 ; GFX8-NEXT: s_add_i32 s2, s2, s4
; GFX8-NEXT: s_cmp_gt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s4, s3, 0
; GFX8-NEXT: s_cselect_b32 s4, s3, 0
; GFX8-NEXT: s_sub_i32 s4, s8, s4 ; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s5, s5, s7
; GFX8-NEXT: s_cselect_b32 s5, s3, 0 ; GFX8-NEXT: s_min_i32 s4, s5, s4
; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_cmp_gt_i32 s5, s7
; GFX8-NEXT: s_cselect_b32 s5, s5, s7
; GFX8-NEXT: s_cmp_lt_i32 s5, s4
; GFX8-NEXT: s_cselect_b32 s4, s5, s4
; GFX8-NEXT: s_add_i32 s3, s3, s4 ; GFX8-NEXT: s_add_i32 s3, s3, s4
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v4i32: ; GFX9-LABEL: s_saddsat_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define amdgpu_ps <5 x i32> @s_saddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) { define amdgpu_ps <5 x i32> @s_saddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v5i32: ; GFX6-LABEL: s_saddsat_v5i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s10, -2
; GFX6-NEXT: s_cselect_b32 s12, s0, 0
; GFX6-NEXT: s_sub_i32 s12, s10, s12
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s11, 1 ; GFX6-NEXT: s_brev_b32 s11, 1
; GFX6-NEXT: s_cselect_b32 s13, s0, 0 ; GFX6-NEXT: s_min_i32 s13, s0, 0
; GFX6-NEXT: s_sub_i32 s13, s11, s13 ; GFX6-NEXT: s_sub_i32 s13, s11, s13
; GFX6-NEXT: s_cmp_gt_i32 s13, s5 ; GFX6-NEXT: s_brev_b32 s10, -2
; GFX6-NEXT: s_cselect_b32 s5, s13, s5 ; GFX6-NEXT: s_max_i32 s12, s0, 0
; GFX6-NEXT: s_cmp_lt_i32 s5, s12 ; GFX6-NEXT: s_sub_i32 s12, s10, s12
; GFX6-NEXT: s_cselect_b32 s5, s5, s12 ; GFX6-NEXT: s_max_i32 s5, s13, s5
; GFX6-NEXT: s_min_i32 s5, s5, s12
; GFX6-NEXT: s_min_i32 s12, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s5 ; GFX6-NEXT: s_add_i32 s0, s0, s5
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s5, s1, 0
; GFX6-NEXT: s_cselect_b32 s5, s1, 0
; GFX6-NEXT: s_sub_i32 s5, s10, s5
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s12, s1, 0
; GFX6-NEXT: s_sub_i32 s12, s11, s12 ; GFX6-NEXT: s_sub_i32 s12, s11, s12
; GFX6-NEXT: s_cmp_gt_i32 s12, s6 ; GFX6-NEXT: s_sub_i32 s5, s10, s5
; GFX6-NEXT: s_cselect_b32 s6, s12, s6 ; GFX6-NEXT: s_max_i32 s6, s12, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s5 ; GFX6-NEXT: s_min_i32 s5, s6, s5
; GFX6-NEXT: s_cselect_b32 s5, s6, s5 ; GFX6-NEXT: s_min_i32 s6, s2, 0
; GFX6-NEXT: s_sub_i32 s6, s11, s6
; GFX6-NEXT: s_add_i32 s1, s1, s5 ; GFX6-NEXT: s_add_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s5, s2, 0
; GFX6-NEXT: s_cselect_b32 s5, s2, 0
; GFX6-NEXT: s_sub_i32 s5, s10, s5 ; GFX6-NEXT: s_sub_i32 s5, s10, s5
; GFX6-NEXT: s_cmp_lt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s6, s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s2, 0 ; GFX6-NEXT: s_min_i32 s5, s6, s5
; GFX6-NEXT: s_min_i32 s6, s3, 0
; GFX6-NEXT: s_sub_i32 s6, s11, s6 ; GFX6-NEXT: s_sub_i32 s6, s11, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_cmp_lt_i32 s6, s5
; GFX6-NEXT: s_cselect_b32 s5, s6, s5
; GFX6-NEXT: s_add_i32 s2, s2, s5 ; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: s_cmp_gt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s5, s3, 0
; GFX6-NEXT: s_cselect_b32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s10, s5 ; GFX6-NEXT: s_sub_i32 s5, s10, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s6, s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s3, 0 ; GFX6-NEXT: s_min_i32 s5, s6, s5
; GFX6-NEXT: s_min_i32 s6, s4, 0
; GFX6-NEXT: s_sub_i32 s6, s11, s6 ; GFX6-NEXT: s_sub_i32 s6, s11, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_cmp_lt_i32 s6, s5
; GFX6-NEXT: s_cselect_b32 s5, s6, s5
; GFX6-NEXT: s_add_i32 s3, s3, s5 ; GFX6-NEXT: s_add_i32 s3, s3, s5
; GFX6-NEXT: s_cmp_gt_i32 s4, 0 ; GFX6-NEXT: s_max_i32 s5, s4, 0
; GFX6-NEXT: s_cselect_b32 s5, s4, 0
; GFX6-NEXT: s_sub_i32 s5, s10, s5 ; GFX6-NEXT: s_sub_i32 s5, s10, s5
; GFX6-NEXT: s_cmp_lt_i32 s4, 0 ; GFX6-NEXT: s_max_i32 s6, s6, s9
; GFX6-NEXT: s_cselect_b32 s6, s4, 0 ; GFX6-NEXT: s_min_i32 s5, s6, s5
; GFX6-NEXT: s_sub_i32 s6, s11, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s9
; GFX6-NEXT: s_cselect_b32 s6, s6, s9
; GFX6-NEXT: s_cmp_lt_i32 s6, s5
; GFX6-NEXT: s_cselect_b32 s5, s6, s5
; GFX6-NEXT: s_add_i32 s4, s4, s5 ; GFX6-NEXT: s_add_i32 s4, s4, s5
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v5i32: ; GFX8-LABEL: s_saddsat_v5i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s10, -2
; GFX8-NEXT: s_cselect_b32 s12, s0, 0
; GFX8-NEXT: s_sub_i32 s12, s10, s12
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s11, 1 ; GFX8-NEXT: s_brev_b32 s11, 1
; GFX8-NEXT: s_cselect_b32 s13, s0, 0 ; GFX8-NEXT: s_min_i32 s13, s0, 0
; GFX8-NEXT: s_sub_i32 s13, s11, s13 ; GFX8-NEXT: s_sub_i32 s13, s11, s13
; GFX8-NEXT: s_cmp_gt_i32 s13, s5 ; GFX8-NEXT: s_brev_b32 s10, -2
; GFX8-NEXT: s_cselect_b32 s5, s13, s5 ; GFX8-NEXT: s_max_i32 s12, s0, 0
; GFX8-NEXT: s_cmp_lt_i32 s5, s12 ; GFX8-NEXT: s_sub_i32 s12, s10, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12 ; GFX8-NEXT: s_max_i32 s5, s13, s5
; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_min_i32 s12, s1, 0
; GFX8-NEXT: s_add_i32 s0, s0, s5 ; GFX8-NEXT: s_add_i32 s0, s0, s5
; GFX8-NEXT: s_cmp_gt_i32 s1, 0 ; GFX8-NEXT: s_max_i32 s5, s1, 0
; GFX8-NEXT: s_cselect_b32 s5, s1, 0
; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_cmp_lt_i32 s1, 0
; GFX8-NEXT: s_cselect_b32 s12, s1, 0
; GFX8-NEXT: s_sub_i32 s12, s11, s12 ; GFX8-NEXT: s_sub_i32 s12, s11, s12
; GFX8-NEXT: s_cmp_gt_i32 s12, s6 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_cselect_b32 s6, s12, s6 ; GFX8-NEXT: s_max_i32 s6, s12, s6
; GFX8-NEXT: s_cmp_lt_i32 s6, s5 ; GFX8-NEXT: s_min_i32 s5, s6, s5
; GFX8-NEXT: s_cselect_b32 s5, s6, s5 ; GFX8-NEXT: s_min_i32 s6, s2, 0
; GFX8-NEXT: s_sub_i32 s6, s11, s6
; GFX8-NEXT: s_add_i32 s1, s1, s5 ; GFX8-NEXT: s_add_i32 s1, s1, s5
; GFX8-NEXT: s_cmp_gt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s5, s2, 0
; GFX8-NEXT: s_cselect_b32 s5, s2, 0
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_cmp_lt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s6, s6, s7
; GFX8-NEXT: s_cselect_b32 s6, s2, 0 ; GFX8-NEXT: s_min_i32 s5, s6, s5
; GFX8-NEXT: s_min_i32 s6, s3, 0
; GFX8-NEXT: s_sub_i32 s6, s11, s6 ; GFX8-NEXT: s_sub_i32 s6, s11, s6
; GFX8-NEXT: s_cmp_gt_i32 s6, s7
; GFX8-NEXT: s_cselect_b32 s6, s6, s7
; GFX8-NEXT: s_cmp_lt_i32 s6, s5
; GFX8-NEXT: s_cselect_b32 s5, s6, s5
; GFX8-NEXT: s_add_i32 s2, s2, s5 ; GFX8-NEXT: s_add_i32 s2, s2, s5
; GFX8-NEXT: s_cmp_gt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s5, s3, 0
; GFX8-NEXT: s_cselect_b32 s5, s3, 0
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_cmp_lt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s6, s6, s8
; GFX8-NEXT: s_cselect_b32 s6, s3, 0 ; GFX8-NEXT: s_min_i32 s5, s6, s5
; GFX8-NEXT: s_min_i32 s6, s4, 0
; GFX8-NEXT: s_sub_i32 s6, s11, s6 ; GFX8-NEXT: s_sub_i32 s6, s11, s6
; GFX8-NEXT: s_cmp_gt_i32 s6, s8
; GFX8-NEXT: s_cselect_b32 s6, s6, s8
; GFX8-NEXT: s_cmp_lt_i32 s6, s5
; GFX8-NEXT: s_cselect_b32 s5, s6, s5
; GFX8-NEXT: s_add_i32 s3, s3, s5 ; GFX8-NEXT: s_add_i32 s3, s3, s5
; GFX8-NEXT: s_cmp_gt_i32 s4, 0 ; GFX8-NEXT: s_max_i32 s5, s4, 0
; GFX8-NEXT: s_cselect_b32 s5, s4, 0
; GFX8-NEXT: s_sub_i32 s5, s10, s5 ; GFX8-NEXT: s_sub_i32 s5, s10, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, 0 ; GFX8-NEXT: s_max_i32 s6, s6, s9
; GFX8-NEXT: s_cselect_b32 s6, s4, 0 ; GFX8-NEXT: s_min_i32 s5, s6, s5
; GFX8-NEXT: s_sub_i32 s6, s11, s6
; GFX8-NEXT: s_cmp_gt_i32 s6, s9
; GFX8-NEXT: s_cselect_b32 s6, s6, s9
; GFX8-NEXT: s_cmp_lt_i32 s6, s5
; GFX8-NEXT: s_cselect_b32 s5, s6, s5
; GFX8-NEXT: s_add_i32 s4, s4, s5 ; GFX8-NEXT: s_add_i32 s4, s4, s5
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v5i32: ; GFX9-LABEL: s_saddsat_v5i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v16i32: ; GFX6-LABEL: s_saddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s32, -2
; GFX6-NEXT: s_cselect_b32 s34, s0, 0
; GFX6-NEXT: s_sub_i32 s34, s32, s34
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s33, 1 ; GFX6-NEXT: s_brev_b32 s33, 1
; GFX6-NEXT: s_cselect_b32 s35, s0, 0 ; GFX6-NEXT: s_min_i32 s35, s0, 0
; GFX6-NEXT: s_sub_i32 s35, s33, s35 ; GFX6-NEXT: s_sub_i32 s35, s33, s35
; GFX6-NEXT: s_cmp_gt_i32 s35, s16 ; GFX6-NEXT: s_brev_b32 s32, -2
; GFX6-NEXT: s_cselect_b32 s16, s35, s16 ; GFX6-NEXT: s_max_i32 s34, s0, 0
; GFX6-NEXT: s_cmp_lt_i32 s16, s34 ; GFX6-NEXT: s_sub_i32 s34, s32, s34
; GFX6-NEXT: s_cselect_b32 s16, s16, s34 ; GFX6-NEXT: s_max_i32 s16, s35, s16
; GFX6-NEXT: s_min_i32 s16, s16, s34
; GFX6-NEXT: s_min_i32 s34, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s16 ; GFX6-NEXT: s_add_i32 s0, s0, s16
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s16, s1, 0
; GFX6-NEXT: s_cselect_b32 s16, s1, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s34, s1, 0
; GFX6-NEXT: s_sub_i32 s34, s33, s34 ; GFX6-NEXT: s_sub_i32 s34, s33, s34
; GFX6-NEXT: s_cmp_gt_i32 s34, s17 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cselect_b32 s17, s34, s17 ; GFX6-NEXT: s_max_i32 s17, s34, s17
; GFX6-NEXT: s_cmp_lt_i32 s17, s16 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16 ; GFX6-NEXT: s_min_i32 s17, s2, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_add_i32 s1, s1, s16 ; GFX6-NEXT: s_add_i32 s1, s1, s16
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s16, s2, 0
; GFX6-NEXT: s_cselect_b32 s16, s2, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s2, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s18
; GFX6-NEXT: s_cselect_b32 s17, s2, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s3, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s18
; GFX6-NEXT: s_cselect_b32 s17, s17, s18
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s2, s2, s16 ; GFX6-NEXT: s_add_i32 s2, s2, s16
; GFX6-NEXT: s_cmp_gt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s16, s3, 0
; GFX6-NEXT: s_cselect_b32 s16, s3, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s3, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s19
; GFX6-NEXT: s_cselect_b32 s17, s3, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s4, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s19
; GFX6-NEXT: s_cselect_b32 s17, s17, s19
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s3, s3, s16 ; GFX6-NEXT: s_add_i32 s3, s3, s16
; GFX6-NEXT: s_cmp_gt_i32 s4, 0 ; GFX6-NEXT: s_max_i32 s16, s4, 0
; GFX6-NEXT: s_cselect_b32 s16, s4, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s4, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s20
; GFX6-NEXT: s_cselect_b32 s17, s4, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s5, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s20
; GFX6-NEXT: s_cselect_b32 s17, s17, s20
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s4, s4, s16 ; GFX6-NEXT: s_add_i32 s4, s4, s16
; GFX6-NEXT: s_cmp_gt_i32 s5, 0 ; GFX6-NEXT: s_max_i32 s16, s5, 0
; GFX6-NEXT: s_cselect_b32 s16, s5, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s5, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s21
; GFX6-NEXT: s_cselect_b32 s17, s5, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s6, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s21
; GFX6-NEXT: s_cselect_b32 s17, s17, s21
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s5, s5, s16 ; GFX6-NEXT: s_add_i32 s5, s5, s16
; GFX6-NEXT: s_cmp_gt_i32 s6, 0 ; GFX6-NEXT: s_max_i32 s16, s6, 0
; GFX6-NEXT: s_cselect_b32 s16, s6, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s6, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s22
; GFX6-NEXT: s_cselect_b32 s17, s6, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s7, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s22
; GFX6-NEXT: s_cselect_b32 s17, s17, s22
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s6, s6, s16 ; GFX6-NEXT: s_add_i32 s6, s6, s16
; GFX6-NEXT: s_cmp_gt_i32 s7, 0 ; GFX6-NEXT: s_max_i32 s16, s7, 0
; GFX6-NEXT: s_cselect_b32 s16, s7, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s7, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s23
; GFX6-NEXT: s_cselect_b32 s17, s7, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s8, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s23
; GFX6-NEXT: s_cselect_b32 s17, s17, s23
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s7, s7, s16 ; GFX6-NEXT: s_add_i32 s7, s7, s16
; GFX6-NEXT: s_cmp_gt_i32 s8, 0 ; GFX6-NEXT: s_max_i32 s16, s8, 0
; GFX6-NEXT: s_cselect_b32 s16, s8, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s8, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s24
; GFX6-NEXT: s_cselect_b32 s17, s8, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s9, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s24
; GFX6-NEXT: s_cselect_b32 s17, s17, s24
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s8, s8, s16 ; GFX6-NEXT: s_add_i32 s8, s8, s16
; GFX6-NEXT: s_cmp_gt_i32 s9, 0 ; GFX6-NEXT: s_max_i32 s16, s9, 0
; GFX6-NEXT: s_cselect_b32 s16, s9, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s9, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s25
; GFX6-NEXT: s_cselect_b32 s17, s9, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s10, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s25
; GFX6-NEXT: s_cselect_b32 s17, s17, s25
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s9, s9, s16 ; GFX6-NEXT: s_add_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_gt_i32 s10, 0 ; GFX6-NEXT: s_max_i32 s16, s10, 0
; GFX6-NEXT: s_cselect_b32 s16, s10, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s10, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s26
; GFX6-NEXT: s_cselect_b32 s17, s10, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s11, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s26
; GFX6-NEXT: s_cselect_b32 s17, s17, s26
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s10, s10, s16 ; GFX6-NEXT: s_add_i32 s10, s10, s16
; GFX6-NEXT: s_cmp_gt_i32 s11, 0 ; GFX6-NEXT: s_max_i32 s16, s11, 0
; GFX6-NEXT: s_cselect_b32 s16, s11, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s11, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s27
; GFX6-NEXT: s_cselect_b32 s17, s11, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s12, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s27
; GFX6-NEXT: s_cselect_b32 s17, s17, s27
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s11, s11, s16 ; GFX6-NEXT: s_add_i32 s11, s11, s16
; GFX6-NEXT: s_cmp_gt_i32 s12, 0 ; GFX6-NEXT: s_max_i32 s16, s12, 0
; GFX6-NEXT: s_cselect_b32 s16, s12, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s12, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s28
; GFX6-NEXT: s_cselect_b32 s17, s12, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s13, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s28
; GFX6-NEXT: s_cselect_b32 s17, s17, s28
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s12, s12, s16 ; GFX6-NEXT: s_add_i32 s12, s12, s16
; GFX6-NEXT: s_cmp_gt_i32 s13, 0 ; GFX6-NEXT: s_max_i32 s16, s13, 0
; GFX6-NEXT: s_cselect_b32 s16, s13, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s13, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s29
; GFX6-NEXT: s_cselect_b32 s17, s13, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s14, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s29
; GFX6-NEXT: s_cselect_b32 s17, s17, s29
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s13, s13, s16 ; GFX6-NEXT: s_add_i32 s13, s13, s16
; GFX6-NEXT: s_cmp_gt_i32 s14, 0 ; GFX6-NEXT: s_max_i32 s16, s14, 0
; GFX6-NEXT: s_cselect_b32 s16, s14, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s14, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s30
; GFX6-NEXT: s_cselect_b32 s17, s14, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_min_i32 s17, s15, 0
; GFX6-NEXT: s_sub_i32 s17, s33, s17 ; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s30
; GFX6-NEXT: s_cselect_b32 s17, s17, s30
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s14, s14, s16 ; GFX6-NEXT: s_add_i32 s14, s14, s16
; GFX6-NEXT: s_cmp_gt_i32 s15, 0 ; GFX6-NEXT: s_max_i32 s16, s15, 0
; GFX6-NEXT: s_cselect_b32 s16, s15, 0
; GFX6-NEXT: s_sub_i32 s16, s32, s16 ; GFX6-NEXT: s_sub_i32 s16, s32, s16
; GFX6-NEXT: s_cmp_lt_i32 s15, 0 ; GFX6-NEXT: s_max_i32 s17, s17, s31
; GFX6-NEXT: s_cselect_b32 s17, s15, 0 ; GFX6-NEXT: s_min_i32 s16, s17, s16
; GFX6-NEXT: s_sub_i32 s17, s33, s17
; GFX6-NEXT: s_cmp_gt_i32 s17, s31
; GFX6-NEXT: s_cselect_b32 s17, s17, s31
; GFX6-NEXT: s_cmp_lt_i32 s17, s16
; GFX6-NEXT: s_cselect_b32 s16, s17, s16
; GFX6-NEXT: s_add_i32 s15, s15, s16 ; GFX6-NEXT: s_add_i32 s15, s15, s16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v16i32: ; GFX8-LABEL: s_saddsat_v16i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s32, -2
; GFX8-NEXT: s_cselect_b32 s34, s0, 0
; GFX8-NEXT: s_sub_i32 s34, s32, s34
; GFX8-NEXT: s_cmp_lt_i32 s0, 0
; GFX8-NEXT: s_brev_b32 s33, 1 ; GFX8-NEXT: s_brev_b32 s33, 1
; GFX8-NEXT: s_cselect_b32 s35, s0, 0 ; GFX8-NEXT: s_min_i32 s35, s0, 0
; GFX8-NEXT: s_sub_i32 s35, s33, s35 ; GFX8-NEXT: s_sub_i32 s35, s33, s35
; GFX8-NEXT: s_cmp_gt_i32 s35, s16 ; GFX8-NEXT: s_brev_b32 s32, -2
; GFX8-NEXT: s_cselect_b32 s16, s35, s16 ; GFX8-NEXT: s_max_i32 s34, s0, 0
; GFX8-NEXT: s_cmp_lt_i32 s16, s34 ; GFX8-NEXT: s_sub_i32 s34, s32, s34
; GFX8-NEXT: s_cselect_b32 s16, s16, s34 ; GFX8-NEXT: s_max_i32 s16, s35, s16
; GFX8-NEXT: s_min_i32 s16, s16, s34
; GFX8-NEXT: s_min_i32 s34, s1, 0
; GFX8-NEXT: s_add_i32 s0, s0, s16 ; GFX8-NEXT: s_add_i32 s0, s0, s16
; GFX8-NEXT: s_cmp_gt_i32 s1, 0 ; GFX8-NEXT: s_max_i32 s16, s1, 0
; GFX8-NEXT: s_cselect_b32 s16, s1, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s1, 0
; GFX8-NEXT: s_cselect_b32 s34, s1, 0
; GFX8-NEXT: s_sub_i32 s34, s33, s34 ; GFX8-NEXT: s_sub_i32 s34, s33, s34
; GFX8-NEXT: s_cmp_gt_i32 s34, s17 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cselect_b32 s17, s34, s17 ; GFX8-NEXT: s_max_i32 s17, s34, s17
; GFX8-NEXT: s_cmp_lt_i32 s17, s16 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16 ; GFX8-NEXT: s_min_i32 s17, s2, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_add_i32 s1, s1, s16 ; GFX8-NEXT: s_add_i32 s1, s1, s16
; GFX8-NEXT: s_cmp_gt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s16, s2, 0
; GFX8-NEXT: s_cselect_b32 s16, s2, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s2, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s18
; GFX8-NEXT: s_cselect_b32 s17, s2, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s3, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s18
; GFX8-NEXT: s_cselect_b32 s17, s17, s18
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s2, s2, s16 ; GFX8-NEXT: s_add_i32 s2, s2, s16
; GFX8-NEXT: s_cmp_gt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s16, s3, 0
; GFX8-NEXT: s_cselect_b32 s16, s3, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s3, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s19
; GFX8-NEXT: s_cselect_b32 s17, s3, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s4, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s19
; GFX8-NEXT: s_cselect_b32 s17, s17, s19
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s3, s3, s16 ; GFX8-NEXT: s_add_i32 s3, s3, s16
; GFX8-NEXT: s_cmp_gt_i32 s4, 0 ; GFX8-NEXT: s_max_i32 s16, s4, 0
; GFX8-NEXT: s_cselect_b32 s16, s4, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s4, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s20
; GFX8-NEXT: s_cselect_b32 s17, s4, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s5, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s20
; GFX8-NEXT: s_cselect_b32 s17, s17, s20
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s4, s4, s16 ; GFX8-NEXT: s_add_i32 s4, s4, s16
; GFX8-NEXT: s_cmp_gt_i32 s5, 0 ; GFX8-NEXT: s_max_i32 s16, s5, 0
; GFX8-NEXT: s_cselect_b32 s16, s5, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s5, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s21
; GFX8-NEXT: s_cselect_b32 s17, s5, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s6, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s21
; GFX8-NEXT: s_cselect_b32 s17, s17, s21
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s5, s5, s16 ; GFX8-NEXT: s_add_i32 s5, s5, s16
; GFX8-NEXT: s_cmp_gt_i32 s6, 0 ; GFX8-NEXT: s_max_i32 s16, s6, 0
; GFX8-NEXT: s_cselect_b32 s16, s6, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s6, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s22
; GFX8-NEXT: s_cselect_b32 s17, s6, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s7, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s22
; GFX8-NEXT: s_cselect_b32 s17, s17, s22
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s6, s6, s16 ; GFX8-NEXT: s_add_i32 s6, s6, s16
; GFX8-NEXT: s_cmp_gt_i32 s7, 0 ; GFX8-NEXT: s_max_i32 s16, s7, 0
; GFX8-NEXT: s_cselect_b32 s16, s7, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s7, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s23
; GFX8-NEXT: s_cselect_b32 s17, s7, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s8, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s23
; GFX8-NEXT: s_cselect_b32 s17, s17, s23
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s7, s7, s16 ; GFX8-NEXT: s_add_i32 s7, s7, s16
; GFX8-NEXT: s_cmp_gt_i32 s8, 0 ; GFX8-NEXT: s_max_i32 s16, s8, 0
; GFX8-NEXT: s_cselect_b32 s16, s8, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s8, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s24
; GFX8-NEXT: s_cselect_b32 s17, s8, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s9, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s24
; GFX8-NEXT: s_cselect_b32 s17, s17, s24
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s8, s8, s16 ; GFX8-NEXT: s_add_i32 s8, s8, s16
; GFX8-NEXT: s_cmp_gt_i32 s9, 0 ; GFX8-NEXT: s_max_i32 s16, s9, 0
; GFX8-NEXT: s_cselect_b32 s16, s9, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s9, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s25
; GFX8-NEXT: s_cselect_b32 s17, s9, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s10, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s25
; GFX8-NEXT: s_cselect_b32 s17, s17, s25
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s9, s9, s16 ; GFX8-NEXT: s_add_i32 s9, s9, s16
; GFX8-NEXT: s_cmp_gt_i32 s10, 0 ; GFX8-NEXT: s_max_i32 s16, s10, 0
; GFX8-NEXT: s_cselect_b32 s16, s10, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s10, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s26
; GFX8-NEXT: s_cselect_b32 s17, s10, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s11, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s26
; GFX8-NEXT: s_cselect_b32 s17, s17, s26
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s10, s10, s16 ; GFX8-NEXT: s_add_i32 s10, s10, s16
; GFX8-NEXT: s_cmp_gt_i32 s11, 0 ; GFX8-NEXT: s_max_i32 s16, s11, 0
; GFX8-NEXT: s_cselect_b32 s16, s11, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s11, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s27
; GFX8-NEXT: s_cselect_b32 s17, s11, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s12, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s27
; GFX8-NEXT: s_cselect_b32 s17, s17, s27
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s11, s11, s16 ; GFX8-NEXT: s_add_i32 s11, s11, s16
; GFX8-NEXT: s_cmp_gt_i32 s12, 0 ; GFX8-NEXT: s_max_i32 s16, s12, 0
; GFX8-NEXT: s_cselect_b32 s16, s12, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s12, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s28
; GFX8-NEXT: s_cselect_b32 s17, s12, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s13, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s28
; GFX8-NEXT: s_cselect_b32 s17, s17, s28
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s12, s12, s16 ; GFX8-NEXT: s_add_i32 s12, s12, s16
; GFX8-NEXT: s_cmp_gt_i32 s13, 0 ; GFX8-NEXT: s_max_i32 s16, s13, 0
; GFX8-NEXT: s_cselect_b32 s16, s13, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s13, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s29
; GFX8-NEXT: s_cselect_b32 s17, s13, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s14, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s29
; GFX8-NEXT: s_cselect_b32 s17, s17, s29
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s13, s13, s16 ; GFX8-NEXT: s_add_i32 s13, s13, s16
; GFX8-NEXT: s_cmp_gt_i32 s14, 0 ; GFX8-NEXT: s_max_i32 s16, s14, 0
; GFX8-NEXT: s_cselect_b32 s16, s14, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s14, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s30
; GFX8-NEXT: s_cselect_b32 s17, s14, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_min_i32 s17, s15, 0
; GFX8-NEXT: s_sub_i32 s17, s33, s17 ; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s30
; GFX8-NEXT: s_cselect_b32 s17, s17, s30
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s14, s14, s16 ; GFX8-NEXT: s_add_i32 s14, s14, s16
; GFX8-NEXT: s_cmp_gt_i32 s15, 0 ; GFX8-NEXT: s_max_i32 s16, s15, 0
; GFX8-NEXT: s_cselect_b32 s16, s15, 0
; GFX8-NEXT: s_sub_i32 s16, s32, s16 ; GFX8-NEXT: s_sub_i32 s16, s32, s16
; GFX8-NEXT: s_cmp_lt_i32 s15, 0 ; GFX8-NEXT: s_max_i32 s17, s17, s31
; GFX8-NEXT: s_cselect_b32 s17, s15, 0 ; GFX8-NEXT: s_min_i32 s16, s17, s16
; GFX8-NEXT: s_sub_i32 s17, s33, s17
; GFX8-NEXT: s_cmp_gt_i32 s17, s31
; GFX8-NEXT: s_cselect_b32 s17, s17, s31
; GFX8-NEXT: s_cmp_lt_i32 s17, s16
; GFX8-NEXT: s_cselect_b32 s16, s17, s16
; GFX8-NEXT: s_add_i32 s15, s15, s16 ; GFX8-NEXT: s_add_i32 s15, s15, s16
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v16i32: ; GFX9-LABEL: s_saddsat_v16i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s16 ; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17 ; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18 ; GFX9-NEXT: v_mov_b32_e32 v2, s18
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result ret i16 %result
} }
define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i16: ; GFX6-LABEL: s_saddsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_min_i32 s3, s0, 0
; GFX6-NEXT: s_max_i32 s2, s0, 0
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3 ; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1 ; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cselect_b32 s1, s3, s1 ; GFX6-NEXT: s_max_i32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2 ; GFX6-NEXT: s_min_i32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 16 ; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_i16: ; GFX8-LABEL: s_saddsat_i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s2, s0 ; GFX8-NEXT: s_sext_i32_i16 s2, s0
; GFX8-NEXT: s_sext_i32_i16 s3, 0 ; GFX8-NEXT: s_sext_i32_i16 s3, 0
; GFX8-NEXT: s_cmp_gt_i32 s2, s3 ; GFX8-NEXT: s_max_i32 s4, s2, s3
; GFX8-NEXT: s_cselect_b32 s4, s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_sub_i32 s4, 0x7fff, s4
; GFX8-NEXT: s_cmp_lt_i32 s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3
; GFX8-NEXT: s_sub_i32 s2, 0xffff8000, s2 ; GFX8-NEXT: s_sub_i32 s2, 0xffff8000, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s2, s1 ; GFX8-NEXT: s_max_i32 s1, s2, s1
; GFX8-NEXT: s_cselect_b32 s1, s2, s1 ; GFX8-NEXT: s_sub_i32 s4, 0x7fff, s4
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s2, s4 ; GFX8-NEXT: s_sext_i32_i16 s2, s4
; GFX8-NEXT: s_cmp_lt_i32 s1, s2 ; GFX8-NEXT: s_min_i32 s1, s1, s2
; GFX8-NEXT: s_cselect_b32 s1, s1, s2
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_i16: ; GFX9-LABEL: s_saddsat_i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp ; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_saddsat_i16: ; GFX10-LABEL: s_saddsat_i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result ret i16 %result
} }
define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) { define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: saddsat_i16_sv: ; GFX6-LABEL: saddsat_i16_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_min_i32 s2, s0, 0
; GFX6-NEXT: s_cselect_b32 s1, s0, 0 ; GFX6-NEXT: s_max_i32 s1, s0, 0
; GFX6-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s2, 0x80000000, s2 ; GFX6-NEXT: s_sub_i32 s2, 0x80000000, s2
; GFX6-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX6-NEXT: v_max_i32_e32 v0, s2, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s2, v0
; GFX6-NEXT: v_min_i32_e32 v0, s1, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: saddsat_i16_sv: ; GFX8-LABEL: saddsat_i16_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s1, s0 ; GFX8-NEXT: s_sext_i32_i16 s1, s0
; GFX8-NEXT: s_sext_i32_i16 s2, 0 ; GFX8-NEXT: s_sext_i32_i16 s2, 0
; GFX8-NEXT: s_cmp_gt_i32 s1, s2 ; GFX8-NEXT: s_max_i32 s3, s1, s2
; GFX8-NEXT: s_cselect_b32 s3, s1, s2 ; GFX8-NEXT: s_min_i32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s3, 0x7fff, s3
; GFX8-NEXT: s_cmp_lt_i32 s1, s2
; GFX8-NEXT: s_cselect_b32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s1, 0xffff8000, s1 ; GFX8-NEXT: s_sub_i32 s1, 0xffff8000, s1
; GFX8-NEXT: s_sub_i32 s3, 0x7fff, s3
; GFX8-NEXT: v_max_i16_e32 v0, s1, v0 ; GFX8-NEXT: v_max_i16_e32 v0, s1, v0
; GFX8-NEXT: v_min_i16_e32 v0, s3, v0 ; GFX8-NEXT: v_min_i16_e32 v0, s3, v0
; GFX8-NEXT: v_add_u16_e32 v0, s0, v0 ; GFX8-NEXT: v_add_u16_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: saddsat_i16_sv: ; GFX9-LABEL: saddsat_i16_sv:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp ; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result ret <2 x i16> %result
} }
define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) { define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v2i16: ; GFX6-LABEL: s_saddsat_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_min_i32 s7, s0, 0
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, 0 ; GFX6-NEXT: s_max_i32 s6, s0, 0
; GFX6-NEXT: s_sub_i32 s6, s4, s6 ; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s2, s7, s2
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_min_i32 s2, s2, s6
; GFX6-NEXT: s_cselect_b32 s7, s0, 0
; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s2
; GFX6-NEXT: s_cselect_b32 s2, s7, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s6
; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 16 ; GFX6-NEXT: s_lshl_b32 s2, s3, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s3, s1, 0
; GFX6-NEXT: s_cselect_b32 s3, s1, 0
; GFX6-NEXT: s_sub_i32 s3, s4, s3 ; GFX6-NEXT: s_sub_i32 s3, s4, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, 0 ; GFX6-NEXT: s_min_i32 s4, s1, 0
; GFX6-NEXT: s_cselect_b32 s4, s1, 0
; GFX6-NEXT: s_sub_i32 s4, s5, s4 ; GFX6-NEXT: s_sub_i32 s4, s5, s4
; GFX6-NEXT: s_cmp_gt_i32 s4, s2 ; GFX6-NEXT: s_max_i32 s2, s4, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, s3
; GFX6-NEXT: s_cselect_b32 s2, s2, s3
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s1, s1, 16 ; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s2 ; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v2i16: ; GFX8-LABEL: s_saddsat_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_sext_i32_i16 s6, s0 ; GFX8-NEXT: s_sext_i32_i16 s6, s0
; GFX8-NEXT: s_sext_i32_i16 s7, 0 ; GFX8-NEXT: s_sext_i32_i16 s7, 0
; GFX8-NEXT: s_cmp_gt_i32 s6, s7 ; GFX8-NEXT: s_max_i32 s8, s6, s7
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: s_cselect_b32 s8, s6, s7
; GFX8-NEXT: s_sub_i32 s8, s4, s8
; GFX8-NEXT: s_cmp_lt_i32 s6, s7
; GFX8-NEXT: s_movk_i32 s5, 0x8000 ; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: s_cselect_b32 s6, s6, s7 ; GFX8-NEXT: s_min_i32 s6, s6, s7
; GFX8-NEXT: s_sub_i32 s6, s5, s6 ; GFX8-NEXT: s_sub_i32 s6, s5, s6
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s6, s1 ; GFX8-NEXT: s_max_i32 s1, s6, s1
; GFX8-NEXT: s_cselect_b32 s1, s6, s1 ; GFX8-NEXT: s_sub_i32 s8, s4, s8
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s6, s8 ; GFX8-NEXT: s_sext_i32_i16 s6, s8
; GFX8-NEXT: s_cmp_lt_i32 s1, s6 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_cselect_b32 s1, s1, s6 ; GFX8-NEXT: s_min_i32 s1, s1, s6
; GFX8-NEXT: s_add_i32 s0, s0, s1 ; GFX8-NEXT: s_add_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s2 ; GFX8-NEXT: s_sext_i32_i16 s1, s2
; GFX8-NEXT: s_cmp_gt_i32 s1, s7 ; GFX8-NEXT: s_max_i32 s6, s1, s7
; GFX8-NEXT: s_cselect_b32 s6, s1, s7 ; GFX8-NEXT: s_min_i32 s1, s1, s7
; GFX8-NEXT: s_sub_i32 s4, s4, s6
; GFX8-NEXT: s_cmp_lt_i32 s1, s7
; GFX8-NEXT: s_cselect_b32 s1, s1, s7
; GFX8-NEXT: s_sub_i32 s1, s5, s1 ; GFX8-NEXT: s_sub_i32 s1, s5, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s1, s3 ; GFX8-NEXT: s_max_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3 ; GFX8-NEXT: s_sub_i32 s4, s4, s6
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s4 ; GFX8-NEXT: s_sext_i32_i16 s3, s4
; GFX8-NEXT: s_cmp_lt_i32 s1, s3 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_add_i32 s2, s2, s1 ; GFX8-NEXT: s_add_i32 s2, s2, s1
; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_saddsat_v2i16: ; GFX9-LABEL: s_saddsat_v2i16:
Show All 12 Lines; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <2 x i16> %result to i32 %cast = bitcast <2 x i16> %result to i32
ret i32 %cast ret i32 %cast
} }
define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) { define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: saddsat_v2i16_sv: ; GFX6-LABEL: saddsat_v2i16_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: s_cselect_b32 s4, s0, 0
; GFX6-NEXT: s_sub_i32 s4, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s3, 1 ; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: s_cselect_b32 s5, s0, 0 ; GFX6-NEXT: s_min_i32 s5, s0, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s5, s3, s5 ; GFX6-NEXT: s_sub_i32 s5, s3, s5
; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: s_max_i32 s4, s0, 0
; GFX6-NEXT: s_sub_i32 s4, s2, s4
; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16 ; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s1, s0, 0
; GFX6-NEXT: s_cselect_b32 s1, s0, 0
; GFX6-NEXT: s_sub_i32 s1, s2, s1 ; GFX6-NEXT: s_sub_i32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_min_i32 s2, s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_sub_i32 s2, s3, s2 ; GFX6-NEXT: s_sub_i32 s2, s3, s2
; GFX6-NEXT: v_max_i32_e32 v1, s2, v1 ; GFX6-NEXT: v_max_i32_e32 v1, s2, v1
; GFX6-NEXT: v_min_i32_e32 v1, s1, v1 ; GFX6-NEXT: v_min_i32_e32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff ; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: saddsat_v2i16_sv: ; GFX8-LABEL: saddsat_v2i16_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: s_sext_i32_i16 s4, s0 ; GFX8-NEXT: s_sext_i32_i16 s4, s0
; GFX8-NEXT: s_sext_i32_i16 s5, 0 ; GFX8-NEXT: s_sext_i32_i16 s5, 0
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_max_i32 s6, s4, s5
; GFX8-NEXT: s_movk_i32 s2, 0x7fff
; GFX8-NEXT: s_cselect_b32 s6, s4, s5
; GFX8-NEXT: s_sub_i32 s6, s2, s6
; GFX8-NEXT: s_cmp_lt_i32 s4, s5
; GFX8-NEXT: s_movk_i32 s3, 0x8000 ; GFX8-NEXT: s_movk_i32 s3, 0x8000
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_movk_i32 s2, 0x7fff
; GFX8-NEXT: s_sub_i32 s4, s3, s4 ; GFX8-NEXT: s_sub_i32 s4, s3, s4
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_max_i16_e32 v1, s4, v0 ; GFX8-NEXT: v_max_i16_e32 v1, s4, v0
; GFX8-NEXT: s_sub_i32 s6, s2, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s1 ; GFX8-NEXT: s_sext_i32_i16 s4, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s5
; GFX8-NEXT: v_min_i16_e32 v1, s6, v1 ; GFX8-NEXT: v_min_i16_e32 v1, s6, v1
; GFX8-NEXT: s_cselect_b32 s6, s4, s5 ; GFX8-NEXT: s_max_i32 s6, s4, s5
; GFX8-NEXT: s_sub_i32 s2, s2, s6 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_sub_i32 s3, s3, s4 ; GFX8-NEXT: s_sub_i32 s3, s3, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s3 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: s_sub_i32 s2, s2, s6
; GFX8-NEXT: v_min_i16_e32 v0, s2, v0 ; GFX8-NEXT: v_min_i16_e32 v0, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_add_u16_e32 v1, s0, v1 ; GFX8-NEXT: v_add_u16_e32 v1, s0, v1
; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: saddsat_v2i16_sv: ; GFX9-LABEL: saddsat_v2i16_sv:
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <4 x i16> %result to <2 x float> %cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) { define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v4i16: ; GFX6-LABEL: s_saddsat_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_min_i32 s11, s0, 0
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_brev_b32 s8, -2 ; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, 0 ; GFX6-NEXT: s_max_i32 s10, s0, 0
; GFX6-NEXT: s_sub_i32 s10, s8, s10 ; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s4, s11, s4
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, 0
; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_cmp_gt_i32 s11, s4
; GFX6-NEXT: s_cselect_b32 s4, s11, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s10
; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_min_i32 s4, s4, s10
; GFX6-NEXT: s_min_i32 s10, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s4, s5, 16 ; GFX6-NEXT: s_lshl_b32 s4, s5, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s5, s1, 0
; GFX6-NEXT: s_cselect_b32 s5, s1, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s10, s1, 0
; GFX6-NEXT: s_sub_i32 s10, s9, s10 ; GFX6-NEXT: s_sub_i32 s10, s9, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s4 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s4, s10, s4 ; GFX6-NEXT: s_max_i32 s4, s10, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5 ; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s4, s6, 16 ; GFX6-NEXT: s_lshl_b32 s4, s6, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_min_i32 s6, s2, 0
; GFX6-NEXT: s_cselect_b32 s5, s2, 0 ; GFX6-NEXT: s_max_i32 s5, s2, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s2, 0
; GFX6-NEXT: s_cselect_b32 s6, s2, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6 ; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s4 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s4, s6, s4 ; GFX6-NEXT: s_max_i32 s4, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_min_i32 s6, s3, 0
; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_max_i32 s5, s3, 0
; GFX6-NEXT: s_lshl_b32 s4, s7, 16 ; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s6, s3, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6 ; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s4 ; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cselect_b32 s4, s6, s4 ; GFX6-NEXT: s_max_i32 s4, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5 ; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s4 ; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16 ; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4 ; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4 ; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_and_b32 s2, s3, s4 ; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v4i16: ; GFX8-LABEL: s_saddsat_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_sext_i32_i16 s10, s0 ; GFX8-NEXT: s_sext_i32_i16 s10, s0
; GFX8-NEXT: s_sext_i32_i16 s11, 0 ; GFX8-NEXT: s_sext_i32_i16 s11, 0
; GFX8-NEXT: s_cmp_gt_i32 s10, s11 ; GFX8-NEXT: s_max_i32 s12, s10, s11
; GFX8-NEXT: s_movk_i32 s8, 0x7fff
; GFX8-NEXT: s_cselect_b32 s12, s10, s11
; GFX8-NEXT: s_sub_i32 s12, s8, s12
; GFX8-NEXT: s_cmp_lt_i32 s10, s11
; GFX8-NEXT: s_movk_i32 s9, 0x8000 ; GFX8-NEXT: s_movk_i32 s9, 0x8000
; GFX8-NEXT: s_cselect_b32 s10, s10, s11 ; GFX8-NEXT: s_min_i32 s10, s10, s11
; GFX8-NEXT: s_sub_i32 s10, s9, s10 ; GFX8-NEXT: s_sub_i32 s10, s9, s10
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_movk_i32 s8, 0x7fff
; GFX8-NEXT: s_sext_i32_i16 s10, s10 ; GFX8-NEXT: s_sext_i32_i16 s10, s10
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s10, s2 ; GFX8-NEXT: s_max_i32 s2, s10, s2
; GFX8-NEXT: s_cselect_b32 s2, s10, s2 ; GFX8-NEXT: s_sub_i32 s12, s8, s12
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s10, s12 ; GFX8-NEXT: s_sext_i32_i16 s10, s12
; GFX8-NEXT: s_cmp_lt_i32 s2, s10 ; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_cselect_b32 s2, s2, s10 ; GFX8-NEXT: s_min_i32 s2, s2, s10
; GFX8-NEXT: s_add_i32 s0, s0, s2 ; GFX8-NEXT: s_add_i32 s0, s0, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s4 ; GFX8-NEXT: s_sext_i32_i16 s2, s4
; GFX8-NEXT: s_cmp_gt_i32 s2, s11 ; GFX8-NEXT: s_max_i32 s10, s2, s11
; GFX8-NEXT: s_cselect_b32 s10, s2, s11 ; GFX8-NEXT: s_min_i32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s10, s8, s10
; GFX8-NEXT: s_cmp_lt_i32 s2, s11
; GFX8-NEXT: s_cselect_b32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s2, s9, s2 ; GFX8-NEXT: s_sub_i32 s2, s9, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_gt_i32 s2, s6 ; GFX8-NEXT: s_max_i32 s2, s2, s6
; GFX8-NEXT: s_cselect_b32 s2, s2, s6 ; GFX8-NEXT: s_sub_i32 s10, s8, s10
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s6, s10 ; GFX8-NEXT: s_sext_i32_i16 s6, s10
; GFX8-NEXT: s_cmp_lt_i32 s2, s6 ; GFX8-NEXT: s_min_i32 s2, s2, s6
; GFX8-NEXT: s_cselect_b32 s2, s2, s6
; GFX8-NEXT: s_add_i32 s4, s4, s2 ; GFX8-NEXT: s_add_i32 s4, s4, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s1 ; GFX8-NEXT: s_sext_i32_i16 s2, s1
; GFX8-NEXT: s_cmp_gt_i32 s2, s11 ; GFX8-NEXT: s_max_i32 s6, s2, s11
; GFX8-NEXT: s_cselect_b32 s6, s2, s11 ; GFX8-NEXT: s_min_i32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s6, s8, s6
; GFX8-NEXT: s_cmp_lt_i32 s2, s11
; GFX8-NEXT: s_cselect_b32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s2, s9, s2 ; GFX8-NEXT: s_sub_i32 s2, s9, s2
; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s2, s3 ; GFX8-NEXT: s_max_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3 ; GFX8-NEXT: s_sub_i32 s6, s8, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s6 ; GFX8-NEXT: s_sext_i32_i16 s3, s6
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_lt_i32 s2, s3 ; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_cselect_b32 s2, s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_add_i32 s1, s1, s2 ; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s5 ; GFX8-NEXT: s_sext_i32_i16 s2, s5
; GFX8-NEXT: s_cmp_gt_i32 s2, s11 ; GFX8-NEXT: s_max_i32 s3, s2, s11
; GFX8-NEXT: s_cselect_b32 s3, s2, s11 ; GFX8-NEXT: s_min_i32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s3, s8, s3
; GFX8-NEXT: s_cmp_lt_i32 s2, s11
; GFX8-NEXT: s_cselect_b32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s2, s9, s2 ; GFX8-NEXT: s_sub_i32 s2, s9, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s6, s7 ; GFX8-NEXT: s_sext_i32_i16 s6, s7
; GFX8-NEXT: s_cmp_gt_i32 s2, s6 ; GFX8-NEXT: s_sub_i32 s3, s8, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s6 ; GFX8-NEXT: s_max_i32 s2, s2, s6
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3
; GFX8-NEXT: s_add_i32 s5, s5, s2 ; GFX8-NEXT: s_add_i32 s5, s5, s2
; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_or_b32 s0, s0, s2 ; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_bfe_u32 s2, s5, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s5, 0x100000
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <6 x i16> %result to <3 x float> %cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast ret <3 x float> %cast
} }
define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) { define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v6i16: ; GFX6-LABEL: s_saddsat_v6i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s13, 1
; GFX6-NEXT: s_min_i32 s15, s0, 0
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s15, s13, s15
; GFX6-NEXT: s_brev_b32 s12, -2 ; GFX6-NEXT: s_brev_b32 s12, -2
; GFX6-NEXT: s_cselect_b32 s14, s0, 0 ; GFX6-NEXT: s_max_i32 s14, s0, 0
; GFX6-NEXT: s_sub_i32 s14, s12, s14 ; GFX6-NEXT: s_sub_i32 s14, s12, s14
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s6, s15, s6
; GFX6-NEXT: s_brev_b32 s13, 1
; GFX6-NEXT: s_cselect_b32 s15, s0, 0
; GFX6-NEXT: s_sub_i32 s15, s13, s15
; GFX6-NEXT: s_cmp_gt_i32 s15, s6
; GFX6-NEXT: s_cselect_b32 s6, s15, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s14
; GFX6-NEXT: s_cselect_b32 s6, s6, s14
; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_min_i32 s6, s6, s14
; GFX6-NEXT: s_min_i32 s14, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s6, s7, 16 ; GFX6-NEXT: s_lshl_b32 s6, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s7, s1, 0
; GFX6-NEXT: s_cselect_b32 s7, s1, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s14, s1, 0
; GFX6-NEXT: s_sub_i32 s14, s13, s14 ; GFX6-NEXT: s_sub_i32 s14, s13, s14
; GFX6-NEXT: s_cmp_gt_i32 s14, s6 ; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cselect_b32 s6, s14, s6 ; GFX6-NEXT: s_max_i32 s6, s14, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7 ; GFX6-NEXT: s_min_i32 s6, s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s1, s1, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_add_i32 s1, s1, s6
; GFX6-NEXT: s_lshl_b32 s6, s8, 16 ; GFX6-NEXT: s_lshl_b32 s6, s8, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_min_i32 s8, s2, 0
; GFX6-NEXT: s_cselect_b32 s7, s2, 0 ; GFX6-NEXT: s_max_i32 s7, s2, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s2, 0
; GFX6-NEXT: s_cselect_b32 s8, s2, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8 ; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6 ; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cselect_b32 s6, s8, s6 ; GFX6-NEXT: s_max_i32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s2, s2, s6
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s6, s6, s7
; GFX6-NEXT: s_min_i32 s8, s3, 0
; GFX6-NEXT: s_add_i32 s2, s2, s6
; GFX6-NEXT: s_max_i32 s7, s3, 0
; GFX6-NEXT: s_lshl_b32 s6, s9, 16 ; GFX6-NEXT: s_lshl_b32 s6, s9, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s7, s3, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s8, s3, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8 ; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6 ; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cselect_b32 s6, s8, s6 ; GFX6-NEXT: s_max_i32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_min_i32 s6, s6, s7
; GFX6-NEXT: s_min_i32 s8, s4, 0
; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_max_i32 s7, s4, 0
; GFX6-NEXT: s_lshl_b32 s6, s10, 16 ; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s7, s4, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s8, s4, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8 ; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6 ; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cselect_b32 s6, s8, s6 ; GFX6-NEXT: s_max_i32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_min_i32 s6, s6, s7
; GFX6-NEXT: s_min_i32 s8, s5, 0
; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_max_i32 s7, s5, 0
; GFX6-NEXT: s_lshl_b32 s6, s11, 16 ; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s7, s5, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s8, s5, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8 ; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6 ; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cselect_b32 s6, s8, s6 ; GFX6-NEXT: s_max_i32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7 ; GFX6-NEXT: s_min_i32 s6, s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s5, s5, s6 ; GFX6-NEXT: s_add_i32 s5, s5, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s6, 0xffff ; GFX6-NEXT: s_mov_b32 s6, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s6 ; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s6 ; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6 ; GFX6-NEXT: s_and_b32 s1, s2, s6
; GFX6-NEXT: s_and_b32 s2, s3, s6 ; GFX6-NEXT: s_and_b32 s2, s3, s6
; GFX6-NEXT: s_ashr_i32 s5, s5, 16 ; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s6 ; GFX6-NEXT: s_and_b32 s3, s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6 ; GFX6-NEXT: s_and_b32 s2, s4, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v6i16: ; GFX8-LABEL: s_saddsat_v6i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NEXT: s_sext_i32_i16 s14, s0 ; GFX8-NEXT: s_sext_i32_i16 s14, s0
; GFX8-NEXT: s_sext_i32_i16 s15, 0 ; GFX8-NEXT: s_sext_i32_i16 s15, 0
; GFX8-NEXT: s_cmp_gt_i32 s14, s15 ; GFX8-NEXT: s_max_i32 s16, s14, s15
; GFX8-NEXT: s_movk_i32 s12, 0x7fff
; GFX8-NEXT: s_cselect_b32 s16, s14, s15
; GFX8-NEXT: s_sub_i32 s16, s12, s16
; GFX8-NEXT: s_cmp_lt_i32 s14, s15
; GFX8-NEXT: s_movk_i32 s13, 0x8000 ; GFX8-NEXT: s_movk_i32 s13, 0x8000
; GFX8-NEXT: s_cselect_b32 s14, s14, s15 ; GFX8-NEXT: s_min_i32 s14, s14, s15
; GFX8-NEXT: s_sub_i32 s14, s13, s14 ; GFX8-NEXT: s_sub_i32 s14, s13, s14
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_movk_i32 s12, 0x7fff
; GFX8-NEXT: s_sext_i32_i16 s14, s14 ; GFX8-NEXT: s_sext_i32_i16 s14, s14
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s14, s3 ; GFX8-NEXT: s_max_i32 s3, s14, s3
; GFX8-NEXT: s_cselect_b32 s3, s14, s3 ; GFX8-NEXT: s_sub_i32 s16, s12, s16
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s14, s16 ; GFX8-NEXT: s_sext_i32_i16 s14, s16
; GFX8-NEXT: s_cmp_lt_i32 s3, s14 ; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_cselect_b32 s3, s3, s14 ; GFX8-NEXT: s_min_i32 s3, s3, s14
; GFX8-NEXT: s_add_i32 s0, s0, s3 ; GFX8-NEXT: s_add_i32 s0, s0, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s6 ; GFX8-NEXT: s_sext_i32_i16 s3, s6
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s14, s3, s15
; GFX8-NEXT: s_cselect_b32 s14, s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s14, s12, s14
; GFX8-NEXT: s_cmp_lt_i32 s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s13, s3 ; GFX8-NEXT: s_sub_i32 s3, s13, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_cmp_gt_i32 s3, s9 ; GFX8-NEXT: s_max_i32 s3, s3, s9
; GFX8-NEXT: s_cselect_b32 s3, s3, s9 ; GFX8-NEXT: s_sub_i32 s14, s12, s14
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s9, s14 ; GFX8-NEXT: s_sext_i32_i16 s9, s14
; GFX8-NEXT: s_cmp_lt_i32 s3, s9 ; GFX8-NEXT: s_min_i32 s3, s3, s9
; GFX8-NEXT: s_cselect_b32 s3, s3, s9
; GFX8-NEXT: s_add_i32 s6, s6, s3 ; GFX8-NEXT: s_add_i32 s6, s6, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s1 ; GFX8-NEXT: s_sext_i32_i16 s3, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s9, s3, s15
; GFX8-NEXT: s_cselect_b32 s9, s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s9, s12, s9
; GFX8-NEXT: s_cmp_lt_i32 s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s13, s3 ; GFX8-NEXT: s_sub_i32 s3, s13, s3
; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_max_i32 s3, s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4 ; GFX8-NEXT: s_sub_i32 s9, s12, s9
; GFX8-NEXT: s_sext_i32_i16 s4, s9 ; GFX8-NEXT: s_sext_i32_i16 s4, s9
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_cselect_b32 s3, s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_add_i32 s1, s1, s3 ; GFX8-NEXT: s_add_i32 s1, s1, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s7 ; GFX8-NEXT: s_sext_i32_i16 s3, s7
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s4, s3, s15
; GFX8-NEXT: s_cselect_b32 s4, s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s13, s3 ; GFX8-NEXT: s_sub_i32 s3, s13, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s9, s10 ; GFX8-NEXT: s_sext_i32_i16 s9, s10
; GFX8-NEXT: s_cmp_gt_i32 s3, s9 ; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s9 ; GFX8-NEXT: s_max_i32 s3, s3, s9
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_add_i32 s7, s7, s3 ; GFX8-NEXT: s_add_i32 s7, s7, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s2 ; GFX8-NEXT: s_sext_i32_i16 s3, s2
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s4, s3, s15
; GFX8-NEXT: s_cselect_b32 s4, s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s13, s3 ; GFX8-NEXT: s_sub_i32 s3, s13, s3
; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_gt_i32 s3, s5 ; GFX8-NEXT: s_max_i32 s3, s3, s5
; GFX8-NEXT: s_cselect_b32 s3, s3, s5 ; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NEXT: s_cselect_b32 s3, s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_add_i32 s2, s2, s3 ; GFX8-NEXT: s_add_i32 s2, s2, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s8 ; GFX8-NEXT: s_sext_i32_i16 s3, s8
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s4, s3, s15
; GFX8-NEXT: s_cselect_b32 s4, s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s13, s3 ; GFX8-NEXT: s_sub_i32 s3, s13, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s5, s11 ; GFX8-NEXT: s_sext_i32_i16 s5, s11
; GFX8-NEXT: s_cmp_gt_i32 s3, s5 ; GFX8-NEXT: s_sub_i32 s4, s12, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s5 ; GFX8-NEXT: s_max_i32 s3, s3, s5
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_add_i32 s8, s8, s3 ; GFX8-NEXT: s_add_i32 s8, s8, s3
; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000 ; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16 ; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_or_b32 s0, s0, s3 ; GFX8-NEXT: s_or_b32 s0, s0, s3
; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000 ; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16 ; GFX8-NEXT: s_lshl_b32 s3, s3, 16
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <8 x i16> %result to <4 x float> %cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast ret <4 x float> %cast
} }
define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) { define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v8i16: ; GFX6-LABEL: s_saddsat_v8i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s17, 1
; GFX6-NEXT: s_min_i32 s19, s0, 0
; GFX6-NEXT: s_lshl_b32 s8, s8, 16 ; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, 0 ; GFX6-NEXT: s_sub_i32 s19, s17, s19
; GFX6-NEXT: s_brev_b32 s16, -2 ; GFX6-NEXT: s_brev_b32 s16, -2
; GFX6-NEXT: s_cselect_b32 s18, s0, 0 ; GFX6-NEXT: s_max_i32 s18, s0, 0
; GFX6-NEXT: s_sub_i32 s18, s16, s18 ; GFX6-NEXT: s_sub_i32 s18, s16, s18
; GFX6-NEXT: s_cmp_lt_i32 s0, 0 ; GFX6-NEXT: s_max_i32 s8, s19, s8
; GFX6-NEXT: s_brev_b32 s17, 1
; GFX6-NEXT: s_cselect_b32 s19, s0, 0
; GFX6-NEXT: s_sub_i32 s19, s17, s19
; GFX6-NEXT: s_cmp_gt_i32 s19, s8
; GFX6-NEXT: s_cselect_b32 s8, s19, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s18
; GFX6-NEXT: s_cselect_b32 s8, s8, s18
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_min_i32 s8, s8, s18
; GFX6-NEXT: s_min_i32 s18, s1, 0
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s8, s9, 16 ; GFX6-NEXT: s_lshl_b32 s8, s9, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, 0 ; GFX6-NEXT: s_max_i32 s9, s1, 0
; GFX6-NEXT: s_cselect_b32 s9, s1, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s1, 0
; GFX6-NEXT: s_cselect_b32 s18, s1, 0
; GFX6-NEXT: s_sub_i32 s18, s17, s18 ; GFX6-NEXT: s_sub_i32 s18, s17, s18
; GFX6-NEXT: s_cmp_gt_i32 s18, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s18, s8 ; GFX6-NEXT: s_max_i32 s8, s18, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9 ; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s1, s1, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_add_i32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s8, s10, 16 ; GFX6-NEXT: s_lshl_b32 s8, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, 0 ; GFX6-NEXT: s_min_i32 s10, s2, 0
; GFX6-NEXT: s_cselect_b32 s9, s2, 0 ; GFX6-NEXT: s_max_i32 s9, s2, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s2, 0
; GFX6-NEXT: s_cselect_b32 s10, s2, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s2, s2, s8
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_min_i32 s10, s3, 0
; GFX6-NEXT: s_add_i32 s2, s2, s8
; GFX6-NEXT: s_max_i32 s9, s3, 0
; GFX6-NEXT: s_lshl_b32 s8, s11, 16 ; GFX6-NEXT: s_lshl_b32 s8, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s9, s3, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s10, s3, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_min_i32 s10, s4, 0
; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_max_i32 s9, s4, 0
; GFX6-NEXT: s_lshl_b32 s8, s12, 16 ; GFX6-NEXT: s_lshl_b32 s8, s12, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s9, s4, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s10, s4, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_min_i32 s10, s5, 0
; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_max_i32 s9, s5, 0
; GFX6-NEXT: s_lshl_b32 s8, s13, 16 ; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s9, s5, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s10, s5, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_min_i32 s10, s6, 0
; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_max_i32 s9, s6, 0
; GFX6-NEXT: s_lshl_b32 s8, s14, 16 ; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_cmp_gt_i32 s6, 0
; GFX6-NEXT: s_cselect_b32 s9, s6, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s6, 0
; GFX6-NEXT: s_cselect_b32 s10, s6, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16 ; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_min_i32 s10, s7, 0
; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s9, s7, 0
; GFX6-NEXT: s_lshl_b32 s8, s15, 16 ; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_cmp_gt_i32 s7, 0
; GFX6-NEXT: s_cselect_b32 s9, s7, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s7, 0
; GFX6-NEXT: s_cselect_b32 s10, s7, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10 ; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8 ; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cselect_b32 s8, s10, s8 ; GFX6-NEXT: s_max_i32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9 ; GFX6-NEXT: s_min_i32 s8, s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s7, s7, s8 ; GFX6-NEXT: s_add_i32 s7, s7, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s8 ; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s8 ; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8 ; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s8 ; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s8 ; GFX6-NEXT: s_and_b32 s3, s5, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_ashr_i32 s7, s7, 16 ; GFX6-NEXT: s_ashr_i32 s7, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8 ; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: s_and_b32 s4, s7, s8 ; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8 ; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4 ; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_saddsat_v8i16: ; GFX8-LABEL: s_saddsat_v8i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_lshr_b32 s14, s6, 16
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_sext_i32_i16 s18, s0 ; GFX8-NEXT: s_sext_i32_i16 s18, s0
; GFX8-NEXT: s_sext_i32_i16 s19, 0 ; GFX8-NEXT: s_sext_i32_i16 s19, 0
; GFX8-NEXT: s_cmp_gt_i32 s18, s19 ; GFX8-NEXT: s_max_i32 s20, s18, s19
; GFX8-NEXT: s_movk_i32 s16, 0x7fff
; GFX8-NEXT: s_cselect_b32 s20, s18, s19
; GFX8-NEXT: s_sub_i32 s20, s16, s20
; GFX8-NEXT: s_cmp_lt_i32 s18, s19
; GFX8-NEXT: s_movk_i32 s17, 0x8000 ; GFX8-NEXT: s_movk_i32 s17, 0x8000
; GFX8-NEXT: s_cselect_b32 s18, s18, s19 ; GFX8-NEXT: s_min_i32 s18, s18, s19
; GFX8-NEXT: s_sub_i32 s18, s17, s18 ; GFX8-NEXT: s_sub_i32 s18, s17, s18
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_movk_i32 s16, 0x7fff
; GFX8-NEXT: s_sext_i32_i16 s18, s18 ; GFX8-NEXT: s_sext_i32_i16 s18, s18
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s18, s4 ; GFX8-NEXT: s_max_i32 s4, s18, s4
; GFX8-NEXT: s_cselect_b32 s4, s18, s4 ; GFX8-NEXT: s_sub_i32 s20, s16, s20
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s18, s20 ; GFX8-NEXT: s_sext_i32_i16 s18, s20
; GFX8-NEXT: s_cmp_lt_i32 s4, s18 ; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s18 ; GFX8-NEXT: s_min_i32 s4, s4, s18
; GFX8-NEXT: s_add_i32 s0, s0, s4 ; GFX8-NEXT: s_add_i32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s8 ; GFX8-NEXT: s_sext_i32_i16 s4, s8
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s18, s4, s19
; GFX8-NEXT: s_cselect_b32 s18, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s18, s16, s18
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s12, s12 ; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_cmp_gt_i32 s4, s12 ; GFX8-NEXT: s_max_i32 s4, s4, s12
; GFX8-NEXT: s_cselect_b32 s4, s4, s12 ; GFX8-NEXT: s_sub_i32 s18, s16, s18
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s12, s18 ; GFX8-NEXT: s_sext_i32_i16 s12, s18
; GFX8-NEXT: s_cmp_lt_i32 s4, s12 ; GFX8-NEXT: s_min_i32 s4, s4, s12
; GFX8-NEXT: s_cselect_b32 s4, s4, s12
; GFX8-NEXT: s_add_i32 s8, s8, s4 ; GFX8-NEXT: s_add_i32 s8, s8, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s1 ; GFX8-NEXT: s_sext_i32_i16 s4, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s12, s4, s19
; GFX8-NEXT: s_cselect_b32 s12, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s12, s16, s12
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_max_i32 s4, s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_sub_i32 s12, s16, s12
; GFX8-NEXT: s_sext_i32_i16 s5, s12 ; GFX8-NEXT: s_sext_i32_i16 s5, s12
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s1, s1, s4 ; GFX8-NEXT: s_add_i32 s1, s1, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s9 ; GFX8-NEXT: s_sext_i32_i16 s4, s9
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s5, s4, s19
; GFX8-NEXT: s_cselect_b32 s5, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s12, s13 ; GFX8-NEXT: s_sext_i32_i16 s12, s13
; GFX8-NEXT: s_cmp_gt_i32 s4, s12 ; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s12 ; GFX8-NEXT: s_max_i32 s4, s4, s12
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s9, s9, s4 ; GFX8-NEXT: s_add_i32 s9, s9, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s2 ; GFX8-NEXT: s_sext_i32_i16 s4, s2
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s5, s4, s19
; GFX8-NEXT: s_cselect_b32 s5, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_lshr_b32 s14, s6, 16
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s2, s2, s4 ; GFX8-NEXT: s_add_i32 s2, s2, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s10 ; GFX8-NEXT: s_sext_i32_i16 s4, s10
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s5, s4, s19
; GFX8-NEXT: s_cselect_b32 s5, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s14 ; GFX8-NEXT: s_sext_i32_i16 s6, s14
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s10, s10, s4 ; GFX8-NEXT: s_add_i32 s10, s10, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s3 ; GFX8-NEXT: s_sext_i32_i16 s4, s3
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s5, s4, s19
; GFX8-NEXT: s_cselect_b32 s5, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s7 ; GFX8-NEXT: s_sext_i32_i16 s6, s7
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s3, s3, s4 ; GFX8-NEXT: s_add_i32 s3, s3, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s11 ; GFX8-NEXT: s_sext_i32_i16 s4, s11
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s5, s4, s19
; GFX8-NEXT: s_cselect_b32 s5, s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s17, s4 ; GFX8-NEXT: s_sub_i32 s4, s17, s4
; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s15 ; GFX8-NEXT: s_sext_i32_i16 s6, s15
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_sub_i32 s5, s16, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_add_i32 s11, s11, s4 ; GFX8-NEXT: s_add_i32 s11, s11, s4
; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_or_b32 s0, s0, s4 ; GFX8-NEXT: s_or_b32 s0, s0, s4
; GFX8-NEXT: s_bfe_u32 s4, s9, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, s9, 0x100000
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: s_lshl_b32 s4, s4, 16
▲ Show 20 Lines • Show All 2,730 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs) %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result ret i7 %result
} }
define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) { define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i7: ; GFX6-LABEL: s_ssubsat_i7:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25 ; GFX6-NEXT: s_lshl_b32 s0, s0, 25
; GFX6-NEXT: s_max_i32 s2, s0, -1
; GFX6-NEXT: s_min_i32 s3, s0, -1
; GFX6-NEXT: s_lshl_b32 s1, s1, 25 ; GFX6-NEXT: s_lshl_b32 s1, s1, 25
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1 ; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 25 ; GFX6-NEXT: s_ashr_i32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i7: ; GFX8-LABEL: s_ssubsat_i7:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0 ; GFX8-NEXT: s_sext_i32_i16 s3, s0
; GFX8-NEXT: s_sext_i32_i16 s4, -1 ; GFX8-NEXT: s_sext_i32_i16 s4, -1
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_cselect_b32 s5, s3, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff ; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_sext_i32_i16 s4, s5 ; GFX8-NEXT: s_sext_i32_i16 s4, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s1 ; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_cselect_b32 s1, s4, s1 ; GFX8-NEXT: s_max_i32 s1, s4, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s1, s3 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i7: ; GFX9-LABEL: s_ssubsat_i7:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result ret i8 %result
} }
define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) { define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i8: ; GFX6-LABEL: s_ssubsat_i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_max_i32 s2, s0, -1
; GFX6-NEXT: s_min_i32 s3, s0, -1
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1 ; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 24 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i8: ; GFX8-LABEL: s_ssubsat_i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0 ; GFX8-NEXT: s_sext_i32_i16 s3, s0
; GFX8-NEXT: s_sext_i32_i16 s4, -1 ; GFX8-NEXT: s_sext_i32_i16 s4, -1
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_cselect_b32 s5, s3, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff ; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_sext_i32_i16 s4, s5 ; GFX8-NEXT: s_sext_i32_i16 s4, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s1 ; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_cselect_b32 s1, s4, s1 ; GFX8-NEXT: s_max_i32 s1, s4, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s1, s3 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i8: ; GFX9-LABEL: s_ssubsat_i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast.result = bitcast <2 x i8> %result to i16 %cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result ret i16 %cast.result
} }
define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_ssubsat_v2i8: ; GFX6-LABEL: s_ssubsat_v2i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, -1 ; GFX6-NEXT: s_max_i32 s6, s0, -1
; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_sub_i32 s6, s6, s4 ; GFX6-NEXT: s_sub_i32 s6, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, -1 ; GFX6-NEXT: s_min_i32 s7, s0, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s5 ; GFX6-NEXT: s_sub_i32 s7, s7, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s1 ; GFX6-NEXT: s_max_i32 s1, s6, s1
; GFX6-NEXT: s_cselect_b32 s1, s6, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s7
; GFX6-NEXT: s_cmp_lt_i32 s1, s7
; GFX6-NEXT: s_cselect_b32 s1, s1, s7
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s3, s1, -1
; GFX6-NEXT: s_cselect_b32 s3, s1, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s4, s1, -1
; GFX6-NEXT: s_cselect_b32 s4, s1, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s5 ; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_gt_i32 s3, s2 ; GFX6-NEXT: s_max_i32 s2, s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s1, s1, 24 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_and_b32 s1, s1, s2 ; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v2i8: ; GFX8-LABEL: s_ssubsat_v2i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8 ; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s4 ; GFX8-NEXT: s_lshl_b32 s0, s0, s4
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_sext_i32_i16 s7, s0 ; GFX8-NEXT: s_sext_i32_i16 s7, s0
; GFX8-NEXT: s_sext_i32_i16 s8, -1 ; GFX8-NEXT: s_sext_i32_i16 s8, -1
; GFX8-NEXT: s_cmp_gt_i32 s7, s8 ; GFX8-NEXT: s_max_i32 s9, s7, s8
; GFX8-NEXT: s_movk_i32 s5, 0x7fff ; GFX8-NEXT: s_movk_i32 s5, 0x7fff
; GFX8-NEXT: s_cselect_b32 s9, s7, s8
; GFX8-NEXT: s_sub_i32 s9, s9, s5 ; GFX8-NEXT: s_sub_i32 s9, s9, s5
; GFX8-NEXT: s_cmp_lt_i32 s7, s8 ; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_movk_i32 s6, 0x8000 ; GFX8-NEXT: s_movk_i32 s6, 0x8000
; GFX8-NEXT: s_cselect_b32 s7, s7, s8 ; GFX8-NEXT: s_min_i32 s7, s7, s8
; GFX8-NEXT: s_sub_i32 s7, s7, s6
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s9, s1 ; GFX8-NEXT: s_sub_i32 s7, s7, s6
; GFX8-NEXT: s_cselect_b32 s1, s9, s1 ; GFX8-NEXT: s_max_i32 s1, s9, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s7, s7 ; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_cmp_lt_i32 s1, s7 ; GFX8-NEXT: s_min_i32 s1, s1, s7
; GFX8-NEXT: s_cselect_b32 s1, s1, s7
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_lshl_b32 s1, s2, s4 ; GFX8-NEXT: s_lshl_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s2, s3, s4 ; GFX8-NEXT: s_lshl_b32 s2, s3, s4
; GFX8-NEXT: s_ashr_i32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s1 ; GFX8-NEXT: s_sext_i32_i16 s3, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s8 ; GFX8-NEXT: s_max_i32 s7, s3, s8
; GFX8-NEXT: s_cselect_b32 s7, s3, s8
; GFX8-NEXT: s_sub_i32 s5, s7, s5 ; GFX8-NEXT: s_sub_i32 s5, s7, s5
; GFX8-NEXT: s_cmp_lt_i32 s3, s8 ; GFX8-NEXT: s_min_i32 s3, s3, s8
; GFX8-NEXT: s_cselect_b32 s3, s3, s8
; GFX8-NEXT: s_sub_i32 s3, s3, s6
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s5, s2 ; GFX8-NEXT: s_sub_i32 s3, s3, s6
; GFX8-NEXT: s_cselect_b32 s2, s5, s2 ; GFX8-NEXT: s_max_i32 s2, s5, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3
; GFX8-NEXT: s_sub_i32 s1, s1, s2 ; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_movk_i32 s2, 0xff ; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s1, s1, s4 ; GFX8-NEXT: s_ashr_i32 s1, s1, s4
; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_ashr_i32 s0, s0, s4
; GFX8-NEXT: s_and_b32 s1, s1, s2 ; GFX8-NEXT: s_and_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s0, s0, s2 ; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s4 ; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v2i8: ; GFX9-LABEL: s_ssubsat_v2i8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
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} }
define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) { define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-LABEL: s_ssubsat_v4i8: ; GFX6-LABEL: s_ssubsat_v4i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24 ; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_max_i32 s10, s0, -1
; GFX6-NEXT: s_lshr_b32 s5, s1, 8 ; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16 ; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24 ; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s8 ; GFX6-NEXT: s_sub_i32 s10, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s9, 1 ; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, -1 ; GFX6-NEXT: s_min_i32 s11, s0, -1
; GFX6-NEXT: s_sub_i32 s11, s11, s9 ; GFX6-NEXT: s_sub_i32 s11, s11, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s1 ; GFX6-NEXT: s_max_i32 s1, s10, s1
; GFX6-NEXT: s_cselect_b32 s1, s10, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s11
; GFX6-NEXT: s_cmp_lt_i32 s1, s11
; GFX6-NEXT: s_cselect_b32 s1, s1, s11
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s2, s5, 24 ; GFX6-NEXT: s_lshl_b32 s2, s5, 24
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s5, s1, -1
; GFX6-NEXT: s_cselect_b32 s5, s1, -1 ; GFX6-NEXT: s_min_i32 s10, s1, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s1, -1
; GFX6-NEXT: s_cselect_b32 s10, s1, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s9 ; GFX6-NEXT: s_sub_i32 s10, s10, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s2 ; GFX6-NEXT: s_max_i32 s2, s5, s2
; GFX6-NEXT: s_cselect_b32 s2, s5, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s10
; GFX6-NEXT: s_cmp_lt_i32 s2, s10
; GFX6-NEXT: s_cselect_b32 s2, s2, s10
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_ashr_i32 s1, s1, 24 ; GFX6-NEXT: s_max_i32 s5, s2, -1
; GFX6-NEXT: s_lshl_b32 s3, s6, 24 ; GFX6-NEXT: s_lshl_b32 s3, s6, 24
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s6, s2, -1
; GFX6-NEXT: s_cselect_b32 s5, s2, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s2, -1
; GFX6-NEXT: s_cselect_b32 s6, s2, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9 ; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s3 ; GFX6-NEXT: s_max_i32 s3, s5, s3
; GFX6-NEXT: s_cselect_b32 s3, s5, s3 ; GFX6-NEXT: s_min_i32 s3, s3, s6
; GFX6-NEXT: s_cmp_lt_i32 s3, s6
; GFX6-NEXT: s_cselect_b32 s3, s3, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s3 ; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24 ; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_ashr_i32 s2, s2, 24 ; GFX6-NEXT: s_max_i32 s5, s3, -1
; GFX6-NEXT: s_min_i32 s6, s3, -1
; GFX6-NEXT: s_lshl_b32 s4, s7, 24 ; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s6, s3, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9 ; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4 ; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4 ; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_movk_i32 s4, 0xff ; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: s_and_b32 s1, s1, s4 ; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 24
; GFX6-NEXT: s_and_b32 s0, s0, s4 ; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4 ; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 24 ; GFX6-NEXT: s_ashr_i32 s3, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s3, s4 ; GFX6-NEXT: s_and_b32 s1, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v4i8: ; GFX8-LABEL: s_ssubsat_v4i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8 ; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshr_b32 s3, s0, 16 ; GFX8-NEXT: s_lshr_b32 s3, s0, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 24 ; GFX8-NEXT: s_lshr_b32 s4, s0, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, s8 ; GFX8-NEXT: s_lshl_b32 s0, s0, s8
; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
; GFX8-NEXT: s_sext_i32_i16 s11, s0 ; GFX8-NEXT: s_sext_i32_i16 s11, s0
; GFX8-NEXT: s_sext_i32_i16 s12, -1 ; GFX8-NEXT: s_sext_i32_i16 s12, -1
; GFX8-NEXT: s_cmp_gt_i32 s11, s12 ; GFX8-NEXT: s_max_i32 s13, s11, s12
; GFX8-NEXT: s_movk_i32 s9, 0x7fff ; GFX8-NEXT: s_movk_i32 s9, 0x7fff
; GFX8-NEXT: s_cselect_b32 s13, s11, s12
; GFX8-NEXT: s_sub_i32 s13, s13, s9 ; GFX8-NEXT: s_sub_i32 s13, s13, s9
; GFX8-NEXT: s_cmp_lt_i32 s11, s12 ; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
; GFX8-NEXT: s_movk_i32 s10, 0x8000 ; GFX8-NEXT: s_movk_i32 s10, 0x8000
; GFX8-NEXT: s_cselect_b32 s11, s11, s12 ; GFX8-NEXT: s_min_i32 s11, s11, s12
; GFX8-NEXT: s_sub_i32 s11, s11, s10
; GFX8-NEXT: s_sext_i32_i16 s13, s13 ; GFX8-NEXT: s_sext_i32_i16 s13, s13
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s13, s1 ; GFX8-NEXT: s_sub_i32 s11, s11, s10
; GFX8-NEXT: s_cselect_b32 s1, s13, s1 ; GFX8-NEXT: s_max_i32 s1, s13, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s11, s11 ; GFX8-NEXT: s_sext_i32_i16 s11, s11
; GFX8-NEXT: s_cmp_lt_i32 s1, s11 ; GFX8-NEXT: s_min_i32 s1, s1, s11
; GFX8-NEXT: s_cselect_b32 s1, s1, s11
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_lshl_b32 s1, s2, s8 ; GFX8-NEXT: s_lshl_b32 s1, s2, s8
; GFX8-NEXT: s_lshl_b32 s2, s5, s8 ; GFX8-NEXT: s_lshl_b32 s2, s5, s8
; GFX8-NEXT: s_ashr_i32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s1 ; GFX8-NEXT: s_sext_i32_i16 s5, s1
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_max_i32 s11, s5, s12
; GFX8-NEXT: s_cselect_b32 s11, s5, s12
; GFX8-NEXT: s_sub_i32 s11, s11, s9 ; GFX8-NEXT: s_sub_i32 s11, s11, s9
; GFX8-NEXT: s_cmp_lt_i32 s5, s12 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_sext_i32_i16 s11, s11 ; GFX8-NEXT: s_sext_i32_i16 s11, s11
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s11, s2 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cselect_b32 s2, s11, s2 ; GFX8-NEXT: s_max_i32 s2, s11, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s2, s5 ; GFX8-NEXT: s_min_i32 s2, s2, s5
; GFX8-NEXT: s_cselect_b32 s2, s2, s5
; GFX8-NEXT: s_sub_i32 s1, s1, s2 ; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_lshl_b32 s2, s3, s8 ; GFX8-NEXT: s_lshl_b32 s2, s3, s8
; GFX8-NEXT: s_lshl_b32 s3, s6, s8
; GFX8-NEXT: s_ashr_i32 s1, s1, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s2 ; GFX8-NEXT: s_sext_i32_i16 s5, s2
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_lshl_b32 s3, s6, s8
; GFX8-NEXT: s_cselect_b32 s6, s5, s12 ; GFX8-NEXT: s_max_i32 s6, s5, s12
; GFX8-NEXT: s_sub_i32 s6, s6, s9 ; GFX8-NEXT: s_sub_i32 s6, s6, s9
; GFX8-NEXT: s_cmp_lt_i32 s5, s12 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s6, s3 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cselect_b32 s3, s6, s3 ; GFX8-NEXT: s_max_i32 s3, s6, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s3, s5 ; GFX8-NEXT: s_min_i32 s3, s3, s5
; GFX8-NEXT: s_cselect_b32 s3, s3, s5
; GFX8-NEXT: s_sub_i32 s2, s2, s3 ; GFX8-NEXT: s_sub_i32 s2, s2, s3
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_lshl_b32 s3, s4, s8 ; GFX8-NEXT: s_lshl_b32 s3, s4, s8
; GFX8-NEXT: s_lshl_b32 s4, s7, s8
; GFX8-NEXT: s_ashr_i32 s2, s2, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s3 ; GFX8-NEXT: s_sext_i32_i16 s5, s3
; GFX8-NEXT: s_cmp_gt_i32 s5, s12 ; GFX8-NEXT: s_max_i32 s6, s5, s12
; GFX8-NEXT: s_cselect_b32 s6, s5, s12 ; GFX8-NEXT: s_lshl_b32 s4, s7, s8
; GFX8-NEXT: s_sub_i32 s6, s6, s9 ; GFX8-NEXT: s_sub_i32 s6, s6, s9
; GFX8-NEXT: s_cmp_lt_i32 s5, s12 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s6, s4 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cselect_b32 s4, s6, s4 ; GFX8-NEXT: s_max_i32 s4, s6, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_sub_i32 s3, s3, s4 ; GFX8-NEXT: s_sub_i32 s3, s3, s4
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s1, s1, s8
; GFX8-NEXT: s_movk_i32 s4, 0xff ; GFX8-NEXT: s_movk_i32 s4, 0xff
; GFX8-NEXT: s_ashr_i32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_and_b32 s1, s1, s4 ; GFX8-NEXT: s_and_b32 s1, s1, s4
; GFX8-NEXT: s_ashr_i32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s0, s0, s4 ; GFX8-NEXT: s_and_b32 s0, s0, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s2, s4 ; GFX8-NEXT: s_and_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_ashr_i32 s3, s3, s8 ; GFX8-NEXT: s_ashr_i32 s3, s3, s8
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
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%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs) %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result ret i24 %result
} }
define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) { define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i24: ; GFX6-LABEL: s_ssubsat_i24:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8 ; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_max_i32 s2, s0, -1
; GFX6-NEXT: s_min_i32 s3, s0, -1
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1 ; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 8 ; GFX6-NEXT: s_ashr_i32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i24: ; GFX8-LABEL: s_ssubsat_i24:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s2, s0, s1 ; GFX8-NEXT: s_sub_i32 s2, s0, s1
; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000 ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result ret i32 %result
} }
define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) { define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i32: ; GFX6-LABEL: s_ssubsat_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1 ; GFX6-NEXT: s_max_i32 s2, s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1 ; GFX6-NEXT: s_min_i32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1 ; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i32: ; GFX8-LABEL: s_ssubsat_i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1 ; GFX8-NEXT: s_max_i32 s2, s0, -1
; GFX8-NEXT: s_cselect_b32 s2, s0, -1 ; GFX8-NEXT: s_min_i32 s3, s0, -1
; GFX8-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX8-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_cselect_b32 s3, s0, -1
; GFX8-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX8-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX8-NEXT: s_cmp_gt_i32 s2, s1 ; GFX8-NEXT: s_max_i32 s1, s2, s1
; GFX8-NEXT: s_cselect_b32 s1, s2, s1 ; GFX8-NEXT: s_min_i32 s1, s1, s3
; GFX8-NEXT: s_cmp_lt_i32 s1, s3
; GFX8-NEXT: s_cselect_b32 s1, s1, s3
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i32: ; GFX9-LABEL: s_ssubsat_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp ; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_i32: ; GFX10-LABEL: s_ssubsat_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp ; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result ret i32 %result
} }
define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) { define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX6-LABEL: ssubsat_i32_sv: ; GFX6-LABEL: ssubsat_i32_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1 ; GFX6-NEXT: s_max_i32 s1, s0, -1
; GFX6-NEXT: s_cselect_b32 s1, s0, -1 ; GFX6-NEXT: s_min_i32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000 ; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX6-NEXT: v_max_i32_e32 v0, s1, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s1, v0
; GFX6-NEXT: v_min_i32_e32 v0, s2, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: ssubsat_i32_sv: ; GFX8-LABEL: ssubsat_i32_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1 ; GFX8-NEXT: s_max_i32 s1, s0, -1
; GFX8-NEXT: s_cselect_b32 s1, s0, -1 ; GFX8-NEXT: s_min_i32 s2, s0, -1
; GFX8-NEXT: s_sub_i32 s1, s1, 0x7fffffff ; GFX8-NEXT: s_sub_i32 s1, s1, 0x7fffffff
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_cselect_b32 s2, s0, -1
; GFX8-NEXT: s_sub_i32 s2, s2, 0x80000000 ; GFX8-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX8-NEXT: v_max_i32_e32 v0, s1, v0 ; GFX8-NEXT: v_max_i32_e32 v0, s1, v0
; GFX8-NEXT: v_min_i32_e32 v0, s2, v0 ; GFX8-NEXT: v_min_i32_e32 v0, s2, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: ssubsat_i32_sv: ; GFX9-LABEL: ssubsat_i32_sv:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result ret <2 x i32> %result
} }
define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) { define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i32: ; GFX6-LABEL: s_ssubsat_v2i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, -1 ; GFX6-NEXT: s_max_i32 s6, s0, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s4 ; GFX6-NEXT: s_sub_i32 s6, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, -1 ; GFX6-NEXT: s_min_i32 s7, s0, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s5 ; GFX6-NEXT: s_sub_i32 s7, s7, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s2 ; GFX6-NEXT: s_max_i32 s2, s6, s2
; GFX6-NEXT: s_cselect_b32 s2, s6, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s7
; GFX6-NEXT: s_cmp_lt_i32 s2, s7
; GFX6-NEXT: s_cselect_b32 s2, s2, s7
; GFX6-NEXT: s_sub_i32 s0, s0, s2 ; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s2, s1, -1
; GFX6-NEXT: s_cselect_b32 s2, s1, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s4 ; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s4, s1, -1
; GFX6-NEXT: s_cselect_b32 s4, s1, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s5 ; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_gt_i32 s2, s3 ; GFX6-NEXT: s_max_i32 s2, s2, s3
; GFX6-NEXT: s_cselect_b32 s2, s2, s3 ; GFX6-NEXT: s_min_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v2i32: ; GFX8-LABEL: s_ssubsat_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s4, -2 ; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: s_cselect_b32 s6, s0, -1 ; GFX8-NEXT: s_max_i32 s6, s0, -1
; GFX8-NEXT: s_sub_i32 s6, s6, s4 ; GFX8-NEXT: s_sub_i32 s6, s6, s4
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s5, 1 ; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: s_cselect_b32 s7, s0, -1 ; GFX8-NEXT: s_min_i32 s7, s0, -1
; GFX8-NEXT: s_sub_i32 s7, s7, s5 ; GFX8-NEXT: s_sub_i32 s7, s7, s5
; GFX8-NEXT: s_cmp_gt_i32 s6, s2 ; GFX8-NEXT: s_max_i32 s2, s6, s2
; GFX8-NEXT: s_cselect_b32 s2, s6, s2 ; GFX8-NEXT: s_min_i32 s2, s2, s7
; GFX8-NEXT: s_cmp_lt_i32 s2, s7
; GFX8-NEXT: s_cselect_b32 s2, s2, s7
; GFX8-NEXT: s_sub_i32 s0, s0, s2 ; GFX8-NEXT: s_sub_i32 s0, s0, s2
; GFX8-NEXT: s_cmp_gt_i32 s1, -1 ; GFX8-NEXT: s_max_i32 s2, s1, -1
; GFX8-NEXT: s_cselect_b32 s2, s1, -1
; GFX8-NEXT: s_sub_i32 s2, s2, s4 ; GFX8-NEXT: s_sub_i32 s2, s2, s4
; GFX8-NEXT: s_cmp_lt_i32 s1, -1 ; GFX8-NEXT: s_min_i32 s4, s1, -1
; GFX8-NEXT: s_cselect_b32 s4, s1, -1
; GFX8-NEXT: s_sub_i32 s4, s4, s5 ; GFX8-NEXT: s_sub_i32 s4, s4, s5
; GFX8-NEXT: s_cmp_gt_i32 s2, s3 ; GFX8-NEXT: s_max_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s4
; GFX8-NEXT: s_cmp_lt_i32 s2, s4
; GFX8-NEXT: s_cselect_b32 s2, s2, s4
; GFX8-NEXT: s_sub_i32 s1, s1, s2 ; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v2i32: ; GFX9-LABEL: s_ssubsat_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp ; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result ret <3 x i32> %result
} }
define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) { define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v3i32: ; GFX6-LABEL: s_ssubsat_v3i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s6, -2 ; GFX6-NEXT: s_brev_b32 s6, -2
; GFX6-NEXT: s_cselect_b32 s8, s0, -1 ; GFX6-NEXT: s_max_i32 s8, s0, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s6 ; GFX6-NEXT: s_sub_i32 s8, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s7, 1 ; GFX6-NEXT: s_brev_b32 s7, 1
; GFX6-NEXT: s_cselect_b32 s9, s0, -1 ; GFX6-NEXT: s_min_i32 s9, s0, -1
; GFX6-NEXT: s_max_i32 s3, s8, s3
; GFX6-NEXT: s_sub_i32 s9, s9, s7 ; GFX6-NEXT: s_sub_i32 s9, s9, s7
; GFX6-NEXT: s_cmp_gt_i32 s8, s3 ; GFX6-NEXT: s_min_i32 s3, s3, s9
; GFX6-NEXT: s_cselect_b32 s3, s8, s3
; GFX6-NEXT: s_cmp_lt_i32 s3, s9
; GFX6-NEXT: s_cselect_b32 s3, s3, s9
; GFX6-NEXT: s_sub_i32 s0, s0, s3 ; GFX6-NEXT: s_sub_i32 s0, s0, s3
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s3, s1, -1
; GFX6-NEXT: s_cselect_b32 s3, s1, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s6 ; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s8, s1, -1
; GFX6-NEXT: s_cselect_b32 s8, s1, -1 ; GFX6-NEXT: s_max_i32 s3, s3, s4
; GFX6-NEXT: s_sub_i32 s8, s8, s7 ; GFX6-NEXT: s_sub_i32 s8, s8, s7
; GFX6-NEXT: s_cmp_gt_i32 s3, s4 ; GFX6-NEXT: s_min_i32 s3, s3, s8
; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s3, s8
; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_sub_i32 s1, s1, s3 ; GFX6-NEXT: s_sub_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_max_i32 s3, s2, -1
; GFX6-NEXT: s_cselect_b32 s3, s2, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s6 ; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_cmp_lt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s4, s2, -1
; GFX6-NEXT: s_cselect_b32 s4, s2, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s7 ; GFX6-NEXT: s_sub_i32 s4, s4, s7
; GFX6-NEXT: s_cmp_gt_i32 s3, s5 ; GFX6-NEXT: s_max_i32 s3, s3, s5
; GFX6-NEXT: s_cselect_b32 s3, s3, s5 ; GFX6-NEXT: s_min_i32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s3, s4
; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_sub_i32 s2, s2, s3 ; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v3i32: ; GFX8-LABEL: s_ssubsat_v3i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s6, -2 ; GFX8-NEXT: s_brev_b32 s6, -2
; GFX8-NEXT: s_cselect_b32 s8, s0, -1 ; GFX8-NEXT: s_max_i32 s8, s0, -1
; GFX8-NEXT: s_sub_i32 s8, s8, s6 ; GFX8-NEXT: s_sub_i32 s8, s8, s6
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s7, 1 ; GFX8-NEXT: s_brev_b32 s7, 1
; GFX8-NEXT: s_cselect_b32 s9, s0, -1 ; GFX8-NEXT: s_min_i32 s9, s0, -1
; GFX8-NEXT: s_max_i32 s3, s8, s3
; GFX8-NEXT: s_sub_i32 s9, s9, s7 ; GFX8-NEXT: s_sub_i32 s9, s9, s7
; GFX8-NEXT: s_cmp_gt_i32 s8, s3 ; GFX8-NEXT: s_min_i32 s3, s3, s9
; GFX8-NEXT: s_cselect_b32 s3, s8, s3
; GFX8-NEXT: s_cmp_lt_i32 s3, s9
; GFX8-NEXT: s_cselect_b32 s3, s3, s9
; GFX8-NEXT: s_sub_i32 s0, s0, s3 ; GFX8-NEXT: s_sub_i32 s0, s0, s3
; GFX8-NEXT: s_cmp_gt_i32 s1, -1 ; GFX8-NEXT: s_max_i32 s3, s1, -1
; GFX8-NEXT: s_cselect_b32 s3, s1, -1
; GFX8-NEXT: s_sub_i32 s3, s3, s6 ; GFX8-NEXT: s_sub_i32 s3, s3, s6
; GFX8-NEXT: s_cmp_lt_i32 s1, -1 ; GFX8-NEXT: s_min_i32 s8, s1, -1
; GFX8-NEXT: s_cselect_b32 s8, s1, -1 ; GFX8-NEXT: s_max_i32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s8, s8, s7 ; GFX8-NEXT: s_sub_i32 s8, s8, s7
; GFX8-NEXT: s_cmp_gt_i32 s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s8
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s8
; GFX8-NEXT: s_cselect_b32 s3, s3, s8
; GFX8-NEXT: s_sub_i32 s1, s1, s3 ; GFX8-NEXT: s_sub_i32 s1, s1, s3
; GFX8-NEXT: s_cmp_gt_i32 s2, -1 ; GFX8-NEXT: s_max_i32 s3, s2, -1
; GFX8-NEXT: s_cselect_b32 s3, s2, -1
; GFX8-NEXT: s_sub_i32 s3, s3, s6 ; GFX8-NEXT: s_sub_i32 s3, s3, s6
; GFX8-NEXT: s_cmp_lt_i32 s2, -1 ; GFX8-NEXT: s_min_i32 s4, s2, -1
; GFX8-NEXT: s_cselect_b32 s4, s2, -1
; GFX8-NEXT: s_sub_i32 s4, s4, s7 ; GFX8-NEXT: s_sub_i32 s4, s4, s7
; GFX8-NEXT: s_cmp_gt_i32 s3, s5 ; GFX8-NEXT: s_max_i32 s3, s3, s5
; GFX8-NEXT: s_cselect_b32 s3, s3, s5 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s4
; GFX8-NEXT: s_cselect_b32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s2, s2, s3 ; GFX8-NEXT: s_sub_i32 s2, s2, s3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v3i32: ; GFX9-LABEL: s_ssubsat_v3i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5 ; GFX9-NEXT: v_mov_b32_e32 v2, s5
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result ret <4 x i32> %result
} }
define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) { define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v4i32: ; GFX6-LABEL: s_ssubsat_v4i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s8, -2 ; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, -1 ; GFX6-NEXT: s_max_i32 s10, s0, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s8 ; GFX6-NEXT: s_sub_i32 s10, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s9, 1 ; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, -1 ; GFX6-NEXT: s_min_i32 s11, s0, -1
; GFX6-NEXT: s_max_i32 s4, s10, s4
; GFX6-NEXT: s_sub_i32 s11, s11, s9 ; GFX6-NEXT: s_sub_i32 s11, s11, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s4 ; GFX6-NEXT: s_min_i32 s4, s4, s11
; GFX6-NEXT: s_cselect_b32 s4, s10, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s11
; GFX6-NEXT: s_cselect_b32 s4, s4, s11
; GFX6-NEXT: s_sub_i32 s0, s0, s4 ; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s4, s1, -1
; GFX6-NEXT: s_cselect_b32 s4, s1, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s8 ; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s10, s1, -1
; GFX6-NEXT: s_cselect_b32 s10, s1, -1 ; GFX6-NEXT: s_max_i32 s4, s4, s5
; GFX6-NEXT: s_sub_i32 s10, s10, s9 ; GFX6-NEXT: s_sub_i32 s10, s10, s9
; GFX6-NEXT: s_cmp_gt_i32 s4, s5 ; GFX6-NEXT: s_min_i32 s4, s4, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_cmp_lt_i32 s4, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s10
; GFX6-NEXT: s_sub_i32 s1, s1, s4 ; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_max_i32 s4, s2, -1
; GFX6-NEXT: s_cselect_b32 s4, s2, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s8 ; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_cmp_lt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s5, s2, -1
; GFX6-NEXT: s_cselect_b32 s5, s2, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s9 ; GFX6-NEXT: s_sub_i32 s5, s5, s9
; GFX6-NEXT: s_cmp_gt_i32 s4, s6 ; GFX6-NEXT: s_max_i32 s4, s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6 ; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_lt_i32 s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_sub_i32 s2, s2, s4 ; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_gt_i32 s3, -1 ; GFX6-NEXT: s_max_i32 s4, s3, -1
; GFX6-NEXT: s_cselect_b32 s4, s3, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s8 ; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_cmp_lt_i32 s3, -1 ; GFX6-NEXT: s_min_i32 s5, s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s9 ; GFX6-NEXT: s_sub_i32 s5, s5, s9
; GFX6-NEXT: s_cmp_gt_i32 s4, s7 ; GFX6-NEXT: s_max_i32 s4, s4, s7
; GFX6-NEXT: s_cselect_b32 s4, s4, s7 ; GFX6-NEXT: s_min_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_lt_i32 s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v4i32: ; GFX8-LABEL: s_ssubsat_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s8, -2 ; GFX8-NEXT: s_brev_b32 s8, -2
; GFX8-NEXT: s_cselect_b32 s10, s0, -1 ; GFX8-NEXT: s_max_i32 s10, s0, -1
; GFX8-NEXT: s_sub_i32 s10, s10, s8 ; GFX8-NEXT: s_sub_i32 s10, s10, s8
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s9, 1 ; GFX8-NEXT: s_brev_b32 s9, 1
; GFX8-NEXT: s_cselect_b32 s11, s0, -1 ; GFX8-NEXT: s_min_i32 s11, s0, -1
; GFX8-NEXT: s_max_i32 s4, s10, s4
; GFX8-NEXT: s_sub_i32 s11, s11, s9 ; GFX8-NEXT: s_sub_i32 s11, s11, s9
; GFX8-NEXT: s_cmp_gt_i32 s10, s4 ; GFX8-NEXT: s_min_i32 s4, s4, s11
; GFX8-NEXT: s_cselect_b32 s4, s10, s4
; GFX8-NEXT: s_cmp_lt_i32 s4, s11
; GFX8-NEXT: s_cselect_b32 s4, s4, s11
; GFX8-NEXT: s_sub_i32 s0, s0, s4 ; GFX8-NEXT: s_sub_i32 s0, s0, s4
; GFX8-NEXT: s_cmp_gt_i32 s1, -1 ; GFX8-NEXT: s_max_i32 s4, s1, -1
; GFX8-NEXT: s_cselect_b32 s4, s1, -1
; GFX8-NEXT: s_sub_i32 s4, s4, s8 ; GFX8-NEXT: s_sub_i32 s4, s4, s8
; GFX8-NEXT: s_cmp_lt_i32 s1, -1 ; GFX8-NEXT: s_min_i32 s10, s1, -1
; GFX8-NEXT: s_cselect_b32 s10, s1, -1 ; GFX8-NEXT: s_max_i32 s4, s4, s5
; GFX8-NEXT: s_sub_i32 s10, s10, s9 ; GFX8-NEXT: s_sub_i32 s10, s10, s9
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s10
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s10
; GFX8-NEXT: s_cselect_b32 s4, s4, s10
; GFX8-NEXT: s_sub_i32 s1, s1, s4 ; GFX8-NEXT: s_sub_i32 s1, s1, s4
; GFX8-NEXT: s_cmp_gt_i32 s2, -1 ; GFX8-NEXT: s_max_i32 s4, s2, -1
; GFX8-NEXT: s_cselect_b32 s4, s2, -1
; GFX8-NEXT: s_sub_i32 s4, s4, s8 ; GFX8-NEXT: s_sub_i32 s4, s4, s8
; GFX8-NEXT: s_cmp_lt_i32 s2, -1 ; GFX8-NEXT: s_min_i32 s5, s2, -1
; GFX8-NEXT: s_cselect_b32 s5, s2, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s9 ; GFX8-NEXT: s_sub_i32 s5, s5, s9
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_sub_i32 s2, s2, s4 ; GFX8-NEXT: s_sub_i32 s2, s2, s4
; GFX8-NEXT: s_cmp_gt_i32 s3, -1 ; GFX8-NEXT: s_max_i32 s4, s3, -1
; GFX8-NEXT: s_cselect_b32 s4, s3, -1
; GFX8-NEXT: s_sub_i32 s4, s4, s8 ; GFX8-NEXT: s_sub_i32 s4, s4, s8
; GFX8-NEXT: s_cmp_lt_i32 s3, -1 ; GFX8-NEXT: s_min_i32 s5, s3, -1
; GFX8-NEXT: s_cselect_b32 s5, s3, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s9 ; GFX8-NEXT: s_sub_i32 s5, s5, s9
; GFX8-NEXT: s_cmp_gt_i32 s4, s7 ; GFX8-NEXT: s_max_i32 s4, s4, s7
; GFX8-NEXT: s_cselect_b32 s4, s4, s7 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cmp_lt_i32 s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: s_sub_i32 s3, s3, s4 ; GFX8-NEXT: s_sub_i32 s3, s3, s4
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v4i32: ; GFX9-LABEL: s_ssubsat_v4i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) { define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v5i32: ; GFX6-LABEL: s_ssubsat_v5i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s10, -2 ; GFX6-NEXT: s_brev_b32 s10, -2
; GFX6-NEXT: s_cselect_b32 s12, s0, -1 ; GFX6-NEXT: s_max_i32 s12, s0, -1
; GFX6-NEXT: s_sub_i32 s12, s12, s10 ; GFX6-NEXT: s_sub_i32 s12, s12, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s11, 1 ; GFX6-NEXT: s_brev_b32 s11, 1
; GFX6-NEXT: s_cselect_b32 s13, s0, -1 ; GFX6-NEXT: s_min_i32 s13, s0, -1
; GFX6-NEXT: s_max_i32 s5, s12, s5
; GFX6-NEXT: s_sub_i32 s13, s13, s11 ; GFX6-NEXT: s_sub_i32 s13, s13, s11
; GFX6-NEXT: s_cmp_gt_i32 s12, s5 ; GFX6-NEXT: s_min_i32 s5, s5, s13
; GFX6-NEXT: s_cselect_b32 s5, s12, s5
; GFX6-NEXT: s_cmp_lt_i32 s5, s13
; GFX6-NEXT: s_cselect_b32 s5, s5, s13
; GFX6-NEXT: s_sub_i32 s0, s0, s5 ; GFX6-NEXT: s_sub_i32 s0, s0, s5
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s5, s1, -1
; GFX6-NEXT: s_cselect_b32 s5, s1, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s10 ; GFX6-NEXT: s_sub_i32 s5, s5, s10
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s12, s1, -1
; GFX6-NEXT: s_cselect_b32 s12, s1, -1 ; GFX6-NEXT: s_max_i32 s5, s5, s6
; GFX6-NEXT: s_sub_i32 s12, s12, s11 ; GFX6-NEXT: s_sub_i32 s12, s12, s11
; GFX6-NEXT: s_cmp_gt_i32 s5, s6 ; GFX6-NEXT: s_min_i32 s5, s5, s12
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s5, s12
; GFX6-NEXT: s_cselect_b32 s5, s5, s12
; GFX6-NEXT: s_sub_i32 s1, s1, s5 ; GFX6-NEXT: s_sub_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_max_i32 s5, s2, -1
; GFX6-NEXT: s_cselect_b32 s5, s2, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s10 ; GFX6-NEXT: s_sub_i32 s5, s5, s10
; GFX6-NEXT: s_cmp_lt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s6, s2, -1
; GFX6-NEXT: s_cselect_b32 s6, s2, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s11 ; GFX6-NEXT: s_sub_i32 s6, s6, s11
; GFX6-NEXT: s_cmp_gt_i32 s5, s7 ; GFX6-NEXT: s_max_i32 s5, s5, s7
; GFX6-NEXT: s_cselect_b32 s5, s5, s7 ; GFX6-NEXT: s_min_i32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s5 ; GFX6-NEXT: s_sub_i32 s2, s2, s5
; GFX6-NEXT: s_cmp_gt_i32 s3, -1 ; GFX6-NEXT: s_max_i32 s5, s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s10 ; GFX6-NEXT: s_sub_i32 s5, s5, s10
; GFX6-NEXT: s_cmp_lt_i32 s3, -1 ; GFX6-NEXT: s_min_i32 s6, s3, -1
; GFX6-NEXT: s_cselect_b32 s6, s3, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s11 ; GFX6-NEXT: s_sub_i32 s6, s6, s11
; GFX6-NEXT: s_cmp_gt_i32 s5, s8 ; GFX6-NEXT: s_max_i32 s5, s5, s8
; GFX6-NEXT: s_cselect_b32 s5, s5, s8 ; GFX6-NEXT: s_min_i32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s5 ; GFX6-NEXT: s_sub_i32 s3, s3, s5
; GFX6-NEXT: s_cmp_gt_i32 s4, -1 ; GFX6-NEXT: s_max_i32 s5, s4, -1
; GFX6-NEXT: s_cselect_b32 s5, s4, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s10 ; GFX6-NEXT: s_sub_i32 s5, s5, s10
; GFX6-NEXT: s_cmp_lt_i32 s4, -1 ; GFX6-NEXT: s_min_i32 s6, s4, -1
; GFX6-NEXT: s_cselect_b32 s6, s4, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s11 ; GFX6-NEXT: s_sub_i32 s6, s6, s11
; GFX6-NEXT: s_cmp_gt_i32 s5, s9 ; GFX6-NEXT: s_max_i32 s5, s5, s9
; GFX6-NEXT: s_cselect_b32 s5, s5, s9 ; GFX6-NEXT: s_min_i32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_sub_i32 s4, s4, s5 ; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v5i32: ; GFX8-LABEL: s_ssubsat_v5i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s10, -2 ; GFX8-NEXT: s_brev_b32 s10, -2
; GFX8-NEXT: s_cselect_b32 s12, s0, -1 ; GFX8-NEXT: s_max_i32 s12, s0, -1
; GFX8-NEXT: s_sub_i32 s12, s12, s10 ; GFX8-NEXT: s_sub_i32 s12, s12, s10
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s11, 1 ; GFX8-NEXT: s_brev_b32 s11, 1
; GFX8-NEXT: s_cselect_b32 s13, s0, -1 ; GFX8-NEXT: s_min_i32 s13, s0, -1
; GFX8-NEXT: s_max_i32 s5, s12, s5
; GFX8-NEXT: s_sub_i32 s13, s13, s11 ; GFX8-NEXT: s_sub_i32 s13, s13, s11
; GFX8-NEXT: s_cmp_gt_i32 s12, s5 ; GFX8-NEXT: s_min_i32 s5, s5, s13
; GFX8-NEXT: s_cselect_b32 s5, s12, s5
; GFX8-NEXT: s_cmp_lt_i32 s5, s13
; GFX8-NEXT: s_cselect_b32 s5, s5, s13
; GFX8-NEXT: s_sub_i32 s0, s0, s5 ; GFX8-NEXT: s_sub_i32 s0, s0, s5
; GFX8-NEXT: s_cmp_gt_i32 s1, -1 ; GFX8-NEXT: s_max_i32 s5, s1, -1
; GFX8-NEXT: s_cselect_b32 s5, s1, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s10 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cmp_lt_i32 s1, -1 ; GFX8-NEXT: s_min_i32 s12, s1, -1
; GFX8-NEXT: s_cselect_b32 s12, s1, -1 ; GFX8-NEXT: s_max_i32 s5, s5, s6
; GFX8-NEXT: s_sub_i32 s12, s12, s11 ; GFX8-NEXT: s_sub_i32 s12, s12, s11
; GFX8-NEXT: s_cmp_gt_i32 s5, s6 ; GFX8-NEXT: s_min_i32 s5, s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s12
; GFX8-NEXT: s_cselect_b32 s5, s5, s12
; GFX8-NEXT: s_sub_i32 s1, s1, s5 ; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_cmp_gt_i32 s2, -1 ; GFX8-NEXT: s_max_i32 s5, s2, -1
; GFX8-NEXT: s_cselect_b32 s5, s2, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s10 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cmp_lt_i32 s2, -1 ; GFX8-NEXT: s_min_i32 s6, s2, -1
; GFX8-NEXT: s_cselect_b32 s6, s2, -1
; GFX8-NEXT: s_sub_i32 s6, s6, s11 ; GFX8-NEXT: s_sub_i32 s6, s6, s11
; GFX8-NEXT: s_cmp_gt_i32 s5, s7 ; GFX8-NEXT: s_max_i32 s5, s5, s7
; GFX8-NEXT: s_cselect_b32 s5, s5, s7 ; GFX8-NEXT: s_min_i32 s5, s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s6
; GFX8-NEXT: s_cselect_b32 s5, s5, s6
; GFX8-NEXT: s_sub_i32 s2, s2, s5 ; GFX8-NEXT: s_sub_i32 s2, s2, s5
; GFX8-NEXT: s_cmp_gt_i32 s3, -1 ; GFX8-NEXT: s_max_i32 s5, s3, -1
; GFX8-NEXT: s_cselect_b32 s5, s3, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s10 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cmp_lt_i32 s3, -1 ; GFX8-NEXT: s_min_i32 s6, s3, -1
; GFX8-NEXT: s_cselect_b32 s6, s3, -1
; GFX8-NEXT: s_sub_i32 s6, s6, s11 ; GFX8-NEXT: s_sub_i32 s6, s6, s11
; GFX8-NEXT: s_cmp_gt_i32 s5, s8 ; GFX8-NEXT: s_max_i32 s5, s5, s8
; GFX8-NEXT: s_cselect_b32 s5, s5, s8 ; GFX8-NEXT: s_min_i32 s5, s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s6
; GFX8-NEXT: s_cselect_b32 s5, s5, s6
; GFX8-NEXT: s_sub_i32 s3, s3, s5 ; GFX8-NEXT: s_sub_i32 s3, s3, s5
; GFX8-NEXT: s_cmp_gt_i32 s4, -1 ; GFX8-NEXT: s_max_i32 s5, s4, -1
; GFX8-NEXT: s_cselect_b32 s5, s4, -1
; GFX8-NEXT: s_sub_i32 s5, s5, s10 ; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_cmp_lt_i32 s4, -1 ; GFX8-NEXT: s_min_i32 s6, s4, -1
; GFX8-NEXT: s_cselect_b32 s6, s4, -1
; GFX8-NEXT: s_sub_i32 s6, s6, s11 ; GFX8-NEXT: s_sub_i32 s6, s6, s11
; GFX8-NEXT: s_cmp_gt_i32 s5, s9 ; GFX8-NEXT: s_max_i32 s5, s5, s9
; GFX8-NEXT: s_cselect_b32 s5, s5, s9 ; GFX8-NEXT: s_min_i32 s5, s5, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s6
; GFX8-NEXT: s_cselect_b32 s5, s5, s6
; GFX8-NEXT: s_sub_i32 s4, s4, s5 ; GFX8-NEXT: s_sub_i32 s4, s4, s5
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v5i32: ; GFX9-LABEL: s_ssubsat_v5i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s5 ; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
▲ Show 20 Lines • Show All 315 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v16i32: ; GFX6-LABEL: s_ssubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s32, -2 ; GFX6-NEXT: s_brev_b32 s32, -2
; GFX6-NEXT: s_cselect_b32 s34, s0, -1 ; GFX6-NEXT: s_max_i32 s34, s0, -1
; GFX6-NEXT: s_sub_i32 s34, s34, s32 ; GFX6-NEXT: s_sub_i32 s34, s34, s32
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s33, 1 ; GFX6-NEXT: s_brev_b32 s33, 1
; GFX6-NEXT: s_cselect_b32 s35, s0, -1 ; GFX6-NEXT: s_min_i32 s35, s0, -1
; GFX6-NEXT: s_max_i32 s16, s34, s16
; GFX6-NEXT: s_sub_i32 s35, s35, s33 ; GFX6-NEXT: s_sub_i32 s35, s35, s33
; GFX6-NEXT: s_cmp_gt_i32 s34, s16 ; GFX6-NEXT: s_min_i32 s16, s16, s35
; GFX6-NEXT: s_cselect_b32 s16, s34, s16
; GFX6-NEXT: s_cmp_lt_i32 s16, s35
; GFX6-NEXT: s_cselect_b32 s16, s16, s35
; GFX6-NEXT: s_sub_i32 s0, s0, s16 ; GFX6-NEXT: s_sub_i32 s0, s0, s16
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s16, s1, -1
; GFX6-NEXT: s_cselect_b32 s16, s1, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s34, s1, -1
; GFX6-NEXT: s_cselect_b32 s34, s1, -1 ; GFX6-NEXT: s_max_i32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s34, s34, s33 ; GFX6-NEXT: s_sub_i32 s34, s34, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s17 ; GFX6-NEXT: s_min_i32 s16, s16, s34
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s34
; GFX6-NEXT: s_cselect_b32 s16, s16, s34
; GFX6-NEXT: s_sub_i32 s1, s1, s16 ; GFX6-NEXT: s_sub_i32 s1, s1, s16
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_max_i32 s16, s2, -1
; GFX6-NEXT: s_cselect_b32 s16, s2, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s17, s2, -1
; GFX6-NEXT: s_cselect_b32 s17, s2, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s18 ; GFX6-NEXT: s_max_i32 s16, s16, s18
; GFX6-NEXT: s_cselect_b32 s16, s16, s18 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s2, s2, s16 ; GFX6-NEXT: s_sub_i32 s2, s2, s16
; GFX6-NEXT: s_cmp_gt_i32 s3, -1 ; GFX6-NEXT: s_max_i32 s16, s3, -1
; GFX6-NEXT: s_cselect_b32 s16, s3, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s3, -1 ; GFX6-NEXT: s_min_i32 s17, s3, -1
; GFX6-NEXT: s_cselect_b32 s17, s3, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s19 ; GFX6-NEXT: s_max_i32 s16, s16, s19
; GFX6-NEXT: s_cselect_b32 s16, s16, s19 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s3, s3, s16 ; GFX6-NEXT: s_sub_i32 s3, s3, s16
; GFX6-NEXT: s_cmp_gt_i32 s4, -1 ; GFX6-NEXT: s_max_i32 s16, s4, -1
; GFX6-NEXT: s_cselect_b32 s16, s4, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s4, -1 ; GFX6-NEXT: s_min_i32 s17, s4, -1
; GFX6-NEXT: s_cselect_b32 s17, s4, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s20 ; GFX6-NEXT: s_max_i32 s16, s16, s20
; GFX6-NEXT: s_cselect_b32 s16, s16, s20 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s4, s4, s16 ; GFX6-NEXT: s_sub_i32 s4, s4, s16
; GFX6-NEXT: s_cmp_gt_i32 s5, -1 ; GFX6-NEXT: s_max_i32 s16, s5, -1
; GFX6-NEXT: s_cselect_b32 s16, s5, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s5, -1 ; GFX6-NEXT: s_min_i32 s17, s5, -1
; GFX6-NEXT: s_cselect_b32 s17, s5, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s21 ; GFX6-NEXT: s_max_i32 s16, s16, s21
; GFX6-NEXT: s_cselect_b32 s16, s16, s21 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s5, s5, s16 ; GFX6-NEXT: s_sub_i32 s5, s5, s16
; GFX6-NEXT: s_cmp_gt_i32 s6, -1 ; GFX6-NEXT: s_max_i32 s16, s6, -1
; GFX6-NEXT: s_cselect_b32 s16, s6, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s6, -1 ; GFX6-NEXT: s_min_i32 s17, s6, -1
; GFX6-NEXT: s_cselect_b32 s17, s6, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s22 ; GFX6-NEXT: s_max_i32 s16, s16, s22
; GFX6-NEXT: s_cselect_b32 s16, s16, s22 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s6, s6, s16 ; GFX6-NEXT: s_sub_i32 s6, s6, s16
; GFX6-NEXT: s_cmp_gt_i32 s7, -1 ; GFX6-NEXT: s_max_i32 s16, s7, -1
; GFX6-NEXT: s_cselect_b32 s16, s7, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s7, -1 ; GFX6-NEXT: s_min_i32 s17, s7, -1
; GFX6-NEXT: s_cselect_b32 s17, s7, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s23 ; GFX6-NEXT: s_max_i32 s16, s16, s23
; GFX6-NEXT: s_cselect_b32 s16, s16, s23 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s7, s7, s16 ; GFX6-NEXT: s_sub_i32 s7, s7, s16
; GFX6-NEXT: s_cmp_gt_i32 s8, -1 ; GFX6-NEXT: s_max_i32 s16, s8, -1
; GFX6-NEXT: s_cselect_b32 s16, s8, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s8, -1 ; GFX6-NEXT: s_min_i32 s17, s8, -1
; GFX6-NEXT: s_cselect_b32 s17, s8, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s24 ; GFX6-NEXT: s_max_i32 s16, s16, s24
; GFX6-NEXT: s_cselect_b32 s16, s16, s24 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s8, s8, s16 ; GFX6-NEXT: s_sub_i32 s8, s8, s16
; GFX6-NEXT: s_cmp_gt_i32 s9, -1 ; GFX6-NEXT: s_max_i32 s16, s9, -1
; GFX6-NEXT: s_cselect_b32 s16, s9, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s9, -1 ; GFX6-NEXT: s_min_i32 s17, s9, -1
; GFX6-NEXT: s_cselect_b32 s17, s9, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s25 ; GFX6-NEXT: s_max_i32 s16, s16, s25
; GFX6-NEXT: s_cselect_b32 s16, s16, s25 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_gt_i32 s10, -1 ; GFX6-NEXT: s_max_i32 s16, s10, -1
; GFX6-NEXT: s_cselect_b32 s16, s10, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s10, -1 ; GFX6-NEXT: s_min_i32 s17, s10, -1
; GFX6-NEXT: s_cselect_b32 s17, s10, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s26 ; GFX6-NEXT: s_max_i32 s16, s16, s26
; GFX6-NEXT: s_cselect_b32 s16, s16, s26 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s10, s10, s16 ; GFX6-NEXT: s_sub_i32 s10, s10, s16
; GFX6-NEXT: s_cmp_gt_i32 s11, -1 ; GFX6-NEXT: s_max_i32 s16, s11, -1
; GFX6-NEXT: s_cselect_b32 s16, s11, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s11, -1 ; GFX6-NEXT: s_min_i32 s17, s11, -1
; GFX6-NEXT: s_cselect_b32 s17, s11, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s27 ; GFX6-NEXT: s_max_i32 s16, s16, s27
; GFX6-NEXT: s_cselect_b32 s16, s16, s27 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s11, s11, s16 ; GFX6-NEXT: s_sub_i32 s11, s11, s16
; GFX6-NEXT: s_cmp_gt_i32 s12, -1 ; GFX6-NEXT: s_max_i32 s16, s12, -1
; GFX6-NEXT: s_cselect_b32 s16, s12, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s12, -1 ; GFX6-NEXT: s_min_i32 s17, s12, -1
; GFX6-NEXT: s_cselect_b32 s17, s12, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s28 ; GFX6-NEXT: s_max_i32 s16, s16, s28
; GFX6-NEXT: s_cselect_b32 s16, s16, s28 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s12, s12, s16 ; GFX6-NEXT: s_sub_i32 s12, s12, s16
; GFX6-NEXT: s_cmp_gt_i32 s13, -1 ; GFX6-NEXT: s_max_i32 s16, s13, -1
; GFX6-NEXT: s_cselect_b32 s16, s13, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s13, -1 ; GFX6-NEXT: s_min_i32 s17, s13, -1
; GFX6-NEXT: s_cselect_b32 s17, s13, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s29 ; GFX6-NEXT: s_max_i32 s16, s16, s29
; GFX6-NEXT: s_cselect_b32 s16, s16, s29 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s13, s13, s16 ; GFX6-NEXT: s_sub_i32 s13, s13, s16
; GFX6-NEXT: s_cmp_gt_i32 s14, -1 ; GFX6-NEXT: s_max_i32 s16, s14, -1
; GFX6-NEXT: s_cselect_b32 s16, s14, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s14, -1 ; GFX6-NEXT: s_min_i32 s17, s14, -1
; GFX6-NEXT: s_cselect_b32 s17, s14, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s30 ; GFX6-NEXT: s_max_i32 s16, s16, s30
; GFX6-NEXT: s_cselect_b32 s16, s16, s30 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s14, s14, s16 ; GFX6-NEXT: s_sub_i32 s14, s14, s16
; GFX6-NEXT: s_cmp_gt_i32 s15, -1 ; GFX6-NEXT: s_max_i32 s16, s15, -1
; GFX6-NEXT: s_cselect_b32 s16, s15, -1
; GFX6-NEXT: s_sub_i32 s16, s16, s32 ; GFX6-NEXT: s_sub_i32 s16, s16, s32
; GFX6-NEXT: s_cmp_lt_i32 s15, -1 ; GFX6-NEXT: s_min_i32 s17, s15, -1
; GFX6-NEXT: s_cselect_b32 s17, s15, -1
; GFX6-NEXT: s_sub_i32 s17, s17, s33 ; GFX6-NEXT: s_sub_i32 s17, s17, s33
; GFX6-NEXT: s_cmp_gt_i32 s16, s31 ; GFX6-NEXT: s_max_i32 s16, s16, s31
; GFX6-NEXT: s_cselect_b32 s16, s16, s31 ; GFX6-NEXT: s_min_i32 s16, s16, s17
; GFX6-NEXT: s_cmp_lt_i32 s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_sub_i32 s15, s15, s16 ; GFX6-NEXT: s_sub_i32 s15, s15, s16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v16i32: ; GFX8-LABEL: s_ssubsat_v16i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_cmp_gt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s32, -2 ; GFX8-NEXT: s_brev_b32 s32, -2
; GFX8-NEXT: s_cselect_b32 s34, s0, -1 ; GFX8-NEXT: s_max_i32 s34, s0, -1
; GFX8-NEXT: s_sub_i32 s34, s34, s32 ; GFX8-NEXT: s_sub_i32 s34, s34, s32
; GFX8-NEXT: s_cmp_lt_i32 s0, -1
; GFX8-NEXT: s_brev_b32 s33, 1 ; GFX8-NEXT: s_brev_b32 s33, 1
; GFX8-NEXT: s_cselect_b32 s35, s0, -1 ; GFX8-NEXT: s_min_i32 s35, s0, -1
; GFX8-NEXT: s_max_i32 s16, s34, s16
; GFX8-NEXT: s_sub_i32 s35, s35, s33 ; GFX8-NEXT: s_sub_i32 s35, s35, s33
; GFX8-NEXT: s_cmp_gt_i32 s34, s16 ; GFX8-NEXT: s_min_i32 s16, s16, s35
; GFX8-NEXT: s_cselect_b32 s16, s34, s16
; GFX8-NEXT: s_cmp_lt_i32 s16, s35
; GFX8-NEXT: s_cselect_b32 s16, s16, s35
; GFX8-NEXT: s_sub_i32 s0, s0, s16 ; GFX8-NEXT: s_sub_i32 s0, s0, s16
; GFX8-NEXT: s_cmp_gt_i32 s1, -1 ; GFX8-NEXT: s_max_i32 s16, s1, -1
; GFX8-NEXT: s_cselect_b32 s16, s1, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s1, -1 ; GFX8-NEXT: s_min_i32 s34, s1, -1
; GFX8-NEXT: s_cselect_b32 s34, s1, -1 ; GFX8-NEXT: s_max_i32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s34, s34, s33 ; GFX8-NEXT: s_sub_i32 s34, s34, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s17 ; GFX8-NEXT: s_min_i32 s16, s16, s34
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s34
; GFX8-NEXT: s_cselect_b32 s16, s16, s34
; GFX8-NEXT: s_sub_i32 s1, s1, s16 ; GFX8-NEXT: s_sub_i32 s1, s1, s16
; GFX8-NEXT: s_cmp_gt_i32 s2, -1 ; GFX8-NEXT: s_max_i32 s16, s2, -1
; GFX8-NEXT: s_cselect_b32 s16, s2, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s2, -1 ; GFX8-NEXT: s_min_i32 s17, s2, -1
; GFX8-NEXT: s_cselect_b32 s17, s2, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s18 ; GFX8-NEXT: s_max_i32 s16, s16, s18
; GFX8-NEXT: s_cselect_b32 s16, s16, s18 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s2, s2, s16 ; GFX8-NEXT: s_sub_i32 s2, s2, s16
; GFX8-NEXT: s_cmp_gt_i32 s3, -1 ; GFX8-NEXT: s_max_i32 s16, s3, -1
; GFX8-NEXT: s_cselect_b32 s16, s3, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s3, -1 ; GFX8-NEXT: s_min_i32 s17, s3, -1
; GFX8-NEXT: s_cselect_b32 s17, s3, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s19 ; GFX8-NEXT: s_max_i32 s16, s16, s19
; GFX8-NEXT: s_cselect_b32 s16, s16, s19 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s3, s3, s16 ; GFX8-NEXT: s_sub_i32 s3, s3, s16
; GFX8-NEXT: s_cmp_gt_i32 s4, -1 ; GFX8-NEXT: s_max_i32 s16, s4, -1
; GFX8-NEXT: s_cselect_b32 s16, s4, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s4, -1 ; GFX8-NEXT: s_min_i32 s17, s4, -1
; GFX8-NEXT: s_cselect_b32 s17, s4, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s20 ; GFX8-NEXT: s_max_i32 s16, s16, s20
; GFX8-NEXT: s_cselect_b32 s16, s16, s20 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s4, s4, s16 ; GFX8-NEXT: s_sub_i32 s4, s4, s16
; GFX8-NEXT: s_cmp_gt_i32 s5, -1 ; GFX8-NEXT: s_max_i32 s16, s5, -1
; GFX8-NEXT: s_cselect_b32 s16, s5, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s5, -1 ; GFX8-NEXT: s_min_i32 s17, s5, -1
; GFX8-NEXT: s_cselect_b32 s17, s5, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s21 ; GFX8-NEXT: s_max_i32 s16, s16, s21
; GFX8-NEXT: s_cselect_b32 s16, s16, s21 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s5, s5, s16 ; GFX8-NEXT: s_sub_i32 s5, s5, s16
; GFX8-NEXT: s_cmp_gt_i32 s6, -1 ; GFX8-NEXT: s_max_i32 s16, s6, -1
; GFX8-NEXT: s_cselect_b32 s16, s6, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s6, -1 ; GFX8-NEXT: s_min_i32 s17, s6, -1
; GFX8-NEXT: s_cselect_b32 s17, s6, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s22 ; GFX8-NEXT: s_max_i32 s16, s16, s22
; GFX8-NEXT: s_cselect_b32 s16, s16, s22 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s6, s6, s16 ; GFX8-NEXT: s_sub_i32 s6, s6, s16
; GFX8-NEXT: s_cmp_gt_i32 s7, -1 ; GFX8-NEXT: s_max_i32 s16, s7, -1
; GFX8-NEXT: s_cselect_b32 s16, s7, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s7, -1 ; GFX8-NEXT: s_min_i32 s17, s7, -1
; GFX8-NEXT: s_cselect_b32 s17, s7, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s23 ; GFX8-NEXT: s_max_i32 s16, s16, s23
; GFX8-NEXT: s_cselect_b32 s16, s16, s23 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s7, s7, s16 ; GFX8-NEXT: s_sub_i32 s7, s7, s16
; GFX8-NEXT: s_cmp_gt_i32 s8, -1 ; GFX8-NEXT: s_max_i32 s16, s8, -1
; GFX8-NEXT: s_cselect_b32 s16, s8, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s8, -1 ; GFX8-NEXT: s_min_i32 s17, s8, -1
; GFX8-NEXT: s_cselect_b32 s17, s8, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s24 ; GFX8-NEXT: s_max_i32 s16, s16, s24
; GFX8-NEXT: s_cselect_b32 s16, s16, s24 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s8, s8, s16 ; GFX8-NEXT: s_sub_i32 s8, s8, s16
; GFX8-NEXT: s_cmp_gt_i32 s9, -1 ; GFX8-NEXT: s_max_i32 s16, s9, -1
; GFX8-NEXT: s_cselect_b32 s16, s9, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s9, -1 ; GFX8-NEXT: s_min_i32 s17, s9, -1
; GFX8-NEXT: s_cselect_b32 s17, s9, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s25 ; GFX8-NEXT: s_max_i32 s16, s16, s25
; GFX8-NEXT: s_cselect_b32 s16, s16, s25 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s9, s9, s16 ; GFX8-NEXT: s_sub_i32 s9, s9, s16
; GFX8-NEXT: s_cmp_gt_i32 s10, -1 ; GFX8-NEXT: s_max_i32 s16, s10, -1
; GFX8-NEXT: s_cselect_b32 s16, s10, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s10, -1 ; GFX8-NEXT: s_min_i32 s17, s10, -1
; GFX8-NEXT: s_cselect_b32 s17, s10, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s26 ; GFX8-NEXT: s_max_i32 s16, s16, s26
; GFX8-NEXT: s_cselect_b32 s16, s16, s26 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s10, s10, s16 ; GFX8-NEXT: s_sub_i32 s10, s10, s16
; GFX8-NEXT: s_cmp_gt_i32 s11, -1 ; GFX8-NEXT: s_max_i32 s16, s11, -1
; GFX8-NEXT: s_cselect_b32 s16, s11, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s11, -1 ; GFX8-NEXT: s_min_i32 s17, s11, -1
; GFX8-NEXT: s_cselect_b32 s17, s11, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s27 ; GFX8-NEXT: s_max_i32 s16, s16, s27
; GFX8-NEXT: s_cselect_b32 s16, s16, s27 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s11, s11, s16 ; GFX8-NEXT: s_sub_i32 s11, s11, s16
; GFX8-NEXT: s_cmp_gt_i32 s12, -1 ; GFX8-NEXT: s_max_i32 s16, s12, -1
; GFX8-NEXT: s_cselect_b32 s16, s12, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s12, -1 ; GFX8-NEXT: s_min_i32 s17, s12, -1
; GFX8-NEXT: s_cselect_b32 s17, s12, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s28 ; GFX8-NEXT: s_max_i32 s16, s16, s28
; GFX8-NEXT: s_cselect_b32 s16, s16, s28 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s12, s12, s16 ; GFX8-NEXT: s_sub_i32 s12, s12, s16
; GFX8-NEXT: s_cmp_gt_i32 s13, -1 ; GFX8-NEXT: s_max_i32 s16, s13, -1
; GFX8-NEXT: s_cselect_b32 s16, s13, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s13, -1 ; GFX8-NEXT: s_min_i32 s17, s13, -1
; GFX8-NEXT: s_cselect_b32 s17, s13, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s29 ; GFX8-NEXT: s_max_i32 s16, s16, s29
; GFX8-NEXT: s_cselect_b32 s16, s16, s29 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s13, s13, s16 ; GFX8-NEXT: s_sub_i32 s13, s13, s16
; GFX8-NEXT: s_cmp_gt_i32 s14, -1 ; GFX8-NEXT: s_max_i32 s16, s14, -1
; GFX8-NEXT: s_cselect_b32 s16, s14, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s14, -1 ; GFX8-NEXT: s_min_i32 s17, s14, -1
; GFX8-NEXT: s_cselect_b32 s17, s14, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s30 ; GFX8-NEXT: s_max_i32 s16, s16, s30
; GFX8-NEXT: s_cselect_b32 s16, s16, s30 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s14, s14, s16 ; GFX8-NEXT: s_sub_i32 s14, s14, s16
; GFX8-NEXT: s_cmp_gt_i32 s15, -1 ; GFX8-NEXT: s_max_i32 s16, s15, -1
; GFX8-NEXT: s_cselect_b32 s16, s15, -1
; GFX8-NEXT: s_sub_i32 s16, s16, s32 ; GFX8-NEXT: s_sub_i32 s16, s16, s32
; GFX8-NEXT: s_cmp_lt_i32 s15, -1 ; GFX8-NEXT: s_min_i32 s17, s15, -1
; GFX8-NEXT: s_cselect_b32 s17, s15, -1
; GFX8-NEXT: s_sub_i32 s17, s17, s33 ; GFX8-NEXT: s_sub_i32 s17, s17, s33
; GFX8-NEXT: s_cmp_gt_i32 s16, s31 ; GFX8-NEXT: s_max_i32 s16, s16, s31
; GFX8-NEXT: s_cselect_b32 s16, s16, s31 ; GFX8-NEXT: s_min_i32 s16, s16, s17
; GFX8-NEXT: s_cmp_lt_i32 s16, s17
; GFX8-NEXT: s_cselect_b32 s16, s16, s17
; GFX8-NEXT: s_sub_i32 s15, s15, s16 ; GFX8-NEXT: s_sub_i32 s15, s15, s16
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v16i32: ; GFX9-LABEL: s_ssubsat_v16i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s16 ; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17 ; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18 ; GFX9-NEXT: v_mov_b32_e32 v2, s18
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result ret i16 %result
} }
define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i16: ; GFX6-LABEL: s_ssubsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_max_i32 s2, s0, -1
; GFX6-NEXT: s_min_i32 s3, s0, -1
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff ; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000 ; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1 ; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1 ; GFX6-NEXT: s_min_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 16 ; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i16: ; GFX8-LABEL: s_ssubsat_i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s2, s0 ; GFX8-NEXT: s_sext_i32_i16 s2, s0
; GFX8-NEXT: s_sext_i32_i16 s3, -1 ; GFX8-NEXT: s_sext_i32_i16 s3, -1
; GFX8-NEXT: s_cmp_gt_i32 s2, s3 ; GFX8-NEXT: s_max_i32 s4, s2, s3
; GFX8-NEXT: s_cselect_b32 s4, s2, s3
; GFX8-NEXT: s_sub_i32 s4, s4, 0x7fff ; GFX8-NEXT: s_sub_i32 s4, s4, 0x7fff
; GFX8-NEXT: s_cmp_lt_i32 s2, s3 ; GFX8-NEXT: s_min_i32 s2, s2, s3
; GFX8-NEXT: s_cselect_b32 s2, s2, s3
; GFX8-NEXT: s_sub_i32 s2, s2, 0xffff8000
; GFX8-NEXT: s_sext_i32_i16 s3, s4 ; GFX8-NEXT: s_sext_i32_i16 s3, s4
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s3, s1 ; GFX8-NEXT: s_sub_i32 s2, s2, 0xffff8000
; GFX8-NEXT: s_cselect_b32 s1, s3, s1 ; GFX8-NEXT: s_max_i32 s1, s3, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_lt_i32 s1, s2 ; GFX8-NEXT: s_min_i32 s1, s1, s2
; GFX8-NEXT: s_cselect_b32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i16: ; GFX9-LABEL: s_ssubsat_i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp ; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_i16: ; GFX10-LABEL: s_ssubsat_i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result ret i16 %result
} }
define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) { define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: ssubsat_i16_sv: ; GFX6-LABEL: ssubsat_i16_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1 ; GFX6-NEXT: s_max_i32 s1, s0, -1
; GFX6-NEXT: s_cselect_b32 s1, s0, -1 ; GFX6-NEXT: s_min_i32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000 ; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX6-NEXT: v_max_i32_e32 v0, s1, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s1, v0
; GFX6-NEXT: v_min_i32_e32 v0, s2, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: ssubsat_i16_sv: ; GFX8-LABEL: ssubsat_i16_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s1, s0 ; GFX8-NEXT: s_sext_i32_i16 s1, s0
; GFX8-NEXT: s_sext_i32_i16 s2, -1 ; GFX8-NEXT: s_sext_i32_i16 s2, -1
; GFX8-NEXT: s_cmp_gt_i32 s1, s2 ; GFX8-NEXT: s_max_i32 s3, s1, s2
; GFX8-NEXT: s_cselect_b32 s3, s1, s2 ; GFX8-NEXT: s_min_i32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s3, s3, 0x7fff ; GFX8-NEXT: s_sub_i32 s3, s3, 0x7fff
; GFX8-NEXT: s_cmp_lt_i32 s1, s2
; GFX8-NEXT: s_cselect_b32 s1, s1, s2
; GFX8-NEXT: s_sub_i32 s1, s1, 0xffff8000 ; GFX8-NEXT: s_sub_i32 s1, s1, 0xffff8000
; GFX8-NEXT: v_max_i16_e32 v0, s3, v0 ; GFX8-NEXT: v_max_i16_e32 v0, s3, v0
; GFX8-NEXT: v_min_i16_e32 v0, s1, v0 ; GFX8-NEXT: v_min_i16_e32 v0, s1, v0
; GFX8-NEXT: v_sub_u16_e32 v0, s0, v0 ; GFX8-NEXT: v_sub_u16_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: ssubsat_i16_sv: ; GFX9-LABEL: ssubsat_i16_sv:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result ret <2 x i16> %result
} }
define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) { define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i16: ; GFX6-LABEL: s_ssubsat_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, -1 ; GFX6-NEXT: s_max_i32 s6, s0, -1
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_sub_i32 s6, s6, s4 ; GFX6-NEXT: s_sub_i32 s6, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, -1 ; GFX6-NEXT: s_min_i32 s7, s0, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s5 ; GFX6-NEXT: s_sub_i32 s7, s7, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s2 ; GFX6-NEXT: s_max_i32 s2, s6, s2
; GFX6-NEXT: s_cselect_b32 s2, s6, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s7
; GFX6-NEXT: s_cmp_lt_i32 s2, s7
; GFX6-NEXT: s_cselect_b32 s2, s2, s7
; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 16 ; GFX6-NEXT: s_lshl_b32 s2, s3, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s3, s1, -1
; GFX6-NEXT: s_cselect_b32 s3, s1, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s1, -1 ; GFX6-NEXT: s_min_i32 s4, s1, -1
; GFX6-NEXT: s_cselect_b32 s4, s1, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s5 ; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_gt_i32 s3, s2 ; GFX6-NEXT: s_max_i32 s2, s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2 ; GFX6-NEXT: s_min_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s1, s1, 16 ; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s2 ; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2 ; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v2i16: ; GFX8-LABEL: s_ssubsat_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_sext_i32_i16 s6, s0 ; GFX8-NEXT: s_sext_i32_i16 s6, s0
; GFX8-NEXT: s_sext_i32_i16 s7, -1 ; GFX8-NEXT: s_sext_i32_i16 s7, -1
; GFX8-NEXT: s_cmp_gt_i32 s6, s7 ; GFX8-NEXT: s_max_i32 s8, s6, s7
; GFX8-NEXT: s_movk_i32 s4, 0x7fff ; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: s_cselect_b32 s8, s6, s7
; GFX8-NEXT: s_sub_i32 s8, s8, s4 ; GFX8-NEXT: s_sub_i32 s8, s8, s4
; GFX8-NEXT: s_cmp_lt_i32 s6, s7 ; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_movk_i32 s5, 0x8000 ; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: s_cselect_b32 s6, s6, s7 ; GFX8-NEXT: s_min_i32 s6, s6, s7
; GFX8-NEXT: s_sub_i32 s6, s6, s5
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_gt_i32 s8, s1 ; GFX8-NEXT: s_sub_i32 s6, s6, s5
; GFX8-NEXT: s_cselect_b32 s1, s8, s1 ; GFX8-NEXT: s_max_i32 s1, s8, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_lt_i32 s1, s6 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_cselect_b32 s1, s1, s6 ; GFX8-NEXT: s_min_i32 s1, s1, s6
; GFX8-NEXT: s_sub_i32 s0, s0, s1 ; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s2 ; GFX8-NEXT: s_sext_i32_i16 s1, s2
; GFX8-NEXT: s_cmp_gt_i32 s1, s7 ; GFX8-NEXT: s_max_i32 s6, s1, s7
; GFX8-NEXT: s_cselect_b32 s6, s1, s7
; GFX8-NEXT: s_sub_i32 s4, s6, s4 ; GFX8-NEXT: s_sub_i32 s4, s6, s4
; GFX8-NEXT: s_cmp_lt_i32 s1, s7 ; GFX8-NEXT: s_min_i32 s1, s1, s7
; GFX8-NEXT: s_cselect_b32 s1, s1, s7
; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s4, s3 ; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_cselect_b32 s3, s4, s3 ; GFX8-NEXT: s_max_i32 s3, s4, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s1, s1 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_cmp_lt_i32 s3, s1 ; GFX8-NEXT: s_min_i32 s1, s3, s1
; GFX8-NEXT: s_cselect_b32 s1, s3, s1
; GFX8-NEXT: s_sub_i32 s1, s2, s1 ; GFX8-NEXT: s_sub_i32 s1, s2, s1
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_or_b32 s0, s0, s1 ; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v2i16: ; GFX9-LABEL: s_ssubsat_v2i16:
Show All 12 Lines; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <2 x i16> %result to i32 %cast = bitcast <2 x i16> %result to i32
ret i32 %cast ret i32 %cast
} }
define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) { define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: ssubsat_v2i16_sv: ; GFX6-LABEL: ssubsat_v2i16_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s2, -2 ; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: s_cselect_b32 s4, s0, -1 ; GFX6-NEXT: s_max_i32 s4, s0, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s4, s4, s2
; GFX6-NEXT: s_brev_b32 s3, 1 ; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: s_cselect_b32 s5, s0, -1 ; GFX6-NEXT: s_min_i32 s5, s0, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s3 ; GFX6-NEXT: s_sub_i32 s5, s5, s3
; GFX6-NEXT: v_max_i32_e32 v0, s4, v0 ; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_min_i32_e32 v0, s5, v0 ; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16 ; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1 ; GFX6-NEXT: s_max_i32 s1, s0, -1
; GFX6-NEXT: s_cselect_b32 s1, s0, -1
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_min_i32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s3 ; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: v_max_i32_e32 v1, s1, v1 ; GFX6-NEXT: v_max_i32_e32 v1, s1, v1
; GFX6-NEXT: v_min_i32_e32 v1, s2, v1 ; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff ; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1 ; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: ssubsat_v2i16_sv: ; GFX8-LABEL: ssubsat_v2i16_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: s_sext_i32_i16 s4, s0 ; GFX8-NEXT: s_sext_i32_i16 s4, s0
; GFX8-NEXT: s_sext_i32_i16 s5, -1 ; GFX8-NEXT: s_sext_i32_i16 s5, -1
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_max_i32 s6, s4, s5
; GFX8-NEXT: s_movk_i32 s2, 0x7fff ; GFX8-NEXT: s_movk_i32 s2, 0x7fff
; GFX8-NEXT: s_cselect_b32 s6, s4, s5
; GFX8-NEXT: s_sub_i32 s6, s6, s2 ; GFX8-NEXT: s_sub_i32 s6, s6, s2
; GFX8-NEXT: s_cmp_lt_i32 s4, s5
; GFX8-NEXT: s_movk_i32 s3, 0x8000 ; GFX8-NEXT: s_movk_i32 s3, 0x8000
; GFX8-NEXT: s_cselect_b32 s4, s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: s_sub_i32 s4, s4, s3 ; GFX8-NEXT: s_sub_i32 s4, s4, s3
; GFX8-NEXT: v_max_i16_e32 v1, s6, v0 ; GFX8-NEXT: v_max_i16_e32 v1, s6, v0
; GFX8-NEXT: v_min_i16_e32 v1, s4, v1 ; GFX8-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-NEXT: s_sext_i32_i16 s4, s1 ; GFX8-NEXT: s_sext_i32_i16 s4, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s5 ; GFX8-NEXT: s_max_i32 s6, s4, s5
; GFX8-NEXT: s_cselect_b32 s6, s4, s5
; GFX8-NEXT: s_sub_i32 s2, s6, s2 ; GFX8-NEXT: s_sub_i32 s2, s6, s2
; GFX8-NEXT: s_cmp_lt_i32 s4, s5 ; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_cselect_b32 s4, s4, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: s_sub_i32 s3, s4, s3 ; GFX8-NEXT: s_sub_i32 s3, s4, s3
; GFX8-NEXT: v_min_i16_e32 v0, s3, v0 ; GFX8-NEXT: v_min_i16_e32 v0, s3, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_sub_u16_e32 v1, s0, v1 ; GFX8-NEXT: v_sub_u16_e32 v1, s0, v1
; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <4 x i16> %result to <2 x float> %cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) { define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v4i16: ; GFX6-LABEL: s_ssubsat_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s8, -2 ; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, -1 ; GFX6-NEXT: s_max_i32 s10, s0, -1
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_sub_i32 s10, s10, s8 ; GFX6-NEXT: s_sub_i32 s10, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s9, 1 ; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, -1 ; GFX6-NEXT: s_min_i32 s11, s0, -1
; GFX6-NEXT: s_sub_i32 s11, s11, s9 ; GFX6-NEXT: s_sub_i32 s11, s11, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s4 ; GFX6-NEXT: s_max_i32 s4, s10, s4
; GFX6-NEXT: s_cselect_b32 s4, s10, s4 ; GFX6-NEXT: s_min_i32 s4, s4, s11
; GFX6-NEXT: s_cmp_lt_i32 s4, s11
; GFX6-NEXT: s_cselect_b32 s4, s4, s11
; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s4, s5, 16 ; GFX6-NEXT: s_lshl_b32 s4, s5, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s5, s1, -1
; GFX6-NEXT: s_cselect_b32 s5, s1, -1 ; GFX6-NEXT: s_min_i32 s10, s1, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s1, -1
; GFX6-NEXT: s_cselect_b32 s10, s1, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s9 ; GFX6-NEXT: s_sub_i32 s10, s10, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4 ; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s10
; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_max_i32 s5, s2, -1
; GFX6-NEXT: s_min_i32 s4, s4, s10
; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s4, s6, 16 ; GFX6-NEXT: s_lshl_b32 s4, s6, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s6, s2, -1
; GFX6-NEXT: s_cselect_b32 s5, s2, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s2, -1
; GFX6-NEXT: s_cselect_b32 s6, s2, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9 ; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4 ; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_max_i32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_min_i32 s6, s3, -1
; GFX6-NEXT: s_lshl_b32 s4, s7, 16 ; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s6, s3, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9 ; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4 ; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4 ; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s4, 0xffff ; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s4 ; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16 ; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4 ; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4 ; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_and_b32 s2, s3, s4 ; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v4i16: ; GFX8-LABEL: s_ssubsat_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_sext_i32_i16 s10, s0 ; GFX8-NEXT: s_sext_i32_i16 s10, s0
; GFX8-NEXT: s_sext_i32_i16 s11, -1 ; GFX8-NEXT: s_sext_i32_i16 s11, -1
; GFX8-NEXT: s_cmp_gt_i32 s10, s11 ; GFX8-NEXT: s_max_i32 s12, s10, s11
; GFX8-NEXT: s_movk_i32 s8, 0x7fff ; GFX8-NEXT: s_movk_i32 s8, 0x7fff
; GFX8-NEXT: s_cselect_b32 s12, s10, s11
; GFX8-NEXT: s_sub_i32 s12, s12, s8 ; GFX8-NEXT: s_sub_i32 s12, s12, s8
; GFX8-NEXT: s_cmp_lt_i32 s10, s11 ; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_movk_i32 s9, 0x8000 ; GFX8-NEXT: s_movk_i32 s9, 0x8000
; GFX8-NEXT: s_cselect_b32 s10, s10, s11 ; GFX8-NEXT: s_min_i32 s10, s10, s11
; GFX8-NEXT: s_sub_i32 s10, s10, s9
; GFX8-NEXT: s_sext_i32_i16 s12, s12 ; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_gt_i32 s12, s2 ; GFX8-NEXT: s_sub_i32 s10, s10, s9
; GFX8-NEXT: s_cselect_b32 s2, s12, s2 ; GFX8-NEXT: s_max_i32 s2, s12, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s10, s10 ; GFX8-NEXT: s_sext_i32_i16 s10, s10
; GFX8-NEXT: s_cmp_lt_i32 s2, s10 ; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_cselect_b32 s2, s2, s10 ; GFX8-NEXT: s_min_i32 s2, s2, s10
; GFX8-NEXT: s_sub_i32 s0, s0, s2 ; GFX8-NEXT: s_sub_i32 s0, s0, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s4 ; GFX8-NEXT: s_sext_i32_i16 s2, s4
; GFX8-NEXT: s_cmp_gt_i32 s2, s11 ; GFX8-NEXT: s_max_i32 s10, s2, s11
; GFX8-NEXT: s_cselect_b32 s10, s2, s11
; GFX8-NEXT: s_sub_i32 s10, s10, s8 ; GFX8-NEXT: s_sub_i32 s10, s10, s8
; GFX8-NEXT: s_cmp_lt_i32 s2, s11 ; GFX8-NEXT: s_min_i32 s2, s2, s11
; GFX8-NEXT: s_cselect_b32 s2, s2, s11
; GFX8-NEXT: s_sub_i32 s2, s2, s9
; GFX8-NEXT: s_sext_i32_i16 s10, s10 ; GFX8-NEXT: s_sext_i32_i16 s10, s10
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_gt_i32 s10, s6 ; GFX8-NEXT: s_sub_i32 s2, s2, s9
; GFX8-NEXT: s_cselect_b32 s6, s10, s6 ; GFX8-NEXT: s_max_i32 s6, s10, s6
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s2, s2 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_cmp_lt_i32 s6, s2 ; GFX8-NEXT: s_min_i32 s2, s6, s2
; GFX8-NEXT: s_cselect_b32 s2, s6, s2
; GFX8-NEXT: s_sub_i32 s2, s4, s2 ; GFX8-NEXT: s_sub_i32 s2, s4, s2
; GFX8-NEXT: s_sext_i32_i16 s4, s1 ; GFX8-NEXT: s_sext_i32_i16 s4, s1
; GFX8-NEXT: s_cmp_gt_i32 s4, s11 ; GFX8-NEXT: s_max_i32 s6, s4, s11
; GFX8-NEXT: s_cselect_b32 s6, s4, s11
; GFX8-NEXT: s_sub_i32 s6, s6, s8 ; GFX8-NEXT: s_sub_i32 s6, s6, s8
; GFX8-NEXT: s_cmp_lt_i32 s4, s11 ; GFX8-NEXT: s_min_i32 s4, s4, s11
; GFX8-NEXT: s_cselect_b32 s4, s4, s11 ; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_sub_i32 s4, s4, s9
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s6, s3 ; GFX8-NEXT: s_max_i32 s3, s6, s3
; GFX8-NEXT: s_cselect_b32 s3, s6, s3 ; GFX8-NEXT: s_sub_i32 s4, s4, s9
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s3, s4 ; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_cselect_b32 s3, s3, s4 ; GFX8-NEXT: s_min_i32 s3, s3, s4
; GFX8-NEXT: s_sub_i32 s1, s1, s3 ; GFX8-NEXT: s_sub_i32 s1, s1, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s5 ; GFX8-NEXT: s_sext_i32_i16 s3, s5
; GFX8-NEXT: s_cmp_gt_i32 s3, s11 ; GFX8-NEXT: s_max_i32 s4, s3, s11
; GFX8-NEXT: s_cselect_b32 s4, s3, s11
; GFX8-NEXT: s_sub_i32 s4, s4, s8 ; GFX8-NEXT: s_sub_i32 s4, s4, s8
; GFX8-NEXT: s_cmp_lt_i32 s3, s11 ; GFX8-NEXT: s_min_i32 s3, s3, s11
; GFX8-NEXT: s_cselect_b32 s3, s3, s11
; GFX8-NEXT: s_sub_i32 s3, s3, s9
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s7 ; GFX8-NEXT: s_sext_i32_i16 s6, s7
; GFX8-NEXT: s_cmp_gt_i32 s4, s6 ; GFX8-NEXT: s_sub_i32 s3, s3, s9
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s4, s3 ; GFX8-NEXT: s_min_i32 s3, s4, s3
; GFX8-NEXT: s_cselect_b32 s3, s4, s3
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_sub_i32 s3, s5, s3 ; GFX8-NEXT: s_sub_i32 s3, s5, s3
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_or_b32 s0, s0, s2 ; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_bfe_u32 s2, s3, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s3, 0x100000
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <6 x i16> %result to <3 x float> %cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast ret <3 x float> %cast
} }
define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) { define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v6i16: ; GFX6-LABEL: s_ssubsat_v6i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s12, -2 ; GFX6-NEXT: s_brev_b32 s12, -2
; GFX6-NEXT: s_cselect_b32 s14, s0, -1 ; GFX6-NEXT: s_max_i32 s14, s0, -1
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_sub_i32 s14, s14, s12 ; GFX6-NEXT: s_sub_i32 s14, s14, s12
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s13, 1 ; GFX6-NEXT: s_brev_b32 s13, 1
; GFX6-NEXT: s_cselect_b32 s15, s0, -1 ; GFX6-NEXT: s_min_i32 s15, s0, -1
; GFX6-NEXT: s_sub_i32 s15, s15, s13 ; GFX6-NEXT: s_sub_i32 s15, s15, s13
; GFX6-NEXT: s_cmp_gt_i32 s14, s6 ; GFX6-NEXT: s_max_i32 s6, s14, s6
; GFX6-NEXT: s_cselect_b32 s6, s14, s6 ; GFX6-NEXT: s_min_i32 s6, s6, s15
; GFX6-NEXT: s_cmp_lt_i32 s6, s15
; GFX6-NEXT: s_cselect_b32 s6, s6, s15
; GFX6-NEXT: s_sub_i32 s0, s0, s6
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s6, s7, 16 ; GFX6-NEXT: s_lshl_b32 s6, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s7, s1, -1
; GFX6-NEXT: s_cselect_b32 s7, s1, -1 ; GFX6-NEXT: s_min_i32 s14, s1, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12 ; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s1, -1
; GFX6-NEXT: s_cselect_b32 s14, s1, -1
; GFX6-NEXT: s_sub_i32 s14, s14, s13 ; GFX6-NEXT: s_sub_i32 s14, s14, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6 ; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s14
; GFX6-NEXT: s_cselect_b32 s6, s6, s14
; GFX6-NEXT: s_sub_i32 s1, s1, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_max_i32 s7, s2, -1
; GFX6-NEXT: s_min_i32 s6, s6, s14
; GFX6-NEXT: s_sub_i32 s1, s1, s6
; GFX6-NEXT: s_lshl_b32 s6, s8, 16 ; GFX6-NEXT: s_lshl_b32 s6, s8, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s8, s2, -1
; GFX6-NEXT: s_cselect_b32 s7, s2, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12 ; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s2, -1
; GFX6-NEXT: s_cselect_b32 s8, s2, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13 ; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6 ; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s2, s2, s6
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s6
; GFX6-NEXT: s_min_i32 s8, s3, -1
; GFX6-NEXT: s_lshl_b32 s6, s9, 16 ; GFX6-NEXT: s_lshl_b32 s6, s9, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s7, s3, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12 ; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s8, s3, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13 ; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6 ; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s4, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_min_i32 s8, s4, -1
; GFX6-NEXT: s_lshl_b32 s6, s10, 16 ; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s7, s4, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12 ; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s8, s4, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13 ; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6 ; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s5, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_min_i32 s8, s5, -1
; GFX6-NEXT: s_lshl_b32 s6, s11, 16 ; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s7, s5, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12 ; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s8, s5, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13 ; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6 ; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6 ; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s6 ; GFX6-NEXT: s_sub_i32 s5, s5, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s6, 0xffff ; GFX6-NEXT: s_mov_b32 s6, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s6 ; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s6 ; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6 ; GFX6-NEXT: s_and_b32 s1, s2, s6
; GFX6-NEXT: s_and_b32 s2, s3, s6 ; GFX6-NEXT: s_and_b32 s2, s3, s6
; GFX6-NEXT: s_ashr_i32 s5, s5, 16 ; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s6 ; GFX6-NEXT: s_and_b32 s3, s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6 ; GFX6-NEXT: s_and_b32 s2, s4, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v6i16: ; GFX8-LABEL: s_ssubsat_v6i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NEXT: s_sext_i32_i16 s14, s0 ; GFX8-NEXT: s_sext_i32_i16 s14, s0
; GFX8-NEXT: s_sext_i32_i16 s15, -1 ; GFX8-NEXT: s_sext_i32_i16 s15, -1
; GFX8-NEXT: s_cmp_gt_i32 s14, s15 ; GFX8-NEXT: s_max_i32 s16, s14, s15
; GFX8-NEXT: s_movk_i32 s12, 0x7fff ; GFX8-NEXT: s_movk_i32 s12, 0x7fff
; GFX8-NEXT: s_cselect_b32 s16, s14, s15
; GFX8-NEXT: s_sub_i32 s16, s16, s12 ; GFX8-NEXT: s_sub_i32 s16, s16, s12
; GFX8-NEXT: s_cmp_lt_i32 s14, s15 ; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_movk_i32 s13, 0x8000 ; GFX8-NEXT: s_movk_i32 s13, 0x8000
; GFX8-NEXT: s_cselect_b32 s14, s14, s15 ; GFX8-NEXT: s_min_i32 s14, s14, s15
; GFX8-NEXT: s_sub_i32 s14, s14, s13
; GFX8-NEXT: s_sext_i32_i16 s16, s16 ; GFX8-NEXT: s_sext_i32_i16 s16, s16
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_gt_i32 s16, s3 ; GFX8-NEXT: s_sub_i32 s14, s14, s13
; GFX8-NEXT: s_cselect_b32 s3, s16, s3 ; GFX8-NEXT: s_max_i32 s3, s16, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s14, s14 ; GFX8-NEXT: s_sext_i32_i16 s14, s14
; GFX8-NEXT: s_cmp_lt_i32 s3, s14 ; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_cselect_b32 s3, s3, s14 ; GFX8-NEXT: s_min_i32 s3, s3, s14
; GFX8-NEXT: s_sub_i32 s0, s0, s3 ; GFX8-NEXT: s_sub_i32 s0, s0, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s6 ; GFX8-NEXT: s_sext_i32_i16 s3, s6
; GFX8-NEXT: s_cmp_gt_i32 s3, s15 ; GFX8-NEXT: s_max_i32 s14, s3, s15
; GFX8-NEXT: s_cselect_b32 s14, s3, s15
; GFX8-NEXT: s_sub_i32 s14, s14, s12 ; GFX8-NEXT: s_sub_i32 s14, s14, s12
; GFX8-NEXT: s_cmp_lt_i32 s3, s15 ; GFX8-NEXT: s_min_i32 s3, s3, s15
; GFX8-NEXT: s_cselect_b32 s3, s3, s15
; GFX8-NEXT: s_sub_i32 s3, s3, s13
; GFX8-NEXT: s_sext_i32_i16 s14, s14 ; GFX8-NEXT: s_sext_i32_i16 s14, s14
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_cmp_gt_i32 s14, s9 ; GFX8-NEXT: s_sub_i32 s3, s3, s13
; GFX8-NEXT: s_cselect_b32 s9, s14, s9 ; GFX8-NEXT: s_max_i32 s9, s14, s9
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s3, s3 ; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_cmp_lt_i32 s9, s3 ; GFX8-NEXT: s_min_i32 s3, s9, s3
; GFX8-NEXT: s_cselect_b32 s3, s9, s3
; GFX8-NEXT: s_sub_i32 s3, s6, s3 ; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_sext_i32_i16 s6, s1 ; GFX8-NEXT: s_sext_i32_i16 s6, s1
; GFX8-NEXT: s_cmp_gt_i32 s6, s15 ; GFX8-NEXT: s_max_i32 s9, s6, s15
; GFX8-NEXT: s_cselect_b32 s9, s6, s15
; GFX8-NEXT: s_sub_i32 s9, s9, s12 ; GFX8-NEXT: s_sub_i32 s9, s9, s12
; GFX8-NEXT: s_cmp_lt_i32 s6, s15 ; GFX8-NEXT: s_min_i32 s6, s6, s15
; GFX8-NEXT: s_cselect_b32 s6, s6, s15 ; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_sub_i32 s6, s6, s13
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s9, s4 ; GFX8-NEXT: s_max_i32 s4, s9, s4
; GFX8-NEXT: s_cselect_b32 s4, s9, s4 ; GFX8-NEXT: s_sub_i32 s6, s6, s13
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_lt_i32 s4, s6 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s6 ; GFX8-NEXT: s_min_i32 s4, s4, s6
; GFX8-NEXT: s_sub_i32 s1, s1, s4 ; GFX8-NEXT: s_sub_i32 s1, s1, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s7 ; GFX8-NEXT: s_sext_i32_i16 s4, s7
; GFX8-NEXT: s_cmp_gt_i32 s4, s15 ; GFX8-NEXT: s_max_i32 s6, s4, s15
; GFX8-NEXT: s_cselect_b32 s6, s4, s15
; GFX8-NEXT: s_sub_i32 s6, s6, s12 ; GFX8-NEXT: s_sub_i32 s6, s6, s12
; GFX8-NEXT: s_cmp_lt_i32 s4, s15 ; GFX8-NEXT: s_min_i32 s4, s4, s15
; GFX8-NEXT: s_cselect_b32 s4, s4, s15
; GFX8-NEXT: s_sub_i32 s4, s4, s13
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s9, s10 ; GFX8-NEXT: s_sext_i32_i16 s9, s10
; GFX8-NEXT: s_cmp_gt_i32 s6, s9 ; GFX8-NEXT: s_sub_i32 s4, s4, s13
; GFX8-NEXT: s_cselect_b32 s6, s6, s9 ; GFX8-NEXT: s_max_i32 s6, s6, s9
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s6, s4 ; GFX8-NEXT: s_min_i32 s4, s6, s4
; GFX8-NEXT: s_cselect_b32 s4, s6, s4
; GFX8-NEXT: s_sub_i32 s4, s7, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s2 ; GFX8-NEXT: s_sext_i32_i16 s6, s2
; GFX8-NEXT: s_cmp_gt_i32 s6, s15 ; GFX8-NEXT: s_sub_i32 s4, s7, s4
; GFX8-NEXT: s_cselect_b32 s7, s6, s15 ; GFX8-NEXT: s_max_i32 s7, s6, s15
; GFX8-NEXT: s_sub_i32 s7, s7, s12 ; GFX8-NEXT: s_sub_i32 s7, s7, s12
; GFX8-NEXT: s_cmp_lt_i32 s6, s15 ; GFX8-NEXT: s_min_i32 s6, s6, s15
; GFX8-NEXT: s_cselect_b32 s6, s6, s15 ; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_sub_i32 s6, s6, s13
; GFX8-NEXT: s_sext_i32_i16 s7, s7 ; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_gt_i32 s7, s5 ; GFX8-NEXT: s_max_i32 s5, s7, s5
; GFX8-NEXT: s_cselect_b32 s5, s7, s5 ; GFX8-NEXT: s_sub_i32 s6, s6, s13
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_lt_i32 s5, s6 ; GFX8-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NEXT: s_cselect_b32 s5, s5, s6 ; GFX8-NEXT: s_min_i32 s5, s5, s6
; GFX8-NEXT: s_sub_i32 s2, s2, s5 ; GFX8-NEXT: s_sub_i32 s2, s2, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s8 ; GFX8-NEXT: s_sext_i32_i16 s5, s8
; GFX8-NEXT: s_cmp_gt_i32 s5, s15 ; GFX8-NEXT: s_max_i32 s6, s5, s15
; GFX8-NEXT: s_cselect_b32 s6, s5, s15
; GFX8-NEXT: s_sub_i32 s6, s6, s12 ; GFX8-NEXT: s_sub_i32 s6, s6, s12
; GFX8-NEXT: s_cmp_lt_i32 s5, s15 ; GFX8-NEXT: s_min_i32 s5, s5, s15
; GFX8-NEXT: s_cselect_b32 s5, s5, s15
; GFX8-NEXT: s_sub_i32 s5, s5, s13
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s7, s11 ; GFX8-NEXT: s_sext_i32_i16 s7, s11
; GFX8-NEXT: s_cmp_gt_i32 s6, s7 ; GFX8-NEXT: s_sub_i32 s5, s5, s13
; GFX8-NEXT: s_cselect_b32 s6, s6, s7 ; GFX8-NEXT: s_max_i32 s6, s6, s7
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s6, s5
; GFX8-NEXT: s_cselect_b32 s5, s6, s5
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16 ; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_min_i32 s5, s6, s5
; GFX8-NEXT: s_or_b32 s0, s0, s3 ; GFX8-NEXT: s_or_b32 s0, s0, s3
; GFX8-NEXT: s_bfe_u32 s3, s4, 0x100000 ; GFX8-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX8-NEXT: s_sub_i32 s5, s8, s5 ; GFX8-NEXT: s_sub_i32 s5, s8, s5
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16 ; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_or_b32 s1, s1, s3 ; GFX8-NEXT: s_or_b32 s1, s1, s3
; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000 ; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%cast = bitcast <8 x i16> %result to <4 x float> %cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast ret <4 x float> %cast
} }
define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) { define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v8i16: ; GFX6-LABEL: s_ssubsat_v8i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s16, -2 ; GFX6-NEXT: s_brev_b32 s16, -2
; GFX6-NEXT: s_cselect_b32 s18, s0, -1 ; GFX6-NEXT: s_max_i32 s18, s0, -1
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_sub_i32 s18, s18, s16 ; GFX6-NEXT: s_sub_i32 s18, s18, s16
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s17, 1 ; GFX6-NEXT: s_brev_b32 s17, 1
; GFX6-NEXT: s_cselect_b32 s19, s0, -1 ; GFX6-NEXT: s_min_i32 s19, s0, -1
; GFX6-NEXT: s_sub_i32 s19, s19, s17 ; GFX6-NEXT: s_sub_i32 s19, s19, s17
; GFX6-NEXT: s_cmp_gt_i32 s18, s8 ; GFX6-NEXT: s_max_i32 s8, s18, s8
; GFX6-NEXT: s_cselect_b32 s8, s18, s8 ; GFX6-NEXT: s_min_i32 s8, s8, s19
; GFX6-NEXT: s_cmp_lt_i32 s8, s19
; GFX6-NEXT: s_cselect_b32 s8, s8, s19
; GFX6-NEXT: s_sub_i32 s0, s0, s8
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s8, s9, 16 ; GFX6-NEXT: s_lshl_b32 s8, s9, 16
; GFX6-NEXT: s_cmp_gt_i32 s1, -1 ; GFX6-NEXT: s_max_i32 s9, s1, -1
; GFX6-NEXT: s_cselect_b32 s9, s1, -1 ; GFX6-NEXT: s_min_i32 s18, s1, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s1, -1
; GFX6-NEXT: s_cselect_b32 s18, s1, -1
; GFX6-NEXT: s_sub_i32 s18, s18, s17 ; GFX6-NEXT: s_sub_i32 s18, s18, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s18
; GFX6-NEXT: s_cselect_b32 s8, s8, s18
; GFX6-NEXT: s_sub_i32 s1, s1, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_max_i32 s9, s2, -1
; GFX6-NEXT: s_min_i32 s8, s8, s18
; GFX6-NEXT: s_sub_i32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s8, s10, 16 ; GFX6-NEXT: s_lshl_b32 s8, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s2, -1 ; GFX6-NEXT: s_min_i32 s10, s2, -1
; GFX6-NEXT: s_cselect_b32 s9, s2, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s2, -1
; GFX6-NEXT: s_cselect_b32 s10, s2, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s2, s2, s8
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s8
; GFX6-NEXT: s_min_i32 s10, s3, -1
; GFX6-NEXT: s_lshl_b32 s8, s11, 16 ; GFX6-NEXT: s_lshl_b32 s8, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s9, s3, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s10, s3, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s3, s3, s8
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s4, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s8
; GFX6-NEXT: s_min_i32 s10, s4, -1
; GFX6-NEXT: s_lshl_b32 s8, s12, 16 ; GFX6-NEXT: s_lshl_b32 s8, s12, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s9, s4, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s10, s4, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s5, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_min_i32 s10, s5, -1
; GFX6-NEXT: s_lshl_b32 s8, s13, 16 ; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s9, s5, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s10, s5, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s6, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_min_i32 s10, s6, -1
; GFX6-NEXT: s_lshl_b32 s8, s14, 16 ; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_cmp_gt_i32 s6, -1
; GFX6-NEXT: s_cselect_b32 s9, s6, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s6, -1
; GFX6-NEXT: s_cselect_b32 s10, s6, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16 ; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s7, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_min_i32 s10, s7, -1
; GFX6-NEXT: s_lshl_b32 s8, s15, 16 ; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_cmp_gt_i32 s7, -1
; GFX6-NEXT: s_cselect_b32 s9, s7, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s7, -1
; GFX6-NEXT: s_cselect_b32 s10, s7, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17 ; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8 ; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8 ; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s7, s7, s8 ; GFX6-NEXT: s_sub_i32 s7, s7, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_mov_b32 s8, 0xffff ; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: s_and_b32 s1, s1, s8 ; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s8 ; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8 ; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s8 ; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s8 ; GFX6-NEXT: s_and_b32 s3, s5, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_ashr_i32 s7, s7, 16 ; GFX6-NEXT: s_ashr_i32 s7, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2 ; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8 ; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: s_and_b32 s4, s7, s8 ; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8 ; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4 ; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v8i16: ; GFX8-LABEL: s_ssubsat_v8i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_lshr_b32 s14, s6, 16
; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_sext_i32_i16 s18, s0 ; GFX8-NEXT: s_sext_i32_i16 s18, s0
; GFX8-NEXT: s_sext_i32_i16 s19, -1 ; GFX8-NEXT: s_sext_i32_i16 s19, -1
; GFX8-NEXT: s_cmp_gt_i32 s18, s19 ; GFX8-NEXT: s_max_i32 s20, s18, s19
; GFX8-NEXT: s_movk_i32 s16, 0x7fff ; GFX8-NEXT: s_movk_i32 s16, 0x7fff
; GFX8-NEXT: s_cselect_b32 s20, s18, s19
; GFX8-NEXT: s_sub_i32 s20, s20, s16 ; GFX8-NEXT: s_sub_i32 s20, s20, s16
; GFX8-NEXT: s_cmp_lt_i32 s18, s19 ; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_movk_i32 s17, 0x8000 ; GFX8-NEXT: s_movk_i32 s17, 0x8000
; GFX8-NEXT: s_cselect_b32 s18, s18, s19 ; GFX8-NEXT: s_min_i32 s18, s18, s19
; GFX8-NEXT: s_sub_i32 s18, s18, s17
; GFX8-NEXT: s_sext_i32_i16 s20, s20 ; GFX8-NEXT: s_sext_i32_i16 s20, s20
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_gt_i32 s20, s4 ; GFX8-NEXT: s_sub_i32 s18, s18, s17
; GFX8-NEXT: s_cselect_b32 s4, s20, s4 ; GFX8-NEXT: s_max_i32 s4, s20, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s18, s18 ; GFX8-NEXT: s_sext_i32_i16 s18, s18
; GFX8-NEXT: s_cmp_lt_i32 s4, s18 ; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_cselect_b32 s4, s4, s18 ; GFX8-NEXT: s_min_i32 s4, s4, s18
; GFX8-NEXT: s_sub_i32 s0, s0, s4 ; GFX8-NEXT: s_sub_i32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s8 ; GFX8-NEXT: s_sext_i32_i16 s4, s8
; GFX8-NEXT: s_cmp_gt_i32 s4, s19 ; GFX8-NEXT: s_max_i32 s18, s4, s19
; GFX8-NEXT: s_cselect_b32 s18, s4, s19
; GFX8-NEXT: s_sub_i32 s18, s18, s16 ; GFX8-NEXT: s_sub_i32 s18, s18, s16
; GFX8-NEXT: s_cmp_lt_i32 s4, s19 ; GFX8-NEXT: s_min_i32 s4, s4, s19
; GFX8-NEXT: s_cselect_b32 s4, s4, s19
; GFX8-NEXT: s_sub_i32 s4, s4, s17
; GFX8-NEXT: s_sext_i32_i16 s18, s18 ; GFX8-NEXT: s_sext_i32_i16 s18, s18
; GFX8-NEXT: s_sext_i32_i16 s12, s12 ; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_cmp_gt_i32 s18, s12 ; GFX8-NEXT: s_sub_i32 s4, s4, s17
; GFX8-NEXT: s_cselect_b32 s12, s18, s12 ; GFX8-NEXT: s_max_i32 s12, s18, s12
; GFX8-NEXT: s_sext_i32_i16 s12, s12 ; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s4, s4 ; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_cmp_lt_i32 s12, s4 ; GFX8-NEXT: s_min_i32 s4, s12, s4
; GFX8-NEXT: s_cselect_b32 s4, s12, s4
; GFX8-NEXT: s_sub_i32 s4, s8, s4 ; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_sext_i32_i16 s8, s1 ; GFX8-NEXT: s_sext_i32_i16 s8, s1
; GFX8-NEXT: s_cmp_gt_i32 s8, s19 ; GFX8-NEXT: s_max_i32 s12, s8, s19
; GFX8-NEXT: s_cselect_b32 s12, s8, s19
; GFX8-NEXT: s_sub_i32 s12, s12, s16 ; GFX8-NEXT: s_sub_i32 s12, s12, s16
; GFX8-NEXT: s_cmp_lt_i32 s8, s19 ; GFX8-NEXT: s_min_i32 s8, s8, s19
; GFX8-NEXT: s_cselect_b32 s8, s8, s19 ; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s12, s12 ; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_gt_i32 s12, s5 ; GFX8-NEXT: s_max_i32 s5, s12, s5
; GFX8-NEXT: s_cselect_b32 s5, s12, s5 ; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_cmp_lt_i32 s5, s8 ; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_cselect_b32 s5, s5, s8 ; GFX8-NEXT: s_min_i32 s5, s5, s8
; GFX8-NEXT: s_sub_i32 s1, s1, s5 ; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s9 ; GFX8-NEXT: s_sext_i32_i16 s5, s9
; GFX8-NEXT: s_cmp_gt_i32 s5, s19 ; GFX8-NEXT: s_max_i32 s8, s5, s19
; GFX8-NEXT: s_cselect_b32 s8, s5, s19
; GFX8-NEXT: s_sub_i32 s8, s8, s16 ; GFX8-NEXT: s_sub_i32 s8, s8, s16
; GFX8-NEXT: s_cmp_lt_i32 s5, s19 ; GFX8-NEXT: s_min_i32 s5, s5, s19
; GFX8-NEXT: s_cselect_b32 s5, s5, s19
; GFX8-NEXT: s_sub_i32 s5, s5, s17
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s12, s13 ; GFX8-NEXT: s_sext_i32_i16 s12, s13
; GFX8-NEXT: s_cmp_gt_i32 s8, s12 ; GFX8-NEXT: s_sub_i32 s5, s5, s17
; GFX8-NEXT: s_cselect_b32 s8, s8, s12 ; GFX8-NEXT: s_max_i32 s8, s8, s12
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s5 ; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_cmp_lt_i32 s8, s5 ; GFX8-NEXT: s_min_i32 s5, s8, s5
; GFX8-NEXT: s_cselect_b32 s5, s8, s5
; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_sext_i32_i16 s8, s2 ; GFX8-NEXT: s_sext_i32_i16 s8, s2
; GFX8-NEXT: s_cmp_gt_i32 s8, s19 ; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_cselect_b32 s9, s8, s19 ; GFX8-NEXT: s_max_i32 s9, s8, s19
; GFX8-NEXT: s_sub_i32 s9, s9, s16 ; GFX8-NEXT: s_sub_i32 s9, s9, s16
; GFX8-NEXT: s_cmp_lt_i32 s8, s19 ; GFX8-NEXT: s_min_i32 s8, s8, s19
; GFX8-NEXT: s_cselect_b32 s8, s8, s19 ; GFX8-NEXT: s_lshr_b32 s14, s6, 16
; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_gt_i32 s9, s6 ; GFX8-NEXT: s_max_i32 s6, s9, s6
; GFX8-NEXT: s_cselect_b32 s6, s9, s6 ; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_cmp_lt_i32 s6, s8 ; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_cselect_b32 s6, s6, s8 ; GFX8-NEXT: s_min_i32 s6, s6, s8
; GFX8-NEXT: s_sub_i32 s2, s2, s6 ; GFX8-NEXT: s_sub_i32 s2, s2, s6
; GFX8-NEXT: s_sext_i32_i16 s6, s10 ; GFX8-NEXT: s_sext_i32_i16 s6, s10
; GFX8-NEXT: s_cmp_gt_i32 s6, s19 ; GFX8-NEXT: s_max_i32 s8, s6, s19
; GFX8-NEXT: s_cselect_b32 s8, s6, s19
; GFX8-NEXT: s_sub_i32 s8, s8, s16 ; GFX8-NEXT: s_sub_i32 s8, s8, s16
; GFX8-NEXT: s_cmp_lt_i32 s6, s19 ; GFX8-NEXT: s_min_i32 s6, s6, s19
; GFX8-NEXT: s_cselect_b32 s6, s6, s19
; GFX8-NEXT: s_sub_i32 s6, s6, s17
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s9, s14 ; GFX8-NEXT: s_sext_i32_i16 s9, s14
; GFX8-NEXT: s_cmp_gt_i32 s8, s9 ; GFX8-NEXT: s_sub_i32 s6, s6, s17
; GFX8-NEXT: s_cselect_b32 s8, s8, s9 ; GFX8-NEXT: s_max_i32 s8, s8, s9
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s6, s6 ; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_cmp_lt_i32 s8, s6 ; GFX8-NEXT: s_min_i32 s6, s8, s6
; GFX8-NEXT: s_cselect_b32 s6, s8, s6
; GFX8-NEXT: s_sub_i32 s6, s10, s6
; GFX8-NEXT: s_sext_i32_i16 s8, s3 ; GFX8-NEXT: s_sext_i32_i16 s8, s3
; GFX8-NEXT: s_cmp_gt_i32 s8, s19 ; GFX8-NEXT: s_max_i32 s9, s8, s19
; GFX8-NEXT: s_cselect_b32 s9, s8, s19
; GFX8-NEXT: s_sub_i32 s9, s9, s16 ; GFX8-NEXT: s_sub_i32 s9, s9, s16
; GFX8-NEXT: s_cmp_lt_i32 s8, s19 ; GFX8-NEXT: s_min_i32 s8, s8, s19
; GFX8-NEXT: s_cselect_b32 s8, s8, s19 ; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s9, s9 ; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s7, s7 ; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_cmp_gt_i32 s9, s7 ; GFX8-NEXT: s_max_i32 s7, s9, s7
; GFX8-NEXT: s_cselect_b32 s7, s9, s7 ; GFX8-NEXT: s_sub_i32 s8, s8, s17
; GFX8-NEXT: s_sext_i32_i16 s7, s7 ; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_cmp_lt_i32 s7, s8 ; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_cselect_b32 s7, s7, s8 ; GFX8-NEXT: s_min_i32 s7, s7, s8
; GFX8-NEXT: s_sub_i32 s3, s3, s7 ; GFX8-NEXT: s_sub_i32 s3, s3, s7
; GFX8-NEXT: s_sext_i32_i16 s7, s11 ; GFX8-NEXT: s_sext_i32_i16 s7, s11
; GFX8-NEXT: s_cmp_gt_i32 s7, s19 ; GFX8-NEXT: s_max_i32 s8, s7, s19
; GFX8-NEXT: s_cselect_b32 s8, s7, s19
; GFX8-NEXT: s_sub_i32 s8, s8, s16 ; GFX8-NEXT: s_sub_i32 s8, s8, s16
; GFX8-NEXT: s_cmp_lt_i32 s7, s19 ; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_cselect_b32 s7, s7, s19 ; GFX8-NEXT: s_min_i32 s7, s7, s19
; GFX8-NEXT: s_sub_i32 s7, s7, s17
; GFX8-NEXT: s_sext_i32_i16 s8, s8 ; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s9, s15 ; GFX8-NEXT: s_sext_i32_i16 s9, s15
; GFX8-NEXT: s_cmp_gt_i32 s8, s9
; GFX8-NEXT: s_cselect_b32 s8, s8, s9
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_cmp_lt_i32 s8, s7
; GFX8-NEXT: s_cselect_b32 s7, s8, s7
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 ; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_sub_i32 s7, s7, s17
; GFX8-NEXT: s_max_i32 s8, s8, s9
; GFX8-NEXT: s_or_b32 s0, s0, s4 ; GFX8-NEXT: s_or_b32 s0, s0, s4
; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX8-NEXT: s_sub_i32 s6, s10, s6
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 ; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_min_i32 s7, s8, s7
; GFX8-NEXT: s_or_b32 s1, s1, s4 ; GFX8-NEXT: s_or_b32 s1, s1, s4
; GFX8-NEXT: s_bfe_u32 s4, s6, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, s6, 0x100000
; GFX8-NEXT: s_sub_i32 s7, s11, s7 ; GFX8-NEXT: s_sub_i32 s7, s11, s7
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16 ; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_or_b32 s2, s2, s4 ; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 ; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
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llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

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} }
define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) { define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i7: ; GFX6-LABEL: s_uaddsat_i7:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25 ; GFX6-NEXT: s_lshl_b32 s0, s0, 25
; GFX6-NEXT: s_lshl_b32 s1, s1, 25 ; GFX6-NEXT: s_lshl_b32 s1, s1, 25
; GFX6-NEXT: s_not_b32 s2, s0 ; GFX6-NEXT: s_not_b32 s2, s0
; GFX6-NEXT: s_cmp_lt_u32 s2, s1 ; GFX6-NEXT: s_min_u32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 25 ; GFX6-NEXT: s_lshr_b32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i7: ; GFX8-LABEL: s_uaddsat_i7:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
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} }
define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) { define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i8: ; GFX6-LABEL: s_uaddsat_i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_not_b32 s2, s0 ; GFX6-NEXT: s_not_b32 s2, s0
; GFX6-NEXT: s_cmp_lt_u32 s2, s1 ; GFX6-NEXT: s_min_u32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 24 ; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i8: ; GFX8-LABEL: s_uaddsat_i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
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define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_uaddsat_v2i8: ; GFX6-LABEL: s_uaddsat_v2i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshr_b32 s3, s1, 8 ; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_not_b32 s4, s0 ; GFX6-NEXT: s_not_b32 s4, s0
; GFX6-NEXT: s_cmp_lt_u32 s4, s1 ; GFX6-NEXT: s_min_u32 s1, s4, s1
; GFX6-NEXT: s_cselect_b32 s1, s4, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_not_b32 s3, s1 ; GFX6-NEXT: s_not_b32 s3, s1
; GFX6-NEXT: s_cmp_lt_u32 s3, s2 ; GFX6-NEXT: s_min_u32 s2, s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 24 ; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v2i8: ; GFX8-LABEL: s_uaddsat_v2i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s3, s1, 8 ; GFX8-NEXT: s_lshr_b32 s3, s1, 8
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; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24 ; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8 ; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16 ; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24 ; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_not_b32 s8, s0 ; GFX6-NEXT: s_not_b32 s8, s0
; GFX6-NEXT: s_cmp_lt_u32 s8, s1 ; GFX6-NEXT: s_min_u32 s1, s8, s1
; GFX6-NEXT: s_cselect_b32 s1, s8, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshl_b32 s2, s5, 24 ; GFX6-NEXT: s_lshl_b32 s2, s5, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_not_b32 s5, s1 ; GFX6-NEXT: s_not_b32 s5, s1
; GFX6-NEXT: s_cmp_lt_u32 s5, s2 ; GFX6-NEXT: s_min_u32 s2, s5, s2
; GFX6-NEXT: s_cselect_b32 s2, s5, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshl_b32 s3, s6, 24 ; GFX6-NEXT: s_lshl_b32 s3, s6, 24
; GFX6-NEXT: s_not_b32 s5, s2 ; GFX6-NEXT: s_not_b32 s5, s2
; GFX6-NEXT: s_cmp_lt_u32 s5, s3 ; GFX6-NEXT: s_min_u32 s3, s5, s3
; GFX6-NEXT: s_cselect_b32 s3, s5, s3
; GFX6-NEXT: s_add_i32 s2, s2, s3 ; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24 ; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24 ; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_not_b32 s5, s3 ; GFX6-NEXT: s_not_b32 s5, s3
; GFX6-NEXT: s_cmp_lt_u32 s5, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_cselect_b32 s4, s5, s4 ; GFX6-NEXT: s_min_u32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 16 ; GFX6-NEXT: s_lshl_b32 s1, s2, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 24 ; GFX6-NEXT: s_lshr_b32 s3, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s3, 24 ; GFX6-NEXT: s_lshl_b32 s1, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
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} }
define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) { define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i24: ; GFX6-LABEL: s_uaddsat_i24:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8 ; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_not_b32 s2, s0 ; GFX6-NEXT: s_not_b32 s2, s0
; GFX6-NEXT: s_cmp_lt_u32 s2, s1 ; GFX6-NEXT: s_min_u32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 8 ; GFX6-NEXT: s_lshr_b32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i24: ; GFX8-LABEL: s_uaddsat_i24:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b32 s1, s1, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 8 ; GFX8-NEXT: s_lshl_b32 s0, s0, 8
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%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result ret i32 %result
} }
define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) { define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i32: ; GFX6-LABEL: s_uaddsat_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s2, s0 ; GFX6-NEXT: s_not_b32 s2, s0
; GFX6-NEXT: s_cmp_lt_u32 s2, s1 ; GFX6-NEXT: s_min_u32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i32: ; GFX8-LABEL: s_uaddsat_i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp ; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
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%result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result ret <2 x i32> %result
} }
define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) { define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v2i32: ; GFX6-LABEL: s_uaddsat_v2i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s4, s0 ; GFX6-NEXT: s_not_b32 s4, s0
; GFX6-NEXT: s_cmp_lt_u32 s4, s2 ; GFX6-NEXT: s_min_u32 s2, s4, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2
; GFX6-NEXT: s_add_i32 s0, s0, s2 ; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s1 ; GFX6-NEXT: s_not_b32 s2, s1
; GFX6-NEXT: s_cmp_lt_u32 s2, s3 ; GFX6-NEXT: s_min_u32 s2, s2, s3
; GFX6-NEXT: s_cselect_b32 s2, s2, s3
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v2i32: ; GFX8-LABEL: s_uaddsat_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], s0, v0 clamp ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], s0, v0 clamp
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%result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result ret <3 x i32> %result
} }
define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) { define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v3i32: ; GFX6-LABEL: s_uaddsat_v3i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s6, s0 ; GFX6-NEXT: s_not_b32 s6, s0
; GFX6-NEXT: s_cmp_lt_u32 s6, s3 ; GFX6-NEXT: s_min_u32 s3, s6, s3
; GFX6-NEXT: s_cselect_b32 s3, s6, s3
; GFX6-NEXT: s_add_i32 s0, s0, s3 ; GFX6-NEXT: s_add_i32 s0, s0, s3
; GFX6-NEXT: s_not_b32 s3, s1 ; GFX6-NEXT: s_not_b32 s3, s1
; GFX6-NEXT: s_cmp_lt_u32 s3, s4 ; GFX6-NEXT: s_min_u32 s3, s3, s4
; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_add_i32 s1, s1, s3 ; GFX6-NEXT: s_add_i32 s1, s1, s3
; GFX6-NEXT: s_not_b32 s3, s2 ; GFX6-NEXT: s_not_b32 s3, s2
; GFX6-NEXT: s_cmp_lt_u32 s3, s5 ; GFX6-NEXT: s_min_u32 s3, s3, s5
; GFX6-NEXT: s_cselect_b32 s3, s3, s5
; GFX6-NEXT: s_add_i32 s2, s2, s3 ; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v3i32: ; GFX8-LABEL: s_uaddsat_v3i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s3 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result ret <4 x i32> %result
} }
define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) { define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v4i32: ; GFX6-LABEL: s_uaddsat_v4i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s8, s0 ; GFX6-NEXT: s_not_b32 s8, s0
; GFX6-NEXT: s_cmp_lt_u32 s8, s4 ; GFX6-NEXT: s_min_u32 s4, s8, s4
; GFX6-NEXT: s_cselect_b32 s4, s8, s4
; GFX6-NEXT: s_add_i32 s0, s0, s4 ; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_not_b32 s4, s1 ; GFX6-NEXT: s_not_b32 s4, s1
; GFX6-NEXT: s_cmp_lt_u32 s4, s5 ; GFX6-NEXT: s_min_u32 s4, s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s1, s1, s4 ; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_not_b32 s4, s2 ; GFX6-NEXT: s_not_b32 s4, s2
; GFX6-NEXT: s_cmp_lt_u32 s4, s6 ; GFX6-NEXT: s_min_u32 s4, s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_add_i32 s2, s2, s4 ; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_not_b32 s4, s3 ; GFX6-NEXT: s_not_b32 s4, s3
; GFX6-NEXT: s_cmp_lt_u32 s4, s7 ; GFX6-NEXT: s_min_u32 s4, s4, s7
; GFX6-NEXT: s_cselect_b32 s4, s4, s7
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v4i32: ; GFX8-LABEL: s_uaddsat_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) { define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v5i32: ; GFX6-LABEL: s_uaddsat_v5i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s10, s0 ; GFX6-NEXT: s_not_b32 s10, s0
; GFX6-NEXT: s_cmp_lt_u32 s10, s5 ; GFX6-NEXT: s_min_u32 s5, s10, s5
; GFX6-NEXT: s_cselect_b32 s5, s10, s5
; GFX6-NEXT: s_add_i32 s0, s0, s5 ; GFX6-NEXT: s_add_i32 s0, s0, s5
; GFX6-NEXT: s_not_b32 s5, s1 ; GFX6-NEXT: s_not_b32 s5, s1
; GFX6-NEXT: s_cmp_lt_u32 s5, s6 ; GFX6-NEXT: s_min_u32 s5, s5, s6
; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_add_i32 s1, s1, s5 ; GFX6-NEXT: s_add_i32 s1, s1, s5
; GFX6-NEXT: s_not_b32 s5, s2 ; GFX6-NEXT: s_not_b32 s5, s2
; GFX6-NEXT: s_cmp_lt_u32 s5, s7 ; GFX6-NEXT: s_min_u32 s5, s5, s7
; GFX6-NEXT: s_cselect_b32 s5, s5, s7
; GFX6-NEXT: s_add_i32 s2, s2, s5 ; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: s_not_b32 s5, s3 ; GFX6-NEXT: s_not_b32 s5, s3
; GFX6-NEXT: s_cmp_lt_u32 s5, s8 ; GFX6-NEXT: s_min_u32 s5, s5, s8
; GFX6-NEXT: s_cselect_b32 s5, s5, s8
; GFX6-NEXT: s_add_i32 s3, s3, s5 ; GFX6-NEXT: s_add_i32 s3, s3, s5
; GFX6-NEXT: s_not_b32 s5, s4 ; GFX6-NEXT: s_not_b32 s5, s4
; GFX6-NEXT: s_cmp_lt_u32 s5, s9 ; GFX6-NEXT: s_min_u32 s5, s5, s9
; GFX6-NEXT: s_cselect_b32 s5, s5, s9
; GFX6-NEXT: s_add_i32 s4, s4, s5 ; GFX6-NEXT: s_add_i32 s4, s4, s5
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v5i32: ; GFX8-LABEL: s_uaddsat_v5i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s5 ; GFX8-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s7 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v16i32: ; GFX6-LABEL: s_uaddsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_not_b32 s32, s0 ; GFX6-NEXT: s_not_b32 s32, s0
; GFX6-NEXT: s_cmp_lt_u32 s32, s16 ; GFX6-NEXT: s_min_u32 s16, s32, s16
; GFX6-NEXT: s_cselect_b32 s16, s32, s16
; GFX6-NEXT: s_add_i32 s0, s0, s16 ; GFX6-NEXT: s_add_i32 s0, s0, s16
; GFX6-NEXT: s_not_b32 s16, s1 ; GFX6-NEXT: s_not_b32 s16, s1
; GFX6-NEXT: s_cmp_lt_u32 s16, s17 ; GFX6-NEXT: s_min_u32 s16, s16, s17
; GFX6-NEXT: s_cselect_b32 s16, s16, s17
; GFX6-NEXT: s_add_i32 s1, s1, s16 ; GFX6-NEXT: s_add_i32 s1, s1, s16
; GFX6-NEXT: s_not_b32 s16, s2 ; GFX6-NEXT: s_not_b32 s16, s2
; GFX6-NEXT: s_cmp_lt_u32 s16, s18 ; GFX6-NEXT: s_min_u32 s16, s16, s18
; GFX6-NEXT: s_cselect_b32 s16, s16, s18
; GFX6-NEXT: s_add_i32 s2, s2, s16 ; GFX6-NEXT: s_add_i32 s2, s2, s16
; GFX6-NEXT: s_not_b32 s16, s3 ; GFX6-NEXT: s_not_b32 s16, s3
; GFX6-NEXT: s_cmp_lt_u32 s16, s19 ; GFX6-NEXT: s_min_u32 s16, s16, s19
; GFX6-NEXT: s_cselect_b32 s16, s16, s19
; GFX6-NEXT: s_add_i32 s3, s3, s16 ; GFX6-NEXT: s_add_i32 s3, s3, s16
; GFX6-NEXT: s_not_b32 s16, s4 ; GFX6-NEXT: s_not_b32 s16, s4
; GFX6-NEXT: s_cmp_lt_u32 s16, s20 ; GFX6-NEXT: s_min_u32 s16, s16, s20
; GFX6-NEXT: s_cselect_b32 s16, s16, s20
; GFX6-NEXT: s_add_i32 s4, s4, s16 ; GFX6-NEXT: s_add_i32 s4, s4, s16
; GFX6-NEXT: s_not_b32 s16, s5 ; GFX6-NEXT: s_not_b32 s16, s5
; GFX6-NEXT: s_cmp_lt_u32 s16, s21 ; GFX6-NEXT: s_min_u32 s16, s16, s21
; GFX6-NEXT: s_cselect_b32 s16, s16, s21
; GFX6-NEXT: s_add_i32 s5, s5, s16 ; GFX6-NEXT: s_add_i32 s5, s5, s16
; GFX6-NEXT: s_not_b32 s16, s6 ; GFX6-NEXT: s_not_b32 s16, s6
; GFX6-NEXT: s_cmp_lt_u32 s16, s22 ; GFX6-NEXT: s_min_u32 s16, s16, s22
; GFX6-NEXT: s_cselect_b32 s16, s16, s22
; GFX6-NEXT: s_add_i32 s6, s6, s16 ; GFX6-NEXT: s_add_i32 s6, s6, s16
; GFX6-NEXT: s_not_b32 s16, s7 ; GFX6-NEXT: s_not_b32 s16, s7
; GFX6-NEXT: s_cmp_lt_u32 s16, s23 ; GFX6-NEXT: s_min_u32 s16, s16, s23
; GFX6-NEXT: s_cselect_b32 s16, s16, s23
; GFX6-NEXT: s_add_i32 s7, s7, s16 ; GFX6-NEXT: s_add_i32 s7, s7, s16
; GFX6-NEXT: s_not_b32 s16, s8 ; GFX6-NEXT: s_not_b32 s16, s8
; GFX6-NEXT: s_cmp_lt_u32 s16, s24 ; GFX6-NEXT: s_min_u32 s16, s16, s24
; GFX6-NEXT: s_cselect_b32 s16, s16, s24
; GFX6-NEXT: s_add_i32 s8, s8, s16 ; GFX6-NEXT: s_add_i32 s8, s8, s16
; GFX6-NEXT: s_not_b32 s16, s9 ; GFX6-NEXT: s_not_b32 s16, s9
; GFX6-NEXT: s_cmp_lt_u32 s16, s25 ; GFX6-NEXT: s_min_u32 s16, s16, s25
; GFX6-NEXT: s_cselect_b32 s16, s16, s25
; GFX6-NEXT: s_add_i32 s9, s9, s16 ; GFX6-NEXT: s_add_i32 s9, s9, s16
; GFX6-NEXT: s_not_b32 s16, s10 ; GFX6-NEXT: s_not_b32 s16, s10
; GFX6-NEXT: s_cmp_lt_u32 s16, s26 ; GFX6-NEXT: s_min_u32 s16, s16, s26
; GFX6-NEXT: s_cselect_b32 s16, s16, s26
; GFX6-NEXT: s_add_i32 s10, s10, s16 ; GFX6-NEXT: s_add_i32 s10, s10, s16
; GFX6-NEXT: s_not_b32 s16, s11 ; GFX6-NEXT: s_not_b32 s16, s11
; GFX6-NEXT: s_cmp_lt_u32 s16, s27 ; GFX6-NEXT: s_min_u32 s16, s16, s27
; GFX6-NEXT: s_cselect_b32 s16, s16, s27
; GFX6-NEXT: s_add_i32 s11, s11, s16 ; GFX6-NEXT: s_add_i32 s11, s11, s16
; GFX6-NEXT: s_not_b32 s16, s12 ; GFX6-NEXT: s_not_b32 s16, s12
; GFX6-NEXT: s_cmp_lt_u32 s16, s28 ; GFX6-NEXT: s_min_u32 s16, s16, s28
; GFX6-NEXT: s_cselect_b32 s16, s16, s28
; GFX6-NEXT: s_add_i32 s12, s12, s16 ; GFX6-NEXT: s_add_i32 s12, s12, s16
; GFX6-NEXT: s_not_b32 s16, s13 ; GFX6-NEXT: s_not_b32 s16, s13
; GFX6-NEXT: s_cmp_lt_u32 s16, s29 ; GFX6-NEXT: s_min_u32 s16, s16, s29
; GFX6-NEXT: s_cselect_b32 s16, s16, s29
; GFX6-NEXT: s_add_i32 s13, s13, s16 ; GFX6-NEXT: s_add_i32 s13, s13, s16
; GFX6-NEXT: s_not_b32 s16, s14 ; GFX6-NEXT: s_not_b32 s16, s14
; GFX6-NEXT: s_cmp_lt_u32 s16, s30 ; GFX6-NEXT: s_min_u32 s16, s16, s30
; GFX6-NEXT: s_cselect_b32 s16, s16, s30
; GFX6-NEXT: s_add_i32 s14, s14, s16 ; GFX6-NEXT: s_add_i32 s14, s14, s16
; GFX6-NEXT: s_not_b32 s16, s15 ; GFX6-NEXT: s_not_b32 s16, s15
; GFX6-NEXT: s_cmp_lt_u32 s16, s31 ; GFX6-NEXT: s_min_u32 s16, s16, s31
; GFX6-NEXT: s_cselect_b32 s16, s16, s31
; GFX6-NEXT: s_add_i32 s15, s15, s16 ; GFX6-NEXT: s_add_i32 s15, s15, s16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v16i32: ; GFX8-LABEL: s_uaddsat_v16i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s16 ; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: v_mov_b32_e32 v1, s17 ; GFX8-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NEXT: v_mov_b32_e32 v2, s18 ; GFX8-NEXT: v_mov_b32_e32 v2, s18
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} }
define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i16: ; GFX6-LABEL: s_uaddsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_not_b32 s2, s0 ; GFX6-NEXT: s_not_b32 s2, s0
; GFX6-NEXT: s_cmp_lt_u32 s2, s1 ; GFX6-NEXT: s_min_u32 s1, s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1 ; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i16: ; GFX8-LABEL: s_uaddsat_i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp ; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
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} }
define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) { define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v2i16: ; GFX6-LABEL: s_uaddsat_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_not_b32 s4, s0 ; GFX6-NEXT: s_not_b32 s4, s0
; GFX6-NEXT: s_cmp_lt_u32 s4, s2 ; GFX6-NEXT: s_min_u32 s2, s4, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2
; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 16 ; GFX6-NEXT: s_lshl_b32 s2, s3, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_not_b32 s3, s1 ; GFX6-NEXT: s_not_b32 s3, s1
; GFX6-NEXT: s_cmp_lt_u32 s3, s2 ; GFX6-NEXT: s_min_u32 s2, s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v2i16: ; GFX8-LABEL: s_uaddsat_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16 ; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16
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} }
define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) { define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v4i16: ; GFX6-LABEL: s_uaddsat_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_not_b32 s8, s0 ; GFX6-NEXT: s_not_b32 s8, s0
; GFX6-NEXT: s_cmp_lt_u32 s8, s4 ; GFX6-NEXT: s_min_u32 s4, s8, s4
; GFX6-NEXT: s_cselect_b32 s4, s8, s4
; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s4, s5, 16 ; GFX6-NEXT: s_lshl_b32 s4, s5, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_not_b32 s5, s1 ; GFX6-NEXT: s_not_b32 s5, s1
; GFX6-NEXT: s_cmp_lt_u32 s5, s4 ; GFX6-NEXT: s_min_u32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s4, s6, 16 ; GFX6-NEXT: s_lshl_b32 s4, s6, 16
; GFX6-NEXT: s_not_b32 s5, s2 ; GFX6-NEXT: s_not_b32 s5, s2
; GFX6-NEXT: s_cmp_lt_u32 s5, s4 ; GFX6-NEXT: s_min_u32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_lshl_b32 s4, s7, 16 ; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_not_b32 s5, s3 ; GFX6-NEXT: s_not_b32 s5, s3
; GFX6-NEXT: s_cmp_lt_u32 s5, s4 ; GFX6-NEXT: s_min_u32 s4, s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s3, s3, s4 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16 ; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v4i16: ; GFX8-LABEL: s_uaddsat_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16 ; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16 ; GFX8-NEXT: s_lshr_b32 s7, s3, 16
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} }
define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) { define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v6i16: ; GFX6-LABEL: s_uaddsat_v6i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_not_b32 s12, s0 ; GFX6-NEXT: s_not_b32 s12, s0
; GFX6-NEXT: s_cmp_lt_u32 s12, s6 ; GFX6-NEXT: s_min_u32 s6, s12, s6
; GFX6-NEXT: s_cselect_b32 s6, s12, s6
; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s6, s7, 16 ; GFX6-NEXT: s_lshl_b32 s6, s7, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_not_b32 s7, s1 ; GFX6-NEXT: s_not_b32 s7, s1
; GFX6-NEXT: s_cmp_lt_u32 s7, s6 ; GFX6-NEXT: s_min_u32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s1, s1, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_add_i32 s1, s1, s6
; GFX6-NEXT: s_lshl_b32 s6, s8, 16 ; GFX6-NEXT: s_lshl_b32 s6, s8, 16
; GFX6-NEXT: s_not_b32 s7, s2 ; GFX6-NEXT: s_not_b32 s7, s2
; GFX6-NEXT: s_cmp_lt_u32 s7, s6 ; GFX6-NEXT: s_min_u32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s2, s2, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_add_i32 s2, s2, s6
; GFX6-NEXT: s_lshl_b32 s6, s9, 16 ; GFX6-NEXT: s_lshl_b32 s6, s9, 16
; GFX6-NEXT: s_not_b32 s7, s3 ; GFX6-NEXT: s_not_b32 s7, s3
; GFX6-NEXT: s_cmp_lt_u32 s7, s6 ; GFX6-NEXT: s_min_u32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16 ; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_lshl_b32 s6, s10, 16 ; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_not_b32 s7, s4 ; GFX6-NEXT: s_not_b32 s7, s4
; GFX6-NEXT: s_cmp_lt_u32 s7, s6 ; GFX6-NEXT: s_min_u32 s6, s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshr_b32 s4, s4, 16 ; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_lshl_b32 s6, s11, 16 ; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_not_b32 s7, s5 ; GFX6-NEXT: s_not_b32 s7, s5
; GFX6-NEXT: s_cmp_lt_u32 s7, s6 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_cselect_b32 s6, s7, s6 ; GFX6-NEXT: s_min_u32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s5, s5, s6 ; GFX6-NEXT: s_add_i32 s5, s5, s6
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16 ; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s2, s5, 16 ; GFX6-NEXT: s_lshl_b32 s2, s5, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2 ; GFX6-NEXT: s_or_b32 s2, s4, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v6i16: ; GFX8-LABEL: s_uaddsat_v6i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16 ; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16 ; GFX8-NEXT: s_lshr_b32 s10, s4, 16
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} }
define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) { define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v8i16: ; GFX6-LABEL: s_uaddsat_v8i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s8, s8, 16 ; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_not_b32 s16, s0 ; GFX6-NEXT: s_not_b32 s16, s0
; GFX6-NEXT: s_cmp_lt_u32 s16, s8 ; GFX6-NEXT: s_min_u32 s8, s16, s8
; GFX6-NEXT: s_cselect_b32 s8, s16, s8
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s8, s9, 16 ; GFX6-NEXT: s_lshl_b32 s8, s9, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_not_b32 s9, s1 ; GFX6-NEXT: s_not_b32 s9, s1
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_add_i32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s8, s10, 16 ; GFX6-NEXT: s_lshl_b32 s8, s10, 16
; GFX6-NEXT: s_not_b32 s9, s2 ; GFX6-NEXT: s_not_b32 s9, s2
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshr_b32 s2, s2, 16 ; GFX6-NEXT: s_add_i32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s8, s11, 16 ; GFX6-NEXT: s_lshl_b32 s8, s11, 16
; GFX6-NEXT: s_not_b32 s9, s3 ; GFX6-NEXT: s_not_b32 s9, s3
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16 ; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_lshl_b32 s8, s12, 16 ; GFX6-NEXT: s_lshl_b32 s8, s12, 16
; GFX6-NEXT: s_not_b32 s9, s4 ; GFX6-NEXT: s_not_b32 s9, s4
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshr_b32 s4, s4, 16 ; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_lshl_b32 s8, s13, 16 ; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_not_b32 s9, s5 ; GFX6-NEXT: s_not_b32 s9, s5
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16 ; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_lshl_b32 s8, s14, 16 ; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_not_b32 s9, s6 ; GFX6-NEXT: s_not_b32 s9, s6
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_lshl_b32 s7, s7, 16 ; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshr_b32 s6, s6, 16 ; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_lshl_b32 s8, s15, 16 ; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_not_b32 s9, s7 ; GFX6-NEXT: s_not_b32 s9, s7
; GFX6-NEXT: s_cmp_lt_u32 s9, s8 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_cselect_b32 s8, s9, s8 ; GFX6-NEXT: s_min_u32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s7, s7, s8 ; GFX6-NEXT: s_add_i32 s7, s7, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16 ; GFX6-NEXT: s_lshr_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s3, s7, 16 ; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s2, s5, 16 ; GFX6-NEXT: s_lshl_b32 s2, s5, 16
; GFX6-NEXT: s_lshr_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s3, s7, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2 ; GFX6-NEXT: s_or_b32 s2, s4, s2
; GFX6-NEXT: s_or_b32 s3, s6, s3 ; GFX6-NEXT: s_or_b32 s3, s6, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_v8i16: ; GFX8-LABEL: s_uaddsat_v8i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16 ; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16 ; GFX8-NEXT: s_lshr_b32 s13, s5, 16
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llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i7 %result ret i7 %result
} }
define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) { define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i7: ; GFX6-LABEL: s_usubsat_i7:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25 ; GFX6-NEXT: s_lshl_b32 s0, s0, 25
; GFX6-NEXT: s_lshl_b32 s1, s1, 25 ; GFX6-NEXT: s_lshl_b32 s1, s1, 25
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 25 ; GFX6-NEXT: s_lshr_b32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i7: ; GFX8-LABEL: s_usubsat_i7:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i8 %result ret i8 %result
} }
define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) { define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i8: ; GFX6-LABEL: s_usubsat_i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 24 ; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i8: ; GFX8-LABEL: s_usubsat_i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2
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define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_usubsat_v2i8: ; GFX6-LABEL: s_usubsat_v2i8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8 ; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_cmp_lt_u32 s1, s2 ; GFX6-NEXT: s_min_u32 s2, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 24 ; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v2i8: ; GFX8-LABEL: s_usubsat_v2i8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000 ; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s3, s1, 8 ; GFX8-NEXT: s_lshr_b32 s3, s1, 8
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; GFX6-NEXT: s_lshr_b32 s2, s0, 8 ; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24 ; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8 ; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16 ; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24 ; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24 ; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24 ; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s2, s5, 24 ; GFX6-NEXT: s_lshl_b32 s2, s5, 24
; GFX6-NEXT: s_cmp_lt_u32 s1, s2 ; GFX6-NEXT: s_min_u32 s2, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24 ; GFX6-NEXT: s_lshl_b32 s2, s3, 24
; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_lshl_b32 s3, s6, 24 ; GFX6-NEXT: s_lshl_b32 s3, s6, 24
; GFX6-NEXT: s_cmp_lt_u32 s2, s3 ; GFX6-NEXT: s_min_u32 s3, s2, s3
; GFX6-NEXT: s_cselect_b32 s3, s2, s3
; GFX6-NEXT: s_sub_i32 s2, s2, s3 ; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24 ; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24 ; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_cmp_lt_u32 s3, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, 24
; GFX6-NEXT: s_cselect_b32 s4, s3, s4 ; GFX6-NEXT: s_min_u32 s4, s3, s4
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_lshr_b32 s2, s2, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 16 ; GFX6-NEXT: s_lshl_b32 s1, s2, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 24 ; GFX6-NEXT: s_lshr_b32 s3, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s3, 24 ; GFX6-NEXT: s_lshl_b32 s1, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i24 %result ret i24 %result
} }
define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) { define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i24: ; GFX6-LABEL: s_usubsat_i24:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8 ; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 8 ; GFX6-NEXT: s_lshr_b32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i24: ; GFX8-LABEL: s_usubsat_i24:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b32 s1, s1, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 8 ; GFX8-NEXT: s_lshl_b32 s0, s0, 8
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result ret i32 %result
} }
define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) { define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i32: ; GFX6-LABEL: s_usubsat_i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i32: ; GFX8-LABEL: s_usubsat_i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp ; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result ret <2 x i32> %result
} }
define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) { define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v2i32: ; GFX6-LABEL: s_usubsat_v2i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s2 ; GFX6-NEXT: s_min_u32 s2, s0, s2
; GFX6-NEXT: s_cselect_b32 s2, s0, s2
; GFX6-NEXT: s_sub_i32 s0, s0, s2 ; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s1, s3 ; GFX6-NEXT: s_min_u32 s2, s1, s3
; GFX6-NEXT: s_cselect_b32 s2, s1, s3
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v2i32: ; GFX8-LABEL: s_usubsat_v2i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp ; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp
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; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result ret <3 x i32> %result
} }
define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) { define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v3i32: ; GFX6-LABEL: s_usubsat_v3i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s3 ; GFX6-NEXT: s_min_u32 s3, s0, s3
; GFX6-NEXT: s_cselect_b32 s3, s0, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s3 ; GFX6-NEXT: s_sub_i32 s0, s0, s3
; GFX6-NEXT: s_cmp_lt_u32 s1, s4 ; GFX6-NEXT: s_min_u32 s3, s1, s4
; GFX6-NEXT: s_cselect_b32 s3, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s3 ; GFX6-NEXT: s_sub_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_lt_u32 s2, s5 ; GFX6-NEXT: s_min_u32 s3, s2, s5
; GFX6-NEXT: s_cselect_b32 s3, s2, s5
; GFX6-NEXT: s_sub_i32 s2, s2, s3 ; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v3i32: ; GFX8-LABEL: s_usubsat_v3i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s3 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result ret <4 x i32> %result
} }
define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) { define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v4i32: ; GFX6-LABEL: s_usubsat_v4i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s4 ; GFX6-NEXT: s_min_u32 s4, s0, s4
; GFX6-NEXT: s_cselect_b32 s4, s0, s4
; GFX6-NEXT: s_sub_i32 s0, s0, s4 ; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_cmp_lt_u32 s1, s5 ; GFX6-NEXT: s_min_u32 s4, s1, s5
; GFX6-NEXT: s_cselect_b32 s4, s1, s5
; GFX6-NEXT: s_sub_i32 s1, s1, s4 ; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_u32 s2, s6 ; GFX6-NEXT: s_min_u32 s4, s2, s6
; GFX6-NEXT: s_cselect_b32 s4, s2, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s4 ; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_u32 s3, s7 ; GFX6-NEXT: s_min_u32 s4, s3, s7
; GFX6-NEXT: s_cselect_b32 s4, s3, s7
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v4i32: ; GFX8-LABEL: s_usubsat_v4i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result ret <5 x i32> %result
} }
define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) { define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v5i32: ; GFX6-LABEL: s_usubsat_v5i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s5 ; GFX6-NEXT: s_min_u32 s5, s0, s5
; GFX6-NEXT: s_cselect_b32 s5, s0, s5
; GFX6-NEXT: s_sub_i32 s0, s0, s5 ; GFX6-NEXT: s_sub_i32 s0, s0, s5
; GFX6-NEXT: s_cmp_lt_u32 s1, s6 ; GFX6-NEXT: s_min_u32 s5, s1, s6
; GFX6-NEXT: s_cselect_b32 s5, s1, s6
; GFX6-NEXT: s_sub_i32 s1, s1, s5 ; GFX6-NEXT: s_sub_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_lt_u32 s2, s7 ; GFX6-NEXT: s_min_u32 s5, s2, s7
; GFX6-NEXT: s_cselect_b32 s5, s2, s7
; GFX6-NEXT: s_sub_i32 s2, s2, s5 ; GFX6-NEXT: s_sub_i32 s2, s2, s5
; GFX6-NEXT: s_cmp_lt_u32 s3, s8 ; GFX6-NEXT: s_min_u32 s5, s3, s8
; GFX6-NEXT: s_cselect_b32 s5, s3, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s5 ; GFX6-NEXT: s_sub_i32 s3, s3, s5
; GFX6-NEXT: s_cmp_lt_u32 s4, s9 ; GFX6-NEXT: s_min_u32 s5, s4, s9
; GFX6-NEXT: s_cselect_b32 s5, s4, s9
; GFX6-NEXT: s_sub_i32 s4, s4, s5 ; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v5i32: ; GFX8-LABEL: s_usubsat_v5i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s5 ; GFX8-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s7 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result ret <16 x i32> %result
} }
define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) { define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v16i32: ; GFX6-LABEL: s_usubsat_v16i32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s16 ; GFX6-NEXT: s_min_u32 s16, s0, s16
; GFX6-NEXT: s_cselect_b32 s16, s0, s16
; GFX6-NEXT: s_sub_i32 s0, s0, s16 ; GFX6-NEXT: s_sub_i32 s0, s0, s16
; GFX6-NEXT: s_cmp_lt_u32 s1, s17 ; GFX6-NEXT: s_min_u32 s16, s1, s17
; GFX6-NEXT: s_cselect_b32 s16, s1, s17
; GFX6-NEXT: s_sub_i32 s1, s1, s16 ; GFX6-NEXT: s_sub_i32 s1, s1, s16
; GFX6-NEXT: s_cmp_lt_u32 s2, s18 ; GFX6-NEXT: s_min_u32 s16, s2, s18
; GFX6-NEXT: s_cselect_b32 s16, s2, s18
; GFX6-NEXT: s_sub_i32 s2, s2, s16 ; GFX6-NEXT: s_sub_i32 s2, s2, s16
; GFX6-NEXT: s_cmp_lt_u32 s3, s19 ; GFX6-NEXT: s_min_u32 s16, s3, s19
; GFX6-NEXT: s_cselect_b32 s16, s3, s19
; GFX6-NEXT: s_sub_i32 s3, s3, s16 ; GFX6-NEXT: s_sub_i32 s3, s3, s16
; GFX6-NEXT: s_cmp_lt_u32 s4, s20 ; GFX6-NEXT: s_min_u32 s16, s4, s20
; GFX6-NEXT: s_cselect_b32 s16, s4, s20
; GFX6-NEXT: s_sub_i32 s4, s4, s16 ; GFX6-NEXT: s_sub_i32 s4, s4, s16
; GFX6-NEXT: s_cmp_lt_u32 s5, s21 ; GFX6-NEXT: s_min_u32 s16, s5, s21
; GFX6-NEXT: s_cselect_b32 s16, s5, s21
; GFX6-NEXT: s_sub_i32 s5, s5, s16 ; GFX6-NEXT: s_sub_i32 s5, s5, s16
; GFX6-NEXT: s_cmp_lt_u32 s6, s22 ; GFX6-NEXT: s_min_u32 s16, s6, s22
; GFX6-NEXT: s_cselect_b32 s16, s6, s22
; GFX6-NEXT: s_sub_i32 s6, s6, s16 ; GFX6-NEXT: s_sub_i32 s6, s6, s16
; GFX6-NEXT: s_cmp_lt_u32 s7, s23 ; GFX6-NEXT: s_min_u32 s16, s7, s23
; GFX6-NEXT: s_cselect_b32 s16, s7, s23
; GFX6-NEXT: s_sub_i32 s7, s7, s16 ; GFX6-NEXT: s_sub_i32 s7, s7, s16
; GFX6-NEXT: s_cmp_lt_u32 s8, s24 ; GFX6-NEXT: s_min_u32 s16, s8, s24
; GFX6-NEXT: s_cselect_b32 s16, s8, s24
; GFX6-NEXT: s_sub_i32 s8, s8, s16 ; GFX6-NEXT: s_sub_i32 s8, s8, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s25 ; GFX6-NEXT: s_min_u32 s16, s9, s25
; GFX6-NEXT: s_cselect_b32 s16, s9, s25
; GFX6-NEXT: s_sub_i32 s9, s9, s16 ; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_u32 s10, s26 ; GFX6-NEXT: s_min_u32 s16, s10, s26
; GFX6-NEXT: s_cselect_b32 s16, s10, s26
; GFX6-NEXT: s_sub_i32 s10, s10, s16 ; GFX6-NEXT: s_sub_i32 s10, s10, s16
; GFX6-NEXT: s_cmp_lt_u32 s11, s27 ; GFX6-NEXT: s_min_u32 s16, s11, s27
; GFX6-NEXT: s_cselect_b32 s16, s11, s27
; GFX6-NEXT: s_sub_i32 s11, s11, s16 ; GFX6-NEXT: s_sub_i32 s11, s11, s16
; GFX6-NEXT: s_cmp_lt_u32 s12, s28 ; GFX6-NEXT: s_min_u32 s16, s12, s28
; GFX6-NEXT: s_cselect_b32 s16, s12, s28
; GFX6-NEXT: s_sub_i32 s12, s12, s16 ; GFX6-NEXT: s_sub_i32 s12, s12, s16
; GFX6-NEXT: s_cmp_lt_u32 s13, s29 ; GFX6-NEXT: s_min_u32 s16, s13, s29
; GFX6-NEXT: s_cselect_b32 s16, s13, s29
; GFX6-NEXT: s_sub_i32 s13, s13, s16 ; GFX6-NEXT: s_sub_i32 s13, s13, s16
; GFX6-NEXT: s_cmp_lt_u32 s14, s30 ; GFX6-NEXT: s_min_u32 s16, s14, s30
; GFX6-NEXT: s_cselect_b32 s16, s14, s30
; GFX6-NEXT: s_sub_i32 s14, s14, s16 ; GFX6-NEXT: s_sub_i32 s14, s14, s16
; GFX6-NEXT: s_cmp_lt_u32 s15, s31 ; GFX6-NEXT: s_min_u32 s16, s15, s31
; GFX6-NEXT: s_cselect_b32 s16, s15, s31
; GFX6-NEXT: s_sub_i32 s15, s15, s16 ; GFX6-NEXT: s_sub_i32 s15, s15, s16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v16i32: ; GFX8-LABEL: s_usubsat_v16i32:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s16 ; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: v_mov_b32_e32 v1, s17 ; GFX8-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NEXT: v_mov_b32_e32 v2, s18 ; GFX8-NEXT: v_mov_b32_e32 v2, s18
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i16 %result ret i16 %result
} }
define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) { define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i16: ; GFX6-LABEL: s_usubsat_i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_cmp_lt_u32 s0, s1 ; GFX6-NEXT: s_min_u32 s1, s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1 ; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 16 ; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i16: ; GFX8-LABEL: s_usubsat_i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp ; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <2 x i16> %result ret <2 x i16> %result
} }
define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) { define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v2i16: ; GFX6-LABEL: s_usubsat_v2i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_cmp_lt_u32 s0, s2 ; GFX6-NEXT: s_min_u32 s2, s0, s2
; GFX6-NEXT: s_cselect_b32 s2, s0, s2
; GFX6-NEXT: s_sub_i32 s0, s0, s2 ; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s3, 16 ; GFX6-NEXT: s_lshl_b32 s2, s3, 16
; GFX6-NEXT: s_cmp_lt_u32 s1, s2 ; GFX6-NEXT: s_min_u32 s2, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2 ; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 16 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v2i16: ; GFX8-LABEL: s_usubsat_v2i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16 ; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <2 x float> %cast ret <2 x float> %cast
} }
define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) { define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v4i16: ; GFX6-LABEL: s_usubsat_v4i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_cmp_lt_u32 s0, s4 ; GFX6-NEXT: s_min_u32 s4, s0, s4
; GFX6-NEXT: s_cselect_b32 s4, s0, s4
; GFX6-NEXT: s_sub_i32 s0, s0, s4 ; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s4, s5, 16 ; GFX6-NEXT: s_lshl_b32 s4, s5, 16
; GFX6-NEXT: s_cmp_lt_u32 s1, s4 ; GFX6-NEXT: s_min_u32 s4, s1, s4
; GFX6-NEXT: s_cselect_b32 s4, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s4 ; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s4, s6, 16 ; GFX6-NEXT: s_lshl_b32 s4, s6, 16
; GFX6-NEXT: s_cmp_lt_u32 s2, s4 ; GFX6-NEXT: s_min_u32 s4, s2, s4
; GFX6-NEXT: s_cselect_b32 s4, s2, s4
; GFX6-NEXT: s_sub_i32 s2, s2, s4 ; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s7, 16 ; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_cmp_lt_u32 s3, s4 ; GFX6-NEXT: s_min_u32 s4, s3, s4
; GFX6-NEXT: s_cselect_b32 s4, s3, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s3, s3, s4 ; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16 ; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v4i16: ; GFX8-LABEL: s_usubsat_v4i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16 ; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16 ; GFX8-NEXT: s_lshr_b32 s7, s3, 16
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <3 x float> %cast ret <3 x float> %cast
} }
define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) { define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v6i16: ; GFX6-LABEL: s_usubsat_v6i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_cmp_lt_u32 s0, s6 ; GFX6-NEXT: s_min_u32 s6, s0, s6
; GFX6-NEXT: s_cselect_b32 s6, s0, s6
; GFX6-NEXT: s_sub_i32 s0, s0, s6 ; GFX6-NEXT: s_sub_i32 s0, s0, s6
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s6, s7, 16 ; GFX6-NEXT: s_lshl_b32 s6, s7, 16
; GFX6-NEXT: s_cmp_lt_u32 s1, s6 ; GFX6-NEXT: s_min_u32 s6, s1, s6
; GFX6-NEXT: s_cselect_b32 s6, s1, s6
; GFX6-NEXT: s_sub_i32 s1, s1, s6 ; GFX6-NEXT: s_sub_i32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s6, s8, 16 ; GFX6-NEXT: s_lshl_b32 s6, s8, 16
; GFX6-NEXT: s_cmp_lt_u32 s2, s6 ; GFX6-NEXT: s_min_u32 s6, s2, s6
; GFX6-NEXT: s_cselect_b32 s6, s2, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s6 ; GFX6-NEXT: s_sub_i32 s2, s2, s6
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s6, s9, 16 ; GFX6-NEXT: s_lshl_b32 s6, s9, 16
; GFX6-NEXT: s_cmp_lt_u32 s3, s6 ; GFX6-NEXT: s_min_u32 s6, s3, s6
; GFX6-NEXT: s_cselect_b32 s6, s3, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s6 ; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s6, s10, 16 ; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_cmp_lt_u32 s4, s6 ; GFX6-NEXT: s_min_u32 s6, s4, s6
; GFX6-NEXT: s_cselect_b32 s6, s4, s6
; GFX6-NEXT: s_sub_i32 s4, s4, s6 ; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s11, 16 ; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_cmp_lt_u32 s5, s6 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_cselect_b32 s6, s5, s6 ; GFX6-NEXT: s_min_u32 s6, s5, s6
; GFX6-NEXT: s_sub_i32 s5, s5, s6 ; GFX6-NEXT: s_sub_i32 s5, s5, s6
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16 ; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s2, s5, 16 ; GFX6-NEXT: s_lshl_b32 s2, s5, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2 ; GFX6-NEXT: s_or_b32 s2, s4, s2
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v6i16: ; GFX8-LABEL: s_usubsat_v6i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16 ; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16 ; GFX8-NEXT: s_lshr_b32 s10, s4, 16
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; GFX10-NEXT: s_setpc_b64 s[30:31]
ret <4 x float> %cast ret <4 x float> %cast
} }
define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) { define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v8i16: ; GFX6-LABEL: s_usubsat_v8i16:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16 ; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s8, s8, 16 ; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_cmp_lt_u32 s0, s8 ; GFX6-NEXT: s_min_u32 s8, s0, s8
; GFX6-NEXT: s_cselect_b32 s8, s0, s8
; GFX6-NEXT: s_sub_i32 s0, s0, s8 ; GFX6-NEXT: s_sub_i32 s0, s0, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s8, s9, 16 ; GFX6-NEXT: s_lshl_b32 s8, s9, 16
; GFX6-NEXT: s_cmp_lt_u32 s1, s8 ; GFX6-NEXT: s_min_u32 s8, s1, s8
; GFX6-NEXT: s_cselect_b32 s8, s1, s8
; GFX6-NEXT: s_sub_i32 s1, s1, s8 ; GFX6-NEXT: s_sub_i32 s1, s1, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16 ; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s8, s10, 16 ; GFX6-NEXT: s_lshl_b32 s8, s10, 16
; GFX6-NEXT: s_cmp_lt_u32 s2, s8 ; GFX6-NEXT: s_min_u32 s8, s2, s8
; GFX6-NEXT: s_cselect_b32 s8, s2, s8
; GFX6-NEXT: s_sub_i32 s2, s2, s8 ; GFX6-NEXT: s_sub_i32 s2, s2, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s8, s11, 16 ; GFX6-NEXT: s_lshl_b32 s8, s11, 16
; GFX6-NEXT: s_cmp_lt_u32 s3, s8 ; GFX6-NEXT: s_min_u32 s8, s3, s8
; GFX6-NEXT: s_cselect_b32 s8, s3, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s8 ; GFX6-NEXT: s_sub_i32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16 ; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s8, s12, 16 ; GFX6-NEXT: s_lshl_b32 s8, s12, 16
; GFX6-NEXT: s_cmp_lt_u32 s4, s8 ; GFX6-NEXT: s_min_u32 s8, s4, s8
; GFX6-NEXT: s_cselect_b32 s8, s4, s8
; GFX6-NEXT: s_sub_i32 s4, s4, s8 ; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16 ; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s8, s13, 16 ; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_cmp_lt_u32 s5, s8 ; GFX6-NEXT: s_min_u32 s8, s5, s8
; GFX6-NEXT: s_cselect_b32 s8, s5, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8 ; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16 ; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s8, s14, 16 ; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_cmp_lt_u32 s6, s8 ; GFX6-NEXT: s_min_u32 s8, s6, s8
; GFX6-NEXT: s_cselect_b32 s8, s6, s8
; GFX6-NEXT: s_sub_i32 s6, s6, s8 ; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_lshr_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16 ; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16 ; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_cmp_lt_u32 s7, s8 ; GFX6-NEXT: s_lshr_b32 s1, s1, 16
; GFX6-NEXT: s_cselect_b32 s8, s7, s8 ; GFX6-NEXT: s_min_u32 s8, s7, s8
; GFX6-NEXT: s_sub_i32 s7, s7, s8 ; GFX6-NEXT: s_sub_i32 s7, s7, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s1, s3, 16 ; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16 ; GFX6-NEXT: s_lshr_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s3, s7, 16 ; GFX6-NEXT: s_lshr_b32 s5, s5, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1 ; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_lshr_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s2, s5, 16 ; GFX6-NEXT: s_lshl_b32 s2, s5, 16
; GFX6-NEXT: s_lshr_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s3, s7, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2 ; GFX6-NEXT: s_or_b32 s2, s4, s2
; GFX6-NEXT: s_or_b32 s3, s6, s3 ; GFX6-NEXT: s_or_b32 s3, s6, s3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_v8i16: ; GFX8-LABEL: s_usubsat_v8i16:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16 ; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16 ; GFX8-NEXT: s_lshr_b32 s13, s5, 16
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