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[GlobalISel] Add G_ASSERT_ZEXT
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Authored by paquette on Jan 27 2021, 2:30 PM.

Details

Summary

This adds a generic opcode which communicates that a type has already been zero-extended from a narrower type.

This is intended to be similar to AssertZext in SelectionDAG.

For example,

%x_was_extended:_(s64) = G_ASSERT_ZEXT %x, 16

Signifies that the top 48 bits of %x are known to be 0.

This is useful in cases like this:

define i1 @zeroext_param(i8 zeroext %x) {
    %cmp = icmp ult i8 %x, -20
    ret i1 %cmp
}

In AArch64, %x must use a 32-bit register, which is then truncated to a 8-bit value.

If we know that %x is already zero-ed out in the relevant high bits, we can avoid the truncate.

Currently, in GISel, this looks like this:

_zeroext_param:
    and w8, w0, #0xff ; We don't actually need this!
    cmp w8, #236
    cset w0, lo
    ret

While SDAG does not produce the truncation, since it knows that it's unnecessary:

_zeroext_param:
    cmp w0, #236
    cset w0, lo
    ret

This patch

  • Adds G_ASSERT_ZEXT
  • Adds MIRBuilder support for it
  • Adds MachineVerifier support for it
  • Documents it

It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.)

The reason for doing this rather than making it a pseudo like, say, COPY, is that these *are* pre-ISel generic opcodes. The only difference is

  1. They should be ignored by the legalizer
  2. They shouldn't impact register bank selection
  3. They should select to nothing

It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.)

Diff Detail

Event Timeline

paquette created this revision.Jan 27 2021, 2:30 PM
paquette requested review of this revision.Jan 27 2021, 2:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 27 2021, 2:30 PM
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paquette updated this revision to Diff 319701.Jan 27 2021, 3:49 PM
paquette edited the summary of this revision. (Show Details)
  • Remove requirement that these be removed before regbankselect. @arsenm mentioned that it's useful to have these in selection.
  • Pull these out of PRE_ISEL_GENERIC_OPCODE_*, and place them above in their own markers. That way, isPreISelGenericOpcode doesn't return true for them, but we can still communicate that they are GlobalISel-specific hints.
arsenm added inline comments.Jan 27 2021, 4:11 PM
llvm/include/llvm/Target/GenericOpcodes.td
1345–1346

Should mention this behaves identically to a COPY

llvm/lib/CodeGen/MachineVerifier.cpp
946

I think these assert messages aren't consistent with using 0 indexing or not, but I guess this is the better direction

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-hint.mir
18

Should probably include a case with an illegal register type

The copy-look-through util functions should probably look through this, although that's a separate patch

paquette updated this revision to Diff 319711.Jan 27 2021, 4:31 PM
  • Update documentation to include that this behaves like a COPY
  • Add two testcases for invalid registers to the MachineVerifier test (type mismatch, physical register)

We should clarify what kind of copies this is allowed to do. As a hint, I think it shouldn't be legal to use this copy to change regbanks, or regclasses, or to use/define physical registers. As a hint, it should be guaranteed to be safe to look through to the vreg source.

paquette updated this revision to Diff 319933.Jan 28 2021, 11:40 AM
  • Update docs to clarify what kinds of COPY instructions are allowed
  • Update MachineVerifier to check regbank/regclass restrictions + add a test
arsenm accepted this revision.Jan 28 2021, 12:23 PM
arsenm added inline comments.
llvm/test/MachineVerifier/test_g_assert_zext_register_bank_class.mir
4–8 ↗(On Diff #319933)

Don't need the IR section

This revision is now accepted and ready to land.Jan 28 2021, 12:23 PM
This revision was automatically updated to reflect the committed changes.