[GlobalISel] Walk through hints in getDefIgnoringCopies et al

[paquette]

Summary

Treat hint instructions like G_ASSERT_ZEXT like COPY instructions in helpers which walk through copies.

This ensures that instructions like G_ASSERT_ZEXT won't impact any optimizations that rely on these helpers.

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir

3–11

You can drop this IR section

[thakis]

Looks like this breaks tests: http://45.33.8.238/linux/38250/step_12.txt

Please take a look and revert for now if it takes a while to fix.

[paquette]

Reverted while I take a look at the test failures...

[paquette]

Fixed + recommitted in daffab1985f1b20081db774d152bcac86b840581

llvm/include/llvm/CodeGen/GlobalISel/Utils.h

 /// defines it.
 struct DefinitionAndSourceRegister {
   MachineInstr *MI;
   Register Reg;
 };
 
 /// Find the def instruction for \p Reg, and underlying value Register folding
 /// away any copies.
+///
+/// Also walks through hints such as G_ASSERT_ZEXT.
 Optional<DefinitionAndSourceRegister>
 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
 
 /// Find the def instruction for \p Reg, folding away any trivial copies. May
 /// return nullptr if \p Reg is not a generic virtual register.
+///
+/// Also walks through hints such as G_ASSERT_ZEXT.
 MachineInstr *getDefIgnoringCopies(Register Reg,
                                    const MachineRegisterInfo &MRI);
 
 /// Find the source register for \p Reg, folding away any trivial copies. It
 /// will be an output register of the instruction that getDefIgnoringCopies
 /// returns. May return an invalid register if \p Reg is not a generic virtual
 /// register.
-Register getSrcRegIgnoringCopies(Register Reg,
-                                 const MachineRegisterInfo &MRI);
+///
+/// Also walks through hints such as G_ASSERT_ZEXT.
+Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
 
 /// Returns an APFloat from Val converted to the appropriate size.
 APFloat getAPFloatFromSize(double Val, unsigned Size);
 
 /// Modify analysis usage so it preserves passes required for the SelectionDAG
 /// fallback.
 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
 

llvm/lib/CodeGen/GlobalISel/Utils.cpp

 
 Optional<DefinitionAndSourceRegister>
 llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) {
   Register DefSrcReg = Reg;
   auto *DefMI = MRI.getVRegDef(Reg);
   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
   if (!DstTy.isValid())
     return None;
-  while (DefMI->getOpcode() == TargetOpcode::COPY) {
+  unsigned Opc = DefMI->getOpcode();
+  while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
     Register SrcReg = DefMI->getOperand(1).getReg();
     auto SrcTy = MRI.getType(SrcReg);
     if (!SrcTy.isValid())
       break;
+    Opc = DefMI->getOpcode();
     DefMI = MRI.getVRegDef(SrcReg);
     DefSrcReg = SrcReg;
   }
   return DefinitionAndSourceRegister{DefMI, DefSrcReg};
 }
 
 MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
                                          const MachineRegisterInfo &MRI) {

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   declare void @foo()
   define void @self() { ret void }
   define void @self_with_copy() { ret void }
   define void @self_not_equivalent_overwrite_w0() { ret void }
   define void @self_not_equivalent_overwrite_w0_implicit() { ret void }
   define void @self_not_equivalent_different_copies() { ret void }
+  define void @self_with_assert_zext() { ret void }
 ...
 ---
 name:            self
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; Optimize (cond ? %a : %a) -> %a
     ; CHECK-LABEL: name: self
bb.0:
     %c:_(s32) = COPY %b
     %cond_wide:gpr(s32) = COPY $w1
     %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
     %select:_(s32) = G_SELECT %cond(s1), %a, %c
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 
 ...
+---
+name:            self_with_assert_zext
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+    ; We should walk through G_ASSERT_ZEXT as if it's a copy, and remove the
+    ; G_SELECT.
+    ;
+    ; CHECK-LABEL: name: self_with_assert_zext
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %a:_(s32) = COPY $w0
+    ; CHECK: %a_assert_zext:_(s32) = G_ASSERT_ZEXT %a, 16
+    ; CHECK: $w0 = COPY %a_assert_zext(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %a:_(s32) = COPY $w0
+    %a_assert_zext:_(s32) = G_ASSERT_ZEXT %a, 16
+    %b:_(s32) = COPY %a_assert_zext
+    %cond_wide:gpr(s32) = COPY $w1
+    %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
+    %select:_(s32) = G_SELECT %cond(s1), %a_assert_zext, %b
+    $w0 = COPY %select(s32)
+    RET_ReallyLR implicit $w0