[GlobalISel] Add hint elimination combine

[paquette]

Summary

This adds a hint elimination combine, which changes

%x = ...
%y = G_ASSERT_ZEXT %x, n
...
%z = G_FOO ... %y ...

into

%x = ...
...
%z = G_FOO ... %x

This is intended to run in a late combiner, post-legalization.

[arsenm]

I think letting the selector handle these as copies would be better. The selector still benefits from the known bits information

[paquette]

Going to try and plumb this through to the selector instead.

llvm/include/llvm/Target/GlobalISel/Combine.td

def load_or_combine : GICombineRule<
   (match (wip_match_opcode G_OR):$root,
     [{ return Helper.matchLoadOrCombine(*${root}, ${info}); }]),
   (apply [{ return Helper.applyLoadOrCombine(*${root}, ${info}); }])>;
 
 // Currently only the one combine above.
 def insert_vec_elt_combines : GICombineGroup<
                             [combine_insert_vec_elts_build_vector]>;
 
+// Remove hint instructions in the same way as copies.
+//
+// %x = ...
+// %y = G_ASSERT_ZEXT %x, n
+// ... = G_FOO %y, ...
+// ->
+//
+// %x = ...
+// ... G_FOO %x, ...
+def eliminate_hints: GICombineRule<
+  (defs root:$root),
+  (match (wip_match_opcode G_ASSERT_ZEXT):$root,
+         [{ return true; }]),
+  (apply [{ Helper.applyCombineCopy(*${root}); }])>;
+
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      undef_to_negative_one,
                                      binop_left_undef_to_zero,
                                      propagate_undef_any_op,
                                      propagate_undef_all_ops,
                                      propagate_undef_shuffle_mask,
                                      erase_undef_store]>;

llvm/lib/Target/AArch64/AArch64Combine.td

 >;
 
 // Post-legalization combines which should happen at all optimization levels.
 // (E.g. ones that facilitate matching for the selector) For example, matching
 // pseudos.
 def AArch64PostLegalizerLoweringHelper
     : GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper",
                        [shuffle_vector_pseudos, vashr_vlshr_imm,
-                        icmp_lowering, form_duplane]> {
+                        icmp_lowering, form_duplane, eliminate_hints]> {
   let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule";
 }
 
 // Post-legalization combines which are primarily optimizations.
 def AArch64PostLegalizerCombinerHelper
     : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                        [copy_prop, erase_undef_store, combines_for_extload,
                         sext_trunc_sextload,
                         hoist_logic_op_with_same_opcode_hands,
                         redundant_and, xor_of_and_with_same_reg,
                         extractvecelt_pairwise_add, redundant_or,
                         mul_const]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-hint.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Check that we remove hint instructions.
+
+---
+name:            assert_zext
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $w0, $w1
+    ; CHECK-LABEL: name: assert_zext
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:_(s32) = COPY $w1
+    ; CHECK: $w0 = COPY %copy(s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %copy:_(s32) = COPY $w1
+    %hint:_(s32) = G_ASSERT_ZEXT %copy, 16
+    $w0 = COPY %hint
+    RET_ReallyLR implicit $w0
+...