[ARM] Add MVE insert-of-extract pattern

[dmgreen]

Summary

A v4i32 insert of an extract can become a simple lane move, as opposed to round-tripping via a GPR. This adds a patterns that turns an v4i32 insert-extract pair into a EXTRACT_SUBREG/INSERT_SUBREG, with the required COPY_TO_REGCLASS. These get better optimized into a simple lane move by the rest of the backed.

[SjoerdMeijer]

Looks like a nice change to me.

llvm/lib/Target/ARM/ARMInstrMVE.td

1857

Nit: looks like there is a precedent above, and that this is exceeding 80 columns.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrMVE.td

1857

Oof. I was worried you were going to say something like that. Some of these patterns do not fit well into 80 lines. I'll see what I can do.

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMInstrMVE.td

1857

Well, do we actually have a coding style for tablegen?
Perhaps this is clearer than breaking it up and there's enough prior art, so perhaps ignore this.

llvm/lib/Target/ARM/ARMInstrMVE.td

let Predicates = [HasMVEInt] in {
   def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane),
             (INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane))>;
 
   def : Pat<(extractelt (v4i32 MQPR:$src), imm:$lane),
             (COPY_TO_REGCLASS
               (i32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), rGPR)>;
   def : Pat<(insertelt (v4i32 MQPR:$src1), rGPR:$src2, imm:$lane),
             (MVE_VMOV_to_lane_32 MQPR:$src1, rGPR:$src2, imm:$lane)>;
+  // This tries to copy from one lane to another, without going via GPR regs
+  def : Pat<(insertelt (v4i32 MQPR:$src1), (extractelt (v4i32 MQPR:$src2), imm:$extlane), imm:$inslane),
+            (v4i32 (COPY_TO_REGCLASS
+                     (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4i32 MQPR:$src1), MQPR)),
+                                    (f32 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4i32 MQPR:$src2), MQPR)),
+                                                         (SSubReg_f32_reg imm:$extlane))),
+                                    (SSubReg_f32_reg imm:$inslane)),
+                      MQPR))>;
 
   def : Pat<(vector_insert (v16i8 MQPR:$src1), rGPR:$src2, imm:$lane),
             (MVE_VMOV_to_lane_8  MQPR:$src1, rGPR:$src2, imm:$lane)>;
   def : Pat<(vector_insert (v8i16 MQPR:$src1), rGPR:$src2, imm:$lane),
             (MVE_VMOV_to_lane_16 MQPR:$src1, rGPR:$src2, imm:$lane)>;
 
   def : Pat<(ARMvgetlanes (v16i8 MQPR:$src), imm:$lane),
             (MVE_VMOV_from_lane_s8 MQPR:$src, imm:$lane)>;

llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll

entry:
   %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %xx)
   ret i64 %z
 }
 
 define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_sext(<2 x i32> %x) {
 ; CHECK-LABEL: add_v2i32_v2i64_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov r0, s0
-; CHECK-NEXT:    vmov.32 q1[0], r0
+; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    vmov r2, s2
 ; CHECK-NEXT:    asrs r1, r0, #31
 ; CHECK-NEXT:    vmov.32 q1[1], r1
 ; CHECK-NEXT:    vmov r0, s4
 ; CHECK-NEXT:    adds r0, r0, r2
 ; CHECK-NEXT:    adc.w r1, r1, r2, asr #31
 ; CHECK-NEXT:    bx lr
 entry:
entry:
   %r = add i64 %z, %a
   ret i64 %r
 }
 
 define arm_aapcs_vfpcc i64 @add_v2i32_v2i64_acc_sext(<2 x i32> %x, i64 %a) {
 ; CHECK-LABEL: add_v2i32_v2i64_acc_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov r2, s0
-; CHECK-NEXT:    vmov.32 q1[0], r2
+; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    vmov r3, s2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov.32 q1[1], r2
 ; CHECK-NEXT:    vmov r12, s4
 ; CHECK-NEXT:    adds.w r12, r12, r3
 ; CHECK-NEXT:    adc.w r2, r2, r3, asr #31
 ; CHECK-NEXT:    adds.w r0, r0, r12
 ; CHECK-NEXT:    adcs r1, r2