[ARM] Add neon FP16 scalar_to_vector patterns.

[dmgreen]

Summary

This adds some simple fp16 scalar_to_vector patterns, preventing a selection failure if this came up.

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMInstrNEON.td

6484–6485

Unrelated to this patch, but while we are at it, I spotted this commented out def. Shall we get rid of this?

[dmgreen]

Sure. Removed commented out code.

[SjoerdMeijer]

Cheers.

llvm/lib/Target/ARM/ARMInstrNEON.td

 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
           (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
                                 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
           (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
                                 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
 
 defm : InsertEltF16<f16, v4f16, v8f16>;
 
-//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
-//          (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
           (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
 
 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
           (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
           (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
 
+def : Pat<(v4f16 (scalar_to_vector (f16 HPR:$src))),
+          (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
+def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))),
+          (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
+
 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
           (VSETLNi8  (v8i8  (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
           (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
           (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
 
 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),

llvm/test/CodeGen/ARM/fp16-insert-extract.ll

 ; CHECKSOFT-NEXT:    vmov r0, s0
 ; CHECKSOFT-NEXT:    bx lr
 entry:
   %elt = extractelement <8 x half> %a, i32 7
   %conv = fpext half %elt to float
   ret float %conv
 }
 
+define <4 x half> @insert_v4f16(half %a) {
+; CHECKHARD-LABEL: insert_v4f16:
+; CHECKHARD:       @ %bb.0: @ %entry
+; CHECKHARD-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECKHARD-NEXT:    bx lr
+;
+; CHECKSOFT-LABEL: insert_v4f16:
+; CHECKSOFT:       @ %bb.0: @ %entry
+; CHECKSOFT-NEXT:    vmov.f16 s0, r0
+; CHECKSOFT-NEXT:    vmov r0, r1, d0
+; CHECKSOFT-NEXT:    bx lr
+entry:
+  %res = insertelement <4 x half> undef, half %a, i32 0
+  ret <4 x half> %res
+}
+
+define <8 x half> @insert_v8f16(half %a) {
+; CHECKHARD-LABEL: insert_v8f16:
+; CHECKHARD:       @ %bb.0: @ %entry
+; CHECKHARD-NEXT:    @ kill: def $s0 killed $s0 def $q0
+; CHECKHARD-NEXT:    bx lr
+;
+; CHECKSOFT-LABEL: insert_v8f16:
+; CHECKSOFT:       @ %bb.0: @ %entry
+; CHECKSOFT-NEXT:    vmov.f16 s0, r0
+; CHECKSOFT-NEXT:    vmov r2, r3, d1
+; CHECKSOFT-NEXT:    vmov r0, r1, d0
+; CHECKSOFT-NEXT:    bx lr
+entry:
+  %res = insertelement <8 x half> undef, half %a, i32 0
+  ret <8 x half> %res
+}
+
 define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
 ; CHECKHARD-LABEL: test_vset_lane_f16:
 ; CHECKHARD:       @ %bb.0: @ %entry
 ; CHECKHARD-NEXT:    vcvtt.f16.f32 s1, s2
 ; CHECKHARD-NEXT:    bx lr
 ;
 ; CHECKSOFT-LABEL: test_vset_lane_f16:
 ; CHECKSOFT:       @ %bb.0: @ %entry