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Differential D95381

[ARM] Select VINS from vector inserts
ClosedPublic

Authored by dmgreen on Jan 25 2021, 11:43 AM.

Details

Reviewers
SjoerdMeijer
NickGuy
efriedma
simon_tatham
ostannard
Commits
rGc72257563347: [ARM] Select VINS from vector inserts
Summary

This patch adds tablegen patterns for pairs of i16/f16 insert/extracts. If we are inserting into two adjacent vector lanes (0 and 1 for example), we can use either a vmov; vins or vmovx; vins` to insert the pair together, avoiding a round-trip from GRP registers. This is quite a large patterns with a number of EXTRACT_SUBREG/INSERT_SUBREG/COPY_TO_REGCLASS nodes, but hopefully as most of those become copies all that will be cleaned up by further optimizations.

The VINS pattern was also adjusted to allow it to represent that it is inserting into the top half of an existing register.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 25 2021, 11:43 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJan 25 2021, 11:43 AM
dmgreen requested review of this revision.Jan 25 2021, 11:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 25 2021, 11:43 AM
dmgreen added a child revision: D95428: [ARM] Add MVE insert-of-extract pattern.Jan 26 2021, 3:19 AM
dmgreen added a parent revision: D95073: [ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu.
SjoerdMeijer added inline comments.Jan 26 2021, 5:28 AM
llvm/lib/Target/ARM/ARMInstrVFP.td
1131

It's unclear to me why we need 2 inputs to model that it is inserting into the top half of an existing register. I forgot if this is how that's done, is there precedent for this?

dmgreen added inline comments.Jan 26 2021, 9:37 AM
llvm/lib/Target/ARM/ARMInstrVFP.td
1131

It's similar to how most things work, yeah. Things like VMOVHcc work like that, or any of the MVE vp.inactive where you conditionally move lanes of the input into the output. The VMOVN also have an input for Qd_src and an output for Qd, combining the two into a single value.

We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.

SjoerdMeijer added inline comments.Jan 26 2021, 9:45 AM
llvm/lib/Target/ARM/ARMInstrVFP.td
1131

We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.

Okay, but should the constraint then be:

"$Sd = $Sm"

Sorry, I might be using you to relearn isel patterns....

SjoerdMeijer added inline comments.Jan 26 2021, 9:47 AM
llvm/lib/Target/ARM/ARMInstrVFP.td
1131

correction:

"$Sda = $Sm"
dmgreen updated this revision to Diff 319371.EditedJan 26 2021, 11:55 AM

I managed to simplify the f16 side of this whilst working on another pattern. It now only handles the two inserts - not requiring them to be extracts too. This allows it to handle more cases with less code, which is always good to see.

It does require adding an added complexity to VCVTT to make it take precedence still.

llvm/lib/Target/ARM/ARMInstrVFP.td
1131

I think it's good as-is - we want to make sure the Sd and Sda are the same register. The final instruction is then VINS Sd, Sm, and with Sda==Sd we are now inserting Sm into the top half of Sda, to produce Sd.

SjoerdMeijer accepted this revision.Jan 27 2021, 7:58 AM

LGTM

llvm/lib/Target/ARM/ARMInstrVFP.td
1131

Ah, yep, got it again, thanks.

This revision is now accepted and ready to land.Jan 27 2021, 7:58 AM
Closed by commit rGc72257563347: [ARM] Select VINS from vector inserts (authored by dmgreen). · Explain WhyFeb 2 2021, 5:50 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGc72257563347: [ARM] Select VINS from vector inserts.

Revision Contents

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llvm/
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ARM/
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test/
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LowOverheadLoops/
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Diff 320763

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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def MVE_VMOV_to_lane_32 : MVE_VMOV_lane_32< MVE_VMOV_to_lane>; def MVE_VMOV_to_lane_32 : MVE_VMOV_lane_32< MVE_VMOV_to_lane>;
def MVE_VMOV_from_lane_s16 : MVE_VMOV_lane_16<"s16", 0b0, MVE_VMOV_from_lane>; def MVE_VMOV_from_lane_s16 : MVE_VMOV_lane_16<"s16", 0b0, MVE_VMOV_from_lane>;
def MVE_VMOV_from_lane_u16 : MVE_VMOV_lane_16<"u16", 0b1, MVE_VMOV_from_lane>; def MVE_VMOV_from_lane_u16 : MVE_VMOV_lane_16<"u16", 0b1, MVE_VMOV_from_lane>;
def MVE_VMOV_to_lane_16 : MVE_VMOV_lane_16< "16", 0b0, MVE_VMOV_to_lane>; def MVE_VMOV_to_lane_16 : MVE_VMOV_lane_16< "16", 0b0, MVE_VMOV_to_lane>;
def MVE_VMOV_from_lane_s8 : MVE_VMOV_lane_8 < "s8", 0b0, MVE_VMOV_from_lane>; def MVE_VMOV_from_lane_s8 : MVE_VMOV_lane_8 < "s8", 0b0, MVE_VMOV_from_lane>;
def MVE_VMOV_from_lane_u8 : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>; def MVE_VMOV_from_lane_u8 : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>;
def MVE_VMOV_to_lane_8 : MVE_VMOV_lane_8 < "8", 0b0, MVE_VMOV_to_lane>; def MVE_VMOV_to_lane_8 : MVE_VMOV_lane_8 < "8", 0b0, MVE_VMOV_to_lane>;
// This is the same as insertelt but allows the inserted value to be an i32 as
// will be used when it is the only legal type.
def ARMVecInsert : SDTypeProfile<1, 3, [
SDTCisVT<2, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
]>;
def ARMinsertelt : SDNode<"ISD::INSERT_VECTOR_ELT", ARMVecInsert>;
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(extractelt (v2f64 MQPR:$src), imm:$lane), def : Pat<(extractelt (v2f64 MQPR:$src), imm:$lane),
(f64 (EXTRACT_SUBREG MQPR:$src, (DSubReg_f64_reg imm:$lane)))>; (f64 (EXTRACT_SUBREG MQPR:$src, (DSubReg_f64_reg imm:$lane)))>;
def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane), def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane),
(INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane))>; (INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane))>;
def : Pat<(extractelt (v4i32 MQPR:$src), imm:$lane), def : Pat<(extractelt (v4i32 MQPR:$src), imm:$lane),
(COPY_TO_REGCLASS (COPY_TO_REGCLASS
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lineslet Predicates = [HasMVEInt] in {
def : Pat<(v4f32 (scalar_to_vector SPR:$src)), def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
def : Pat<(v4f32 (scalar_to_vector GPR:$src)), def : Pat<(v4f32 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_32 (v4f32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_32 (v4f32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))), def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))),
(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), (f16 HPR:$src), ssub_0)>; (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), (f16 HPR:$src), ssub_0)>;
def : Pat<(v8f16 (scalar_to_vector GPR:$src)), def : Pat<(v8f16 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_16 (v8f16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_16 (v8f16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
foreach LANE = [0, 2, 4, 6] in {
defvar SSUB = !cast<SubRegIndex>("ssub_"#!srl(LANE, 1));
// v8f16 pattern for inserting two lanes using a VINS
def : Pat<(insertelt (insertelt (v8f16 MQPR:$srcV), (f16 HPR:$src1), LANE),
(f16 HPR:$src2), !add(LANE,1)),
(COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$srcV, MQPR)),
(VINSH (COPY_TO_REGCLASS HPR:$src1, SPR),
(COPY_TO_REGCLASS HPR:$src2, SPR)),
SSUB), MQPR)>;
// v8i16 pattern for extracting 2 even lane elements and inserting them using a VINS
def : Pat<(ARMinsertelt (ARMinsertelt (v8i16 MQPR:$srcV),
(ARMvgetlaneu (v8i16 MQPR:$src1), imm_even:$lane1),
LANE),
(ARMvgetlaneu (v8i16 MQPR:$src2), imm_even:$lane2),
!add(LANE,1)),
(COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$srcV, MQPR)),
(VINSH (EXTRACT_SUBREG (v8f16 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
(SSubReg_f16_reg imm_even:$lane1)),
(EXTRACT_SUBREG (v8f16 (COPY_TO_REGCLASS MQPR:$src2, MQPR)),
(SSubReg_f16_reg imm_even:$lane2))),
SSUB), MQPR)>;
// v8i16 pattern for extracting an element using VMOVX and inserting another using a VINS
def : Pat<(ARMinsertelt (ARMinsertelt (v8i16 MQPR:$srcV),
(ARMvgetlaneu (v8i16 MQPR:$src1), imm_odd:$lane1),
LANE),
(ARMvgetlaneu (v8i16 MQPR:$src2), imm_even:$lane2),
!add(LANE,1)),
(COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$srcV, MQPR)),
(VINSH (VMOVH (EXTRACT_SUBREG (v8f16 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
(SSubReg_f16_reg imm_odd:$lane1))),
(EXTRACT_SUBREG (v8f16 (COPY_TO_REGCLASS MQPR:$src2, MQPR)),
(SSubReg_f16_reg imm_even:$lane2))),
SSUB), MQPR)>;
}
} }
// end of mve_bit instructions // end of mve_bit instructions
// start of MVE Integer instructions // start of MVE Integer instructions
class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]> class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
: MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary, : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
▲ Show 20 Lines • Show All 5,490 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 792 Lines • ▼ Show 20 Lines
let hasSideEffects = 0 in let hasSideEffects = 0 in
def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
[/* Intentionally left blank, see patterns below */]>, [/* Intentionally left blank, see patterns below */]>,
Requires<[HasFP16]>, Requires<[HasFP16]>,
Sched<[WriteFPCVT]>; Sched<[WriteFPCVT]>;
// AddedComplexity to use over the dual-insert MVE pattern
let AddedComplexity = 6 in
def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
(v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2), (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>; (SSubReg_f16_reg imm:$lane)))>;
def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
(v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2), (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>; (SSubReg_f16_reg imm:$lane)))>;
def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in { let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in {
def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0, def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>, IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
Requires<[HasFullFP16]>; Requires<[HasFullFP16]>;
def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0, def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

It's unclear to me why we need 2 inputs to model that it is inserting into the top half of an existing register. I forgot if this is how that's done, is there precedent for this?

SjoerdMeijer: It's unclear to me why we need 2 inputs to model that it is inserting into the top half of an…
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

It's similar to how most things work, yeah. Things like VMOVHcc work like that, or any of the MVE vp.inactive where you conditionally move lanes of the input into the output. The VMOVN also have an input for Qd_src and an output for Qd, combining the two into a single value.

We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.

dmgreen: It's similar to how most things work, yeah. Things like VMOVHcc work like that, or any of the…
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

We are taking some of the value from Sda (the bottom half) and some from Sm (the top half), combining them into a single value.

Okay, but should the constraint then be:

"$Sd = $Sm"

Sorry, I might be using you to relearn isel patterns....

SjoerdMeijer: > We are taking some of the value from Sda (the bottom half) and some from Sm (the top half)…
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

correction:

"$Sda = $Sm"
SjoerdMeijer: correction: "$Sda = $Sm"
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

I think it's good as-is - we want to make sure the Sd and Sda are the same register. The final instruction is then VINS Sd, Sm, and with Sda==Sd we are now inserting Sm into the top half of Sda, to produce Sd.

dmgreen: I think it's good as-is - we want to make sure the Sd and Sda are the same register. The final…
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

Ah, yep, got it again, thanks.

SjoerdMeijer: Ah, yep, got it again, thanks.
IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>, IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
Requires<[HasFullFP16]>; Requires<[HasFullFP16]> {
let Constraints = "$Sd = $Sda";
}
} // PostEncoderMethod } // PostEncoderMethod
} // hasSideEffects } // hasSideEffects
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FP <-> GPR Copies. Int <-> FP Conversions. // FP <-> GPR Copies. Int <-> FP Conversions.
// //
let isMoveReg = 1 in { let isMoveReg = 1 in {
▲ Show 20 Lines • Show All 1,726 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Linesfor.cond.cleanup: ; preds = %middle.block, %entry
%a.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %9, %middle.block ] %a.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %9, %middle.block ]
ret float %a.0.lcssa ret float %a.0.lcssa
} }
define arm_aapcs_vfpcc float @fast_float_half_mac(half* nocapture readonly %b, half* nocapture readonly %c, i32 %N) { define arm_aapcs_vfpcc float @fast_float_half_mac(half* nocapture readonly %b, half* nocapture readonly %c, i32 %N) {
; CHECK-LABEL: fast_float_half_mac: ; CHECK-LABEL: fast_float_half_mac:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: beq.w .LBB2_22 ; CHECK-NEXT: beq.w .LBB2_20
; CHECK-NEXT: @ %bb.1: @ %vector.ph ; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: adds r3, r2, #3 ; CHECK-NEXT: adds r3, r2, #3
; CHECK-NEXT: vmov.i32 q5, #0x0 ; CHECK-NEXT: vmov.i32 q5, #0x0
; CHECK-NEXT: bic r3, r3, #3 ; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: sub.w r12, r3, #4
; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2
; CHECK-NEXT: sub.w r12, r2, #1 ; CHECK-NEXT: sub.w r12, r2, #1
; CHECK-NEXT: adr r2, .LCPI2_1 ; CHECK-NEXT: adr r2, .LCPI2_1
; CHECK-NEXT: mov lr, lr ; CHECK-NEXT: mov lr, lr
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: vdup.32 q1, r12
; CHECK-NEXT: vdup.32 q2, r12 ; CHECK-NEXT: vdup.32 q2, r12
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: b .LBB2_3
; CHECK-NEXT: b .LBB2_4 ; CHECK-NEXT: .LBB2_2: @ %else26
; CHECK-NEXT: .LBB2_2: @ %cond.load25 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: vmul.f16 q5, q6, q5
; CHECK-NEXT: vmovx.f16 s0, s28
; CHECK-NEXT: vmov r4, s28
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q6[0], r4
; CHECK-NEXT: vldr.16 s0, [r1, #6]
; CHECK-NEXT: vmov.16 q6[1], r2
; CHECK-NEXT: vmov r2, s29
; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q6[3], r2
; CHECK-NEXT: .LBB2_3: @ %else26
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vmul.f16 q0, q6, q5
; CHECK-NEXT: adds r0, #8 ; CHECK-NEXT: adds r0, #8
; CHECK-NEXT: vcvtt.f32.f16 s23, s1 ; CHECK-NEXT: vcvtt.f32.f16 s27, s21
; CHECK-NEXT: adds r1, #8 ; CHECK-NEXT: adds r1, #8
; CHECK-NEXT: vcvtb.f32.f16 s22, s1 ; CHECK-NEXT: vcvtb.f32.f16 s26, s21
; CHECK-NEXT: adds r3, #4 ; CHECK-NEXT: adds r3, #4
; CHECK-NEXT: vcvtt.f32.f16 s21, s0 ; CHECK-NEXT: vcvtt.f32.f16 s25, s20
; CHECK-NEXT: vcvtb.f32.f16 s20, s0 ; CHECK-NEXT: vcvtb.f32.f16 s24, s20
; CHECK-NEXT: vadd.f32 q5, q3, q5 ; CHECK-NEXT: vadd.f32 q5, q3, q6
; CHECK-NEXT: subs.w lr, lr, #1 ; CHECK-NEXT: subs.w lr, lr, #1
; CHECK-NEXT: bne .LBB2_4 ; CHECK-NEXT: bne .LBB2_3
; CHECK-NEXT: b .LBB2_21 ; CHECK-NEXT: b .LBB2_19
; CHECK-NEXT: .LBB2_4: @ %vector.body ; CHECK-NEXT: .LBB2_3: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: @ implicit-def: $q6
; CHECK-NEXT: vadd.i32 q4, q0, r3 ; CHECK-NEXT: vadd.i32 q4, q0, r3
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vcmp.u32 cs, q1, q4 ; CHECK-NEXT: vcmp.u32 cs, q1, q4
; CHECK-NEXT: @ implicit-def: $q5
; CHECK-NEXT: vmrs r4, p0 ; CHECK-NEXT: vmrs r4, p0
; CHECK-NEXT: and r2, r4, #1 ; CHECK-NEXT: and r2, r4, #1
; CHECK-NEXT: rsbs r5, r2, #0 ; CHECK-NEXT: rsbs r5, r2, #0
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: bfi r2, r5, #0, #1 ; CHECK-NEXT: bfi r2, r5, #0, #1
; CHECK-NEXT: ubfx r5, r4, #4, #1 ; CHECK-NEXT: ubfx r5, r4, #4, #1
; CHECK-NEXT: rsbs r5, r5, #0 ; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: bfi r2, r5, #1, #1 ; CHECK-NEXT: bfi r2, r5, #1, #1
; CHECK-NEXT: ubfx r5, r4, #8, #1 ; CHECK-NEXT: ubfx r5, r4, #8, #1
; CHECK-NEXT: ubfx r4, r4, #12, #1 ; CHECK-NEXT: ubfx r4, r4, #12, #1
; CHECK-NEXT: rsbs r5, r5, #0 ; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: bfi r2, r5, #2, #1 ; CHECK-NEXT: bfi r2, r5, #2, #1
; CHECK-NEXT: rsbs r4, r4, #0 ; CHECK-NEXT: rsbs r4, r4, #0
; CHECK-NEXT: bfi r2, r4, #3, #1 ; CHECK-NEXT: bfi r2, r4, #3, #1
; CHECK-NEXT: lsls r4, r2, #31 ; CHECK-NEXT: lsls r4, r2, #31
; CHECK-NEXT: bne .LBB2_9 ; CHECK-NEXT: bne .LBB2_12
; CHECK-NEXT: @ %bb.5: @ %else ; CHECK-NEXT: @ %bb.4: @ %else
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r4, r2, #30 ; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bpl .LBB2_10 ; CHECK-NEXT: bmi .LBB2_13
; CHECK-NEXT: .LBB2_6: @ %cond.load6 ; CHECK-NEXT: .LBB2_5: @ %else7
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s20, [r0, #2]
; CHECK-NEXT: vmov r5, s24
; CHECK-NEXT: vmovx.f16 s24, s25
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.16 q5[0], r5
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov r4, s25
; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov r4, s24
; CHECK-NEXT: vmov.16 q5[3], r4
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bmi .LBB2_11 ; CHECK-NEXT: bmi .LBB2_14
; CHECK-NEXT: .LBB2_7: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: .LBB2_6: @ %else10
; CHECK-NEXT: vmov q6, q5 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bmi .LBB2_12
; CHECK-NEXT: .LBB2_8: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: b .LBB2_13
; CHECK-NEXT: .LBB2_9: @ %cond.load
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vldr.16 s24, [r0]
; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bmi .LBB2_6
; CHECK-NEXT: .LBB2_10: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bpl .LBB2_7
; CHECK-NEXT: .LBB2_11: @ %cond.load9
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vmovx.f16 s24, s20
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vldr.16 s28, [r0, #4]
; CHECK-NEXT: vmov r5, s24
; CHECK-NEXT: vmov.16 q6[0], r4
; CHECK-NEXT: vmovx.f16 s20, s21
; CHECK-NEXT: vmov.16 q6[1], r5
; CHECK-NEXT: vmov r4, s28
; CHECK-NEXT: vmov.16 q6[2], r4
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.16 q6[3], r4
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bpl .LBB2_8 ; CHECK-NEXT: bpl .LBB2_8
; CHECK-NEXT: .LBB2_12: @ %cond.load12 ; CHECK-NEXT: .LBB2_7: @ %cond.load12
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmovx.f16 s20, s24 ; CHECK-NEXT: vmovx.f16 s24, s20
; CHECK-NEXT: vmov r4, s24 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov.16 q5[0], r4
; CHECK-NEXT: vmov.16 q5[1], r2
; CHECK-NEXT: vmov r2, s25
; CHECK-NEXT: vldr.16 s24, [r0, #6] ; CHECK-NEXT: vldr.16 s24, [r0, #6]
; CHECK-NEXT: vmov.16 q5[2], r2 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmov r2, s24 ; CHECK-NEXT: .LBB2_8: @ %else13
; CHECK-NEXT: vmov.16 q5[3], r2 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: .LBB2_13: @ %else13
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1
; CHECK-NEXT: vcmp.u32 cs, q2, q4 ; CHECK-NEXT: vcmp.u32 cs, q2, q4
; CHECK-NEXT: @ implicit-def: $q7 ; CHECK-NEXT: @ implicit-def: $q6
; CHECK-NEXT: vmrs r4, p0 ; CHECK-NEXT: vmrs r4, p0
; CHECK-NEXT: and r2, r4, #1 ; CHECK-NEXT: and r2, r4, #1
; CHECK-NEXT: rsbs r5, r2, #0 ; CHECK-NEXT: rsbs r5, r2, #0
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: bfi r2, r5, #0, #1 ; CHECK-NEXT: bfi r2, r5, #0, #1
; CHECK-NEXT: ubfx r5, r4, #4, #1 ; CHECK-NEXT: ubfx r5, r4, #4, #1
; CHECK-NEXT: rsbs r5, r5, #0 ; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: bfi r2, r5, #1, #1 ; CHECK-NEXT: bfi r2, r5, #1, #1
; CHECK-NEXT: ubfx r5, r4, #8, #1 ; CHECK-NEXT: ubfx r5, r4, #8, #1
; CHECK-NEXT: ubfx r4, r4, #12, #1 ; CHECK-NEXT: ubfx r4, r4, #12, #1
; CHECK-NEXT: rsbs r5, r5, #0 ; CHECK-NEXT: rsbs r5, r5, #0
; CHECK-NEXT: bfi r2, r5, #2, #1 ; CHECK-NEXT: bfi r2, r5, #2, #1
; CHECK-NEXT: rsbs r4, r4, #0 ; CHECK-NEXT: rsbs r4, r4, #0
; CHECK-NEXT: bfi r2, r4, #3, #1 ; CHECK-NEXT: bfi r2, r4, #3, #1
; CHECK-NEXT: lsls r4, r2, #31 ; CHECK-NEXT: lsls r4, r2, #31
; CHECK-NEXT: bne .LBB2_17 ; CHECK-NEXT: bne .LBB2_15
; CHECK-NEXT: @ %bb.14: @ %else17 ; CHECK-NEXT: @ %bb.9: @ %else17
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bmi .LBB2_16
; CHECK-NEXT: .LBB2_10: @ %else20
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bmi .LBB2_17
; CHECK-NEXT: .LBB2_11: @ %else23
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bpl .LBB2_2
; CHECK-NEXT: b .LBB2_18
; CHECK-NEXT: .LBB2_12: @ %cond.load
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s20, [r0]
; CHECK-NEXT: lsls r4, r2, #30 ; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bpl .LBB2_18 ; CHECK-NEXT: bpl .LBB2_5
; CHECK-NEXT: .LBB2_15: @ %cond.load19 ; CHECK-NEXT: .LBB2_13: @ %cond.load6
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s24, [r1, #2] ; CHECK-NEXT: vldr.16 s24, [r0, #2]
; CHECK-NEXT: vmov r5, s28 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmovx.f16 s28, s29 ; CHECK-NEXT: vmovx.f16 s24, s21
; CHECK-NEXT: vmov r4, s24 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmov.16 q6[0], r5
; CHECK-NEXT: vmov.16 q6[1], r4
; CHECK-NEXT: vmov r4, s29
; CHECK-NEXT: vmov.16 q6[2], r4
; CHECK-NEXT: vmov r4, s28
; CHECK-NEXT: vmov.16 q6[3], r4
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bmi .LBB2_19 ; CHECK-NEXT: bpl .LBB2_6
; CHECK-NEXT: .LBB2_16: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: .LBB2_14: @ %cond.load9
; CHECK-NEXT: vmov q7, q6 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmovx.f16 s24, s20
; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmovx.f16 s24, s21
; CHECK-NEXT: vldr.16 s21, [r0, #4]
; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bmi.w .LBB2_2 ; CHECK-NEXT: bmi .LBB2_7
; CHECK-NEXT: b .LBB2_20 ; CHECK-NEXT: b .LBB2_8
; CHECK-NEXT: .LBB2_17: @ %cond.load16 ; CHECK-NEXT: .LBB2_15: @ %cond.load16
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s28, [r1] ; CHECK-NEXT: vldr.16 s24, [r1]
; CHECK-NEXT: lsls r4, r2, #30 ; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bmi .LBB2_15 ; CHECK-NEXT: bpl .LBB2_10
; CHECK-NEXT: .LBB2_18: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: .LBB2_16: @ %cond.load19
; CHECK-NEXT: vmov q6, q7 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s28, [r1, #2]
; CHECK-NEXT: vins.f16 s24, s28
; CHECK-NEXT: vmovx.f16 s28, s25
; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bpl .LBB2_16 ; CHECK-NEXT: bpl .LBB2_11
; CHECK-NEXT: .LBB2_19: @ %cond.load22 ; CHECK-NEXT: .LBB2_17: @ %cond.load22
; CHECK-NEXT: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmovx.f16 s28, s24 ; CHECK-NEXT: vmovx.f16 s28, s24
; CHECK-NEXT: vmov r4, s24 ; CHECK-NEXT: vins.f16 s24, s28
; CHECK-NEXT: vldr.16 s0, [r1, #4] ; CHECK-NEXT: vmovx.f16 s28, s25
; CHECK-NEXT: vmov r5, s28 ; CHECK-NEXT: vldr.16 s25, [r1, #4]
; CHECK-NEXT: vmov.16 q7[0], r4 ; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q7[1], r5
; CHECK-NEXT: vmovx.f16 s0, s25
; CHECK-NEXT: vmov.16 q7[2], r4
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q7[3], r4
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bmi.w .LBB2_2 ; CHECK-NEXT: bpl.w .LBB2_2
; CHECK-NEXT: .LBB2_20: @ in Loop: Header=BB2_4 Depth=1 ; CHECK-NEXT: .LBB2_18: @ %cond.load25
; CHECK-NEXT: vmov q6, q7 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: b .LBB2_3 ; CHECK-NEXT: vmovx.f16 s28, s24
; CHECK-NEXT: .LBB2_21: @ %middle.block ; CHECK-NEXT: vins.f16 s24, s28
; CHECK-NEXT: vldr.16 s28, [r1, #6]
; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: b .LBB2_2
; CHECK-NEXT: .LBB2_19: @ %middle.block
; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: vcmp.u32 cs, q0, q4 ; CHECK-NEXT: vcmp.u32 cs, q0, q4
; CHECK-NEXT: vpsel q0, q5, q3 ; CHECK-NEXT: vpsel q0, q5, q3
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vadd.f32 q0, q0, r0 ; CHECK-NEXT: vadd.f32 q0, q0, r0
; CHECK-NEXT: b .LBB2_23 ; CHECK-NEXT: b .LBB2_21
; CHECK-NEXT: .LBB2_22: ; CHECK-NEXT: .LBB2_20:
; CHECK-NEXT: vldr s0, .LCPI2_0 ; CHECK-NEXT: vldr s0, .LCPI2_0
; CHECK-NEXT: .LBB2_23: @ %for.cond.cleanup ; CHECK-NEXT: .LBB2_21: @ %for.cond.cleanup
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #8
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.24: ; CHECK-NEXT: @ %bb.22:
; CHECK-NEXT: .LCPI2_1: ; CHECK-NEXT: .LCPI2_1:
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
; CHECK-NEXT: .long 2 @ 0x2 ; CHECK-NEXT: .long 2 @ 0x2
; CHECK-NEXT: .long 3 @ 0x3 ; CHECK-NEXT: .long 3 @ 0x3
; CHECK-NEXT: .LCPI2_0: ; CHECK-NEXT: .LCPI2_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
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llvm/test/CodeGen/Thumb2/mve-div-expand.ll

Show First 20 Lines • Show All 800 Lines • ▼ Show 20 Linesentry:
%out = frem <4 x float> %in1, %in2 %out = frem <4 x float> %in1, %in2
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) { define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-LABEL: fdiv_f16: ; CHECK-LABEL: fdiv_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdiv.f16 s8, s0, s4
; CHECK-NEXT: vmovx.f16 s10, s0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vdiv.f16 s8, s10, s8 ; CHECK-NEXT: vmovx.f16 s10, s0
; CHECK-NEXT: vdiv.f16 s12, s1, s5 ; CHECK-NEXT: vdiv.f16 s12, s10, s8
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vdiv.f16 s8, s0, s4
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vins.f16 s8, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmovx.f16 s14, s1 ; CHECK-NEXT: vmovx.f16 s14, s1
; CHECK-NEXT: vmov.16 q2[1], r1 ; CHECK-NEXT: vdiv.f16 s9, s1, s5
; CHECK-NEXT: vdiv.f16 s12, s14, s12 ; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vdiv.f16 s12, s2, s6
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s6
; CHECK-NEXT: vmovx.f16 s14, s2 ; CHECK-NEXT: vmovx.f16 s14, s2
; CHECK-NEXT: vins.f16 s9, s12
; CHECK-NEXT: vmovx.f16 s12, s6
; CHECK-NEXT: vdiv.f16 s12, s14, s12 ; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vdiv.f16 s10, s2, s6
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vdiv.f16 s12, s3, s7 ; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmovx.f16 s4, s7 ; CHECK-NEXT: vmovx.f16 s14, s3
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vdiv.f16 s11, s3, s7
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vins.f16 s11, s12
; CHECK-NEXT: vdiv.f16 s0, s0, s4
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fdiv <8 x half> %in1, %in2 %out = fdiv <8 x half> %in1, %in2
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) { define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
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llvm/test/CodeGen/Thumb2/mve-fmas.ll

Show All 11 Lines
; ;
; CHECK-MVE-VMLA-LABEL: vfma16_v1: ; CHECK-MVE-VMLA-LABEL: vfma16_v1:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v1: ; CHECK-MVE-LABEL: vfma16_v1:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s2
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s3
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s11
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s9
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10
; CHECK-MVE-NEXT: vins.f16 s1, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vins.f16 s3, s13
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
; CHECK-MVE-FP-LABEL: vfma16_v2: ; CHECK-MVE-FP-LABEL: vfma16_v2:
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q0 ; CHECK-MVE-FP-NEXT: vadd.f16 q0, q1, q0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma16_v2: ; CHECK-MVE-VMLA-LABEL: vfma16_v2:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v2: ; CHECK-MVE-LABEL: vfma16_v2:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s2
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmla.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s3
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s11
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s9
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10
; CHECK-MVE-NEXT: vins.f16 s1, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vins.f16 s3, s13
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1 %1 = fadd <8 x half> %0, %src1
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
; CHECK-MVE-FP-LABEL: vfms16: ; CHECK-MVE-FP-LABEL: vfms16:
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, q2
; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vsub.f16 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfms16: ; CHECK-MVE-VMLA-LABEL: vfms16:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfms.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms16: ; CHECK-MVE-LABEL: vfms16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10}
; CHECK-MVE-NEXT: vpush {d8, d9, d10}
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-MVE-NEXT: vmls.f16 s16, s5, s9
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s2
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmls.f16 s16, s6, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmls.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmov.f32 s16, s3
; CHECK-MVE-NEXT: vmov r0, s20
; CHECK-MVE-NEXT: vmls.f16 s16, s7, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s11
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: vmov r0, s16
; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s9
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmls.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10
; CHECK-MVE-NEXT: vins.f16 s1, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vmls.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmls.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vins.f16 s3, s13
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0 %1 = fsub <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfmar16(<8 x half> %src1, <8 x half> %src2, float %src3o) { define arm_aapcs_vfpcc <8 x half> @vfmar16(<8 x half> %src1, <8 x half> %src2, float %src3o) {
Show All 9 Lines
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16: ; CHECK-MVE-LABEL: vfmar16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vmov.f32 s8, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmov.f32 s14, s1 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s5
; CHECK-MVE-NEXT: vmovx.f16 s10, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmla.f16 s14, s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmla.f16 s10, s8, s12 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmla.f16 s1, s5, s8
; CHECK-MVE-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vins.f16 s1, s12
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmovx.f16 s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmla.f16 s2, s6, s8
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s10, s7
; CHECK-MVE-NEXT: vmov.f32 s14, s2 ; CHECK-MVE-NEXT: vins.f16 s2, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmov r0, s13 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s14, s6, s12 ; CHECK-MVE-NEXT: vmla.f16 s3, s7, s8
; CHECK-MVE-NEXT: vmov.16 q2[3], r0 ; CHECK-MVE-NEXT: vins.f16 s3, s12
; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmov.16 q2[4], r0
; CHECK-MVE-NEXT: vmov r0, s13
; CHECK-MVE-NEXT: vmla.f16 s14, s7, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s12
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src2, %sp %0 = fmul <8 x half> %src2, %sp
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
Show All 12 Lines
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16: ; CHECK-MVE-LABEL: vfma16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vmov q3, q0
; CHECK-MVE-NEXT: vmovx.f16 s10, s0 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s8
; CHECK-MVE-NEXT: vmov.f32 s8, s12 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4 ; CHECK-MVE-NEXT: vmov.f32 s0, s3
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s9, s12
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmla.f16 s8, s9, s10
; CHECK-MVE-NEXT: vmovx.f16 s8, s4 ; CHECK-MVE-NEXT: vmla.f16 s0, s12, s4
; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vmov.f32 s9, s3
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov.f32 s1, s3
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s10, s13
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vmla.f16 s1, s13, s5
; CHECK-MVE-NEXT: vmla.f16 s14, s1, s5 ; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vins.f16 s1, s9
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmov.f32 s9, s3
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmov.f32 s2, s3
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s10, s14
; CHECK-MVE-NEXT: vmov.16 q2[2], r0 ; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8
; CHECK-MVE-NEXT: vmov r0, s15 ; CHECK-MVE-NEXT: vmla.f16 s2, s14, s6
; CHECK-MVE-NEXT: vmla.f16 s14, s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s9
; CHECK-MVE-NEXT: vmov.16 q2[3], r0 ; CHECK-MVE-NEXT: vmov.f32 s9, s3
; CHECK-MVE-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s10, s15
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s12 ; CHECK-MVE-NEXT: vmla.f16 s3, s15, s7
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vins.f16 s3, s9
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0
; CHECK-MVE-NEXT: vmov r0, s15
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmla.f16 s14, s3, s7
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src1, %src2 %0 = fmul <8 x half> %src1, %src2
%1 = fadd <8 x half> %sp, %0 %1 = fadd <8 x half> %sp, %0
ret <8 x half> %1 ret <8 x half> %1
▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v1_pred: ; CHECK-MVE-LABEL: vfma16_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9 ; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vseleq.f16 s16, s1, s16 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmov.16 q3[1], r2
; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s2 ; CHECK-MVE-NEXT: vmov.f32 s18, s1
; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s2, s16 ; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s3 ; CHECK-MVE-NEXT: vmov.f32 s18, s2
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s16, s3, s16 ; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s11 ; CHECK-MVE-NEXT: vmov.f32 s18, s3
; CHECK-MVE-NEXT: vmov.f32 s2, s0 ; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmla.f16 s2, s4, s8 ; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s2
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
Show All 13 Lines
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v2_pred: ; CHECK-MVE-LABEL: vfma16_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s16, s5, s9 ; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vseleq.f16 s16, s1, s16 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmov.16 q3[1], r2
; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s2 ; CHECK-MVE-NEXT: vmov.f32 s18, s1
; CHECK-MVE-NEXT: vmla.f16 s16, s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s2, s16 ; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s3 ; CHECK-MVE-NEXT: vmov.f32 s18, s2
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmla.f16 s16, s7, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s16, s3, s16 ; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s11 ; CHECK-MVE-NEXT: vmov.f32 s18, s3
; CHECK-MVE-NEXT: vmov.f32 s2, s0 ; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmla.f16 s2, s4, s8 ; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s2
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1 %1 = fadd <8 x half> %0, %src1
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
Show All 13 Lines
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms16_pred: ; CHECK-MVE-LABEL: vfms16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmls.f16 s12, s4, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmov.16 q3[0], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s16, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmls.f16 s16, s5, s9 ; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: vseleq.f16 s16, s1, s16 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmov.16 q3[1], r2
; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmovx.f16 s16, s9
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s2 ; CHECK-MVE-NEXT: vmov.f32 s18, s1
; CHECK-MVE-NEXT: vmls.f16 s16, s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s2, s16 ; CHECK-MVE-NEXT: vmls.f16 s18, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s20, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s16, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s16, s3 ; CHECK-MVE-NEXT: vmov.f32 s18, s2
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmls.f16 s16, s7, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmls.f16 s18, s6, s10
; CHECK-MVE-NEXT: vseleq.f16 s16, s3, s16 ; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s11 ; CHECK-MVE-NEXT: vmov.f32 s18, s3
; CHECK-MVE-NEXT: vmov.f32 s2, s0 ; CHECK-MVE-NEXT: vmls.f16 s18, s7, s11
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmls.f16 s2, s4, s8 ; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s2
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0 %1 = fsub <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
Show All 16 Lines
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16_pred: ; CHECK-MVE-LABEL: vfmar16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s8, s0
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmovx.f16 s10, s0 ; CHECK-MVE-NEXT: vmovx.f16 s10, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s10 ; CHECK-MVE-NEXT: vmov.f32 s14, s10
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s12 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s14
; CHECK-MVE-NEXT: vseleq.f16 s8, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vmov.16 q2[0], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s14, s5, s12 ; CHECK-MVE-NEXT: vmov.f32 s8, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmov.16 q2[1], r2 ; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12
; CHECK-MVE-NEXT: vseleq.f16 s14, s1, s14 ; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vins.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmov.16 q2[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q2[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s14, s2 ; CHECK-MVE-NEXT: vmla.f16 s13, s5, s12
; CHECK-MVE-NEXT: vmla.f16 s14, s6, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s14 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s9, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmov.16 q2[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q2[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s14, s3 ; CHECK-MVE-NEXT: vmla.f16 s13, s6, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmla.f16 s14, s7, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: vseleq.f16 s14, s3, s14 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vins.f16 s10, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.f32 s2, s0 ; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: vmla.f16 s2, s4, s12 ; CHECK-MVE-NEXT: vmla.f16 s13, s7, s12
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s13
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s2 ; CHECK-MVE-NEXT: vins.f16 s11, s14
; CHECK-MVE-NEXT: vmov.16 q2[6], r1
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src2, %sp %0 = fmul <8 x half> %src2, %sp
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
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; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_pred: ; CHECK-MVE-LABEL: vfma16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vcmp.f16 s10, #0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s8, s12 ; CHECK-MVE-NEXT: vmov.f32 s8, s12
; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8 ; CHECK-MVE-NEXT: vmla.f16 s8, s14, s10
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vseleq.f16 s14, s14, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmovx.f16 s10, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s8, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vmov.16 q2[0], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s14, s1, s5 ; CHECK-MVE-NEXT: vmov.f32 s8, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmov.16 q2[1], r2 ; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4
; CHECK-MVE-NEXT: vseleq.f16 s14, s1, s14 ; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vins.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmov.16 q2[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s12 ; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q2[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s13, s1, s5
; CHECK-MVE-NEXT: vmla.f16 s14, s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s14 ; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s9, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmov.16 q2[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s13, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q2[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s13, s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmla.f16 s14, s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: vseleq.f16 s14, s3, s14 ; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s10, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s12
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12 ; CHECK-MVE-NEXT: vins.f16 s11, s14
; CHECK-MVE-NEXT: vmov.16 q2[6], r1
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src1, %src2 %0 = fmul <8 x half> %src1, %src2
%1 = fadd <8 x half> %sp, %0 %1 = fadd <8 x half> %sp, %0
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llvm/test/CodeGen/Thumb2/mve-fmath.ll

Show All 13 Lines
entry: entry:
%0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {
; CHECK-LABEL: sqrt_float16_t: ; CHECK-LABEL: sqrt_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vsqrt.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vsqrt.f16 s4, s4 ; CHECK-NEXT: vsqrt.f16 s8, s0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vsqrt.f16 s0, s4
; CHECK-NEXT: vsqrt.f16 s4, s0 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vsqrt.f16 s0, s0
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vsqrt.f16 s8, s8 ; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vsqrt.f16 s1, s5
; CHECK-NEXT: vsqrt.f16 s8, s2 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vsqrt.f16 s8, s8 ; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vsqrt.f16 s2, s6
; CHECK-NEXT: vsqrt.f16 s8, s3 ; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmovx.f16 s8, s7
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vsqrt.f16 s8, s8
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vsqrt.f16 s3, s7
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @sqrt_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @sqrt_float64_t(<2 x double> %src) {
; CHECK-LABEL: sqrt_float64_t: ; CHECK-LABEL: sqrt_float64_t:
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} }
define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: copysign_float16_t: ; CHECK-LABEL: copysign_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vstr.16 s4, [sp, #28]
; CHECK-NEXT: vstr.16 s8, [sp, #24] ; CHECK-NEXT: vstr.16 s8, [sp, #24]
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vstr.16 s5, [sp, #20] ; CHECK-NEXT: vstr.16 s4, [sp, #28]
; CHECK-NEXT: vstr.16 s8, [sp, #16] ; CHECK-NEXT: vstr.16 s8, [sp, #16]
; CHECK-NEXT: vmovx.f16 s8, s6 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmovx.f16 s4, s7 ; CHECK-NEXT: vstr.16 s5, [sp, #20]
; CHECK-NEXT: vstr.16 s6, [sp, #12]
; CHECK-NEXT: vstr.16 s8, [sp, #8] ; CHECK-NEXT: vstr.16 s8, [sp, #8]
; CHECK-NEXT: vmovx.f16 s8, s7
; CHECK-NEXT: vstr.16 s6, [sp, #12]
; CHECK-NEXT: vstr.16 s8, [sp]
; CHECK-NEXT: vstr.16 s7, [sp, #4] ; CHECK-NEXT: vstr.16 s7, [sp, #4]
; CHECK-NEXT: vstr.16 s4, [sp] ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: ldrb.w r0, [sp, #29] ; CHECK-NEXT: ldrb.w r0, [sp, #25]
; CHECK-NEXT: vabs.f16 s4, s0 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: ldrb.w r1, [sp, #25]
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s1
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: ldrb.w r0, [sp, #29]
; CHECK-NEXT: tst.w r1, #128 ; CHECK-NEXT: vseleq.f16 s8, s4, s6
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vabs.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vabs.f16 s0, s3
; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: ldrb.w r0, [sp, #21]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: ldrb.w r0, [sp, #17] ; CHECK-NEXT: ldrb.w r0, [sp, #17]
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: ldrb.w r0, [sp, #21]
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vabs.f16 s10, s1
; CHECK-NEXT: vabs.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s12, s10
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: ldrb.w r0, [sp, #9] ; CHECK-NEXT: ldrb.w r0, [sp, #9]
; CHECK-NEXT: vseleq.f16 s5, s10, s12
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vabs.f16 s10, s2
; CHECK-NEXT: vneg.f16 s2, s0 ; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s12, s10
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vseleq.f16 s6, s10, s12
; CHECK-NEXT: vabs.f16 s8, s3 ; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmovx.f16 s8, s3
; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s0, s0, s2 ; CHECK-NEXT: vseleq.f16 s7, s0, s2
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s7, s8
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2) %0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0 ret <8 x half> %0
} }
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llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fneg_float16_t: ; CHECK-MVE-LABEL: fneg_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vneg.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vneg.f16 s4, s4 ; CHECK-MVE-NEXT: vneg.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vneg.f16 s0, s4
; CHECK-MVE-NEXT: vneg.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vneg.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vneg.f16 s8, s8 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vneg.f16 s1, s5
; CHECK-MVE-NEXT: vneg.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vneg.f16 s8, s8 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vneg.f16 s2, s6
; CHECK-MVE-NEXT: vneg.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vneg.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vneg.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fneg_float16_t: ; CHECK-MVEFP-LABEL: fneg_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vneg.f16 q0, q0 ; CHECK-MVEFP-NEXT: vneg.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
Show All 39 Lines
entry: entry:
%0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fabs_float16_t: ; CHECK-MVE-LABEL: fabs_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vabs.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vabs.f16 s4, s4 ; CHECK-MVE-NEXT: vabs.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vabs.f16 s0, s4
; CHECK-MVE-NEXT: vabs.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vabs.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vabs.f16 s8, s8 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vabs.f16 s1, s5
; CHECK-MVE-NEXT: vabs.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vabs.f16 s8, s8 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vabs.f16 s2, s6
; CHECK-MVE-NEXT: vabs.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vabs.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vabs.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fabs_float16_t: ; CHECK-MVEFP-LABEL: fabs_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vabs.f16 q0, q0 ; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src) %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
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llvm/test/CodeGen/Thumb2/mve-frint.ll

Show All 18 Lines
entry: entry:
%0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fceil_float16_t: ; CHECK-MVE-LABEL: fceil_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vrintp.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vrintp.f16 s4, s4 ; CHECK-MVE-NEXT: vrintp.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vrintp.f16 s0, s4
; CHECK-MVE-NEXT: vrintp.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vrintp.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vrintp.f16 s8, s8 ; CHECK-MVE-NEXT: vrintp.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintp.f16 s1, s5
; CHECK-MVE-NEXT: vrintp.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vrintp.f16 s8, s8 ; CHECK-MVE-NEXT: vrintp.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintp.f16 s2, s6
; CHECK-MVE-NEXT: vrintp.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintp.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vrintp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fceil_float16_t: ; CHECK-MVEFP-LABEL: fceil_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintp.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintp.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: ftrunc_float16_t: ; CHECK-MVE-LABEL: ftrunc_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vrintz.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vrintz.f16 s4, s4 ; CHECK-MVE-NEXT: vrintz.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vrintz.f16 s0, s4
; CHECK-MVE-NEXT: vrintz.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vrintz.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vrintz.f16 s8, s8 ; CHECK-MVE-NEXT: vrintz.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintz.f16 s1, s5
; CHECK-MVE-NEXT: vrintz.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vrintz.f16 s8, s8 ; CHECK-MVE-NEXT: vrintz.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintz.f16 s2, s6
; CHECK-MVE-NEXT: vrintz.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintz.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vrintz.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ftrunc_float16_t: ; CHECK-MVEFP-LABEL: ftrunc_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintz.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintz.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: frint_float16_t: ; CHECK-MVE-LABEL: frint_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vrintx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vrintx.f16 s4, s4 ; CHECK-MVE-NEXT: vrintx.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vrintx.f16 s0, s4
; CHECK-MVE-NEXT: vrintx.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vrintx.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vrintx.f16 s8, s8 ; CHECK-MVE-NEXT: vrintx.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintx.f16 s1, s5
; CHECK-MVE-NEXT: vrintx.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vrintx.f16 s8, s8 ; CHECK-MVE-NEXT: vrintx.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintx.f16 s2, s6
; CHECK-MVE-NEXT: vrintx.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintx.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vrintx.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: frint_float16_t: ; CHECK-MVEFP-LABEL: frint_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintx.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintx.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) {
; CHECK-LABEL: fnearbyint_float16_t: ; CHECK-LABEL: fnearbyint_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vrintr.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vrintr.f16 s4, s4 ; CHECK-NEXT: vrintr.f16 s8, s0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vrintr.f16 s0, s4
; CHECK-NEXT: vrintr.f16 s4, s0 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vrintr.f16 s0, s0
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vrintr.f16 s8, s8 ; CHECK-NEXT: vrintr.f16 s8, s8
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vrintr.f16 s1, s5
; CHECK-NEXT: vrintr.f16 s8, s2 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vrintr.f16 s8, s8 ; CHECK-NEXT: vrintr.f16 s8, s8
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vrintr.f16 s2, s6
; CHECK-NEXT: vrintr.f16 s8, s3 ; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmovx.f16 s8, s7
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vrintr.f16 s8, s8
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vrintr.f16 s3, s7
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) {
; CHECK-LABEL: fnearbyint_float64_t: ; CHECK-LABEL: fnearbyint_float64_t:
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entry: entry:
%0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: ffloor_float16_t: ; CHECK-MVE-LABEL: ffloor_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vrintm.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vrintm.f16 s4, s4 ; CHECK-MVE-NEXT: vrintm.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vrintm.f16 s0, s4
; CHECK-MVE-NEXT: vrintm.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vrintm.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vrintm.f16 s8, s8 ; CHECK-MVE-NEXT: vrintm.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintm.f16 s1, s5
; CHECK-MVE-NEXT: vrintm.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vrintm.f16 s8, s8 ; CHECK-MVE-NEXT: vrintm.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintm.f16 s2, s6
; CHECK-MVE-NEXT: vrintm.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrintm.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vrintm.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ffloor_float16_t: ; CHECK-MVEFP-LABEL: ffloor_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintm.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintm.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fround_float16_t: ; CHECK-MVE-LABEL: fround_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vrinta.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vrinta.f16 s4, s4 ; CHECK-MVE-NEXT: vrinta.f16 s8, s0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vrinta.f16 s0, s4
; CHECK-MVE-NEXT: vrinta.f16 s4, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q1[0], r1
; CHECK-MVE-NEXT: vrinta.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q1[1], r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vrinta.f16 s8, s8 ; CHECK-MVE-NEXT: vrinta.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrinta.f16 s1, s5
; CHECK-MVE-NEXT: vrinta.f16 s8, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vmov.16 q1[4], r0
; CHECK-MVE-NEXT: vrinta.f16 s8, s8 ; CHECK-MVE-NEXT: vrinta.f16 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrinta.f16 s2, s6
; CHECK-MVE-NEXT: vrinta.f16 s8, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s7
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vrinta.f16 s8, s8
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vrinta.f16 s3, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fround_float16_t: ; CHECK-MVEFP-LABEL: fround_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrinta.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrinta.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src)
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llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr) { define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr) {
; CHECK-LABEL: scaled_v8f16_sext: ; CHECK-LABEL: scaled_v8f16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r1]
; CHECK-NEXT: vshl.i32 q0, q0, #1 ; CHECK-NEXT: vshl.i32 q0, q0, #1
; CHECK-NEXT: vadd.i32 q1, q0, r0 ; CHECK-NEXT: vadd.i32 q1, q0, r0
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vldr.16 s0, [r3]
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vldr.16 s8, [r2] ; CHECK-NEXT: vldr.16 s8, [r2]
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vldr.16 s4, [r2]
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldr.16 s8, [r2]
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vmov.16 q0[3], r2 ; CHECK-NEXT: vldr.16 s1, [r2]
; CHECK-NEXT: vshl.i32 q1, q1, #1 ; CHECK-NEXT: vshl.i32 q1, q1, #1
; CHECK-NEXT: vadd.i32 q1, q1, r0 ; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vldr.16 s8, [r0] ; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vldr.16 s4, [r0]
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vldr.16 s3, [r0]
; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x i16>, <8 x i16>* %offptr, align 2 %offs = load <8 x i16>, <8 x i16>* %offptr, align 2
%offs.sext = sext <8 x i16> %offs to <8 x i32> %offs.sext = sext <8 x i16> %offs to <8 x i32>
%i16_ptrs = getelementptr inbounds i16, i16* %base, <8 x i32> %offs.sext %i16_ptrs = getelementptr inbounds i16, i16* %base, <8 x i32> %offs.sext
%ptrs = bitcast <8 x i16*> %i16_ptrs to <8 x half*> %ptrs = bitcast <8 x i16*> %i16_ptrs to <8 x half*>
%gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef) %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)
ret <8 x half> %gather ret <8 x half> %gather
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llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll

Show First 20 Lines • Show All 370 Lines • ▼ Show 20 Lines
; f16 ; f16
define arm_aapcs_vfpcc <8 x half> @ptr_f16(<8 x half*>* %offptr) { define arm_aapcs_vfpcc <8 x half> @ptr_f16(<8 x half*>* %offptr) {
; CHECK-LABEL: ptr_f16: ; CHECK-LABEL: ptr_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov r1, s5 ; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.16 q0[1], r1
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vldr.16 s8, [r1] ; CHECK-NEXT: vldr.16 s8, [r1]
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov.16 q0[2], r1
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldr.16 s8, [r1]
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.16 q0[3], r1 ; CHECK-NEXT: vldr.16 s1, [r1]
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vldr.16 s8, [r0] ; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vldr.16 s4, [r0]
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vldr.16 s8, [r0]
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vldr.16 s3, [r0]
; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x half*>, <8 x half*>* %offptr, align 4 %offs = load <8 x half*>, <8 x half*>* %offptr, align 4
%gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef) %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)
ret <8 x half> %gather ret <8 x half> %gather
} }
; i8 ; i8
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llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

Show First 20 Lines • Show All 817 Lines • ▼ Show 20 Lines
define void @foo_v4f32_v4f16(<4 x float> *%dest, <4 x i16> *%mask, <4 x half> *%src) { define void @foo_v4f32_v4f16(<4 x float> *%dest, <4 x i16> *%mask, <4 x half> *%src) {
; CHECK-LABEL: foo_v4f32_v4f16: ; CHECK-LABEL: foo_v4f32_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .pad #8 ; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vldrh.s32 q0, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r1]
; CHECK-NEXT: mov.w lr, #0
; CHECK-NEXT: @ implicit-def: $q1
; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: vcmp.s32 gt, q0, zr
; CHECK-NEXT: vmrs r3, p0 ; CHECK-NEXT: @ implicit-def: $q0
; CHECK-NEXT: and r1, r3, #1 ; CHECK-NEXT: vmrs lr, p0
; CHECK-NEXT: and r1, lr, #1
; CHECK-NEXT: ubfx r3, lr, #4, #1
; CHECK-NEXT: rsb.w r12, r1, #0 ; CHECK-NEXT: rsb.w r12, r1, #0
; CHECK-NEXT: ubfx r1, r3, #4, #1 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: bfi lr, r12, #0, #1 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: bfi r1, r12, #0, #1
; CHECK-NEXT: bfi lr, r1, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
; CHECK-NEXT: ubfx r1, r3, #8, #1 ; CHECK-NEXT: ubfx r3, lr, #8, #1
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi lr, r1, #2, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1
; CHECK-NEXT: ubfx r1, r3, #12, #1 ; CHECK-NEXT: ubfx r3, lr, #12, #1
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi lr, r1, #3, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1
; CHECK-NEXT: lsls.w r1, lr, #31 ; CHECK-NEXT: lsls r3, r1, #31
; CHECK-NEXT: beq .LBB18_2 ; CHECK-NEXT: bne .LBB18_6
; CHECK-NEXT: @ %bb.1: @ %cond.load ; CHECK-NEXT: @ %bb.1: @ %else
; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: lsls r3, r1, #30
; CHECK-NEXT: .LBB18_2: @ %else
; CHECK-NEXT: lsls.w r1, lr, #30
; CHECK-NEXT: bpl .LBB18_6
; CHECK-NEXT: @ %bb.3: @ %cond.load1
; CHECK-NEXT: vldr.16 s0, [r2, #2]
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vmov.16 q0[1], r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov.16 q0[2], r1
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: lsls.w r1, lr, #29
; CHECK-NEXT: bmi .LBB18_7 ; CHECK-NEXT: bmi .LBB18_7
; CHECK-NEXT: .LBB18_4: ; CHECK-NEXT: .LBB18_2: @ %else2
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: lsls r3, r1, #29
; CHECK-NEXT: lsls.w r1, lr, #28
; CHECK-NEXT: bmi .LBB18_8 ; CHECK-NEXT: bmi .LBB18_8
; CHECK-NEXT: .LBB18_5: ; CHECK-NEXT: .LBB18_3: @ %else5
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: b .LBB18_9
; CHECK-NEXT: .LBB18_6:
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: lsls.w r1, lr, #29
; CHECK-NEXT: bpl .LBB18_4
; CHECK-NEXT: .LBB18_7: @ %cond.load4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vldr.16 s8, [r2, #4]
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: lsls.w r1, lr, #28
; CHECK-NEXT: bpl .LBB18_5 ; CHECK-NEXT: bpl .LBB18_5
; CHECK-NEXT: .LBB18_8: @ %cond.load7 ; CHECK-NEXT: .LBB18_4: @ %cond.load7
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vldr.16 s4, [r2, #6]
; CHECK-NEXT: vmov.16 q2[0], r3 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vldr.16 s0, [r2, #6] ; CHECK-NEXT: .LBB18_5: @ %else8
; CHECK-NEXT: vmov.16 q2[1], r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q2[3], r1
; CHECK-NEXT: .LBB18_9: @ %else8
; CHECK-NEXT: vmrs r2, p0 ; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtt.f32.f16 s3, s9 ; CHECK-NEXT: vcvtt.f32.f16 s7, s1
; CHECK-NEXT: vcvtb.f32.f16 s2, s9 ; CHECK-NEXT: vcvtb.f32.f16 s6, s1
; CHECK-NEXT: vcvtt.f32.f16 s1, s8 ; CHECK-NEXT: vcvtt.f32.f16 s5, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s8 ; CHECK-NEXT: vcvtb.f32.f16 s4, s0
; CHECK-NEXT: and r3, r2, #1 ; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1
; CHECK-NEXT: ubfx r3, r2, #4, #1 ; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
; CHECK-NEXT: ubfx r3, r2, #8, #1 ; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: ubfx r2, r2, #12, #1 ; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #2, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1
; CHECK-NEXT: rsbs r2, r2, #0 ; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: bfi r1, r2, #3, #1 ; CHECK-NEXT: bfi r1, r2, #3, #1
; CHECK-NEXT: lsls r2, r1, #31 ; CHECK-NEXT: lsls r2, r1, #31
; CHECK-NEXT: itt ne ; CHECK-NEXT: itt ne
; CHECK-NEXT: vmovne r2, s0 ; CHECK-NEXT: vmovne r2, s4
; CHECK-NEXT: strne r2, [r0] ; CHECK-NEXT: strne r2, [r0]
; CHECK-NEXT: lsls r2, r1, #30 ; CHECK-NEXT: lsls r2, r1, #30
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r2, s1 ; CHECK-NEXT: vmovmi r2, s5
; CHECK-NEXT: strmi r2, [r0, #4] ; CHECK-NEXT: strmi r2, [r0, #4]
; CHECK-NEXT: lsls r2, r1, #29 ; CHECK-NEXT: lsls r2, r1, #29
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r2, s2 ; CHECK-NEXT: vmovmi r2, s6
; CHECK-NEXT: strmi r2, [r0, #8] ; CHECK-NEXT: strmi r2, [r0, #8]
; CHECK-NEXT: lsls r1, r1, #28 ; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r1, s3 ; CHECK-NEXT: vmovmi r1, s7
; CHECK-NEXT: strmi r1, [r0, #12] ; CHECK-NEXT: strmi r1, [r0, #12]
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .LBB18_6: @ %cond.load
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: lsls r3, r1, #30
; CHECK-NEXT: bpl .LBB18_2
; CHECK-NEXT: .LBB18_7: @ %cond.load1
; CHECK-NEXT: vldr.16 s4, [r2, #2]
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: lsls r3, r1, #29
; CHECK-NEXT: bpl .LBB18_3
; CHECK-NEXT: .LBB18_8: @ %cond.load4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vldr.16 s1, [r2, #4]
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: bmi .LBB18_4
; CHECK-NEXT: b .LBB18_5
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %mask, align 2 %0 = load <4 x i16>, <4 x i16>* %mask, align 2
%1 = icmp sgt <4 x i16> %0, zeroinitializer %1 = icmp sgt <4 x i16> %0, zeroinitializer
%2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef) %2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef)
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %3, <4 x float>* %dest, i32 2, <4 x i1> %1) call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %3, <4 x float>* %dest, i32 2, <4 x i1> %1)
ret void ret void
} }
define void @foo_v4f32_v4f16_unaligned(<4 x float> *%dest, <4 x i16> *%mask, <4 x half> *%src) { define void @foo_v4f32_v4f16_unaligned(<4 x float> *%dest, <4 x i16> *%mask, <4 x half> *%src) {
; CHECK-LABEL: foo_v4f32_v4f16_unaligned: ; CHECK-LABEL: foo_v4f32_v4f16_unaligned:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .pad #8 ; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vldrh.s32 q0, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r1]
; CHECK-NEXT: mov.w lr, #0
; CHECK-NEXT: @ implicit-def: $q1
; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: vcmp.s32 gt, q0, zr
; CHECK-NEXT: vmrs r3, p0 ; CHECK-NEXT: @ implicit-def: $q0
; CHECK-NEXT: and r1, r3, #1 ; CHECK-NEXT: vmrs lr, p0
; CHECK-NEXT: and r1, lr, #1
; CHECK-NEXT: ubfx r3, lr, #4, #1
; CHECK-NEXT: rsb.w r12, r1, #0 ; CHECK-NEXT: rsb.w r12, r1, #0
; CHECK-NEXT: ubfx r1, r3, #4, #1 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: bfi lr, r12, #0, #1 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: bfi r1, r12, #0, #1
; CHECK-NEXT: bfi lr, r1, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
; CHECK-NEXT: ubfx r1, r3, #8, #1 ; CHECK-NEXT: ubfx r3, lr, #8, #1
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi lr, r1, #2, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1
; CHECK-NEXT: ubfx r1, r3, #12, #1 ; CHECK-NEXT: ubfx r3, lr, #12, #1
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi lr, r1, #3, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1
; CHECK-NEXT: lsls.w r1, lr, #31 ; CHECK-NEXT: lsls r3, r1, #31
; CHECK-NEXT: beq .LBB19_2 ; CHECK-NEXT: bne .LBB19_6
; CHECK-NEXT: @ %bb.1: @ %cond.load ; CHECK-NEXT: @ %bb.1: @ %else
; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: lsls r3, r1, #30
; CHECK-NEXT: .LBB19_2: @ %else
; CHECK-NEXT: lsls.w r1, lr, #30
; CHECK-NEXT: bpl .LBB19_6
; CHECK-NEXT: @ %bb.3: @ %cond.load1
; CHECK-NEXT: vldr.16 s0, [r2, #2]
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vmov.16 q0[1], r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov.16 q0[2], r1
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: lsls.w r1, lr, #29
; CHECK-NEXT: bmi .LBB19_7 ; CHECK-NEXT: bmi .LBB19_7
; CHECK-NEXT: .LBB19_4: ; CHECK-NEXT: .LBB19_2: @ %else2
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: lsls r3, r1, #29
; CHECK-NEXT: lsls.w r1, lr, #28
; CHECK-NEXT: bmi .LBB19_8 ; CHECK-NEXT: bmi .LBB19_8
; CHECK-NEXT: .LBB19_5: ; CHECK-NEXT: .LBB19_3: @ %else5
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: b .LBB19_9
; CHECK-NEXT: .LBB19_6:
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: lsls.w r1, lr, #29
; CHECK-NEXT: bpl .LBB19_4
; CHECK-NEXT: .LBB19_7: @ %cond.load4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vldr.16 s8, [r2, #4]
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.16 q1[0], r1
; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov.16 q1[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q1[3], r1
; CHECK-NEXT: lsls.w r1, lr, #28
; CHECK-NEXT: bpl .LBB19_5 ; CHECK-NEXT: bpl .LBB19_5
; CHECK-NEXT: .LBB19_8: @ %cond.load7 ; CHECK-NEXT: .LBB19_4: @ %cond.load7
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vldr.16 s4, [r2, #6]
; CHECK-NEXT: vmov.16 q2[0], r3 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vldr.16 s0, [r2, #6] ; CHECK-NEXT: .LBB19_5: @ %else8
; CHECK-NEXT: vmov.16 q2[1], r1
; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov.16 q2[2], r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov.16 q2[3], r1
; CHECK-NEXT: .LBB19_9: @ %else8
; CHECK-NEXT: vmrs r2, p0 ; CHECK-NEXT: vmrs r2, p0
; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vcvtt.f32.f16 s3, s9 ; CHECK-NEXT: vcvtt.f32.f16 s7, s1
; CHECK-NEXT: vcvtb.f32.f16 s2, s9 ; CHECK-NEXT: vcvtb.f32.f16 s6, s1
; CHECK-NEXT: vcvtt.f32.f16 s1, s8 ; CHECK-NEXT: vcvtt.f32.f16 s5, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s8 ; CHECK-NEXT: vcvtb.f32.f16 s4, s0
; CHECK-NEXT: and r3, r2, #1 ; CHECK-NEXT: and r3, r2, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1
; CHECK-NEXT: ubfx r3, r2, #4, #1 ; CHECK-NEXT: ubfx r3, r2, #4, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #1, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1
; CHECK-NEXT: ubfx r3, r2, #8, #1 ; CHECK-NEXT: ubfx r3, r2, #8, #1
; CHECK-NEXT: ubfx r2, r2, #12, #1 ; CHECK-NEXT: ubfx r2, r2, #12, #1
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r1, r3, #2, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1
; CHECK-NEXT: rsbs r2, r2, #0 ; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: bfi r1, r2, #3, #1 ; CHECK-NEXT: bfi r1, r2, #3, #1
; CHECK-NEXT: lsls r2, r1, #31 ; CHECK-NEXT: lsls r2, r1, #31
; CHECK-NEXT: itt ne ; CHECK-NEXT: itt ne
; CHECK-NEXT: vmovne r2, s0 ; CHECK-NEXT: vmovne r2, s4
; CHECK-NEXT: strne r2, [r0] ; CHECK-NEXT: strne r2, [r0]
; CHECK-NEXT: lsls r2, r1, #30 ; CHECK-NEXT: lsls r2, r1, #30
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r2, s1 ; CHECK-NEXT: vmovmi r2, s5
; CHECK-NEXT: strmi r2, [r0, #4] ; CHECK-NEXT: strmi r2, [r0, #4]
; CHECK-NEXT: lsls r2, r1, #29 ; CHECK-NEXT: lsls r2, r1, #29
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r2, s2 ; CHECK-NEXT: vmovmi r2, s6
; CHECK-NEXT: strmi r2, [r0, #8] ; CHECK-NEXT: strmi r2, [r0, #8]
; CHECK-NEXT: lsls r1, r1, #28 ; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: itt mi ; CHECK-NEXT: itt mi
; CHECK-NEXT: vmovmi r1, s3 ; CHECK-NEXT: vmovmi r1, s7
; CHECK-NEXT: strmi r1, [r0, #12] ; CHECK-NEXT: strmi r1, [r0, #12]
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .LBB19_6: @ %cond.load
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: lsls r3, r1, #30
; CHECK-NEXT: bpl .LBB19_2
; CHECK-NEXT: .LBB19_7: @ %cond.load1
; CHECK-NEXT: vldr.16 s4, [r2, #2]
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: lsls r3, r1, #29
; CHECK-NEXT: bpl .LBB19_3
; CHECK-NEXT: .LBB19_8: @ %cond.load4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vldr.16 s1, [r2, #4]
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: lsls r1, r1, #28
; CHECK-NEXT: bmi .LBB19_4
; CHECK-NEXT: b .LBB19_5
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %mask, align 2 %0 = load <4 x i16>, <4 x i16>* %mask, align 2
%1 = icmp sgt <4 x i16> %0, zeroinitializer %1 = icmp sgt <4 x i16> %0, zeroinitializer
%2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef) %2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef)
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %3, <4 x float>* %dest, i32 1, <4 x i1> %1) call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %3, <4 x float>* %dest, i32 1, <4 x i1> %1)
ret void ret void
} }
Show All 21 Lines

llvm/test/CodeGen/Thumb2/mve-minmax.ll

Show First 20 Lines • Show All 309 Lines • ▼ Show 20 Linesentry:
%cmp = fcmp fast ogt <4 x float> %src2, %src1 %cmp = fcmp fast ogt <4 x float> %src2, %src1
%0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1 %0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: minnm_float16_t: ; CHECK-MVE-LABEL: minnm_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vminnm.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vminnm.f16 s8, s10, s8 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vminnm.f16 s12, s5, s1 ; CHECK-MVE-NEXT: vminnm.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vminnm.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vins.f16 s8, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vminnm.f16 s9, s5, s1
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vminnm.f16 s12, s6, s2
; CHECK-MVE-NEXT: vmov.16 q2[3], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vins.f16 s9, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vminnm.f16 s10, s6, s2
; CHECK-MVE-NEXT: vins.f16 s10, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vminnm.f16 s11, s7, s3
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0 ; CHECK-MVE-NEXT: vins.f16 s11, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmovx.f16 s2, s7
; CHECK-MVE-NEXT: vminnm.f16 s12, s7, s3
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vminnm.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: minnm_float16_t: ; CHECK-MVEFP-LABEL: minnm_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
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llvm/test/CodeGen/Thumb2/mve-shuffle.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 3> %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 3>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle1_i16: ; CHECK-LABEL: shuffle1_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmov.u16 r0, q0[7] ; CHECK-NEXT: vins.f16 s4, s3
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vins.f16 s5, s2
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vins.f16 s6, s1
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmovx.f16 s7, s0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle2_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle2_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle2_i16: ; CHECK-LABEL: shuffle2_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle3_i16: ; CHECK-LABEL: shuffle3_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s5, s3
; CHECK-NEXT: vmov.u16 r0, q0[7] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vins.f16 s5, s3
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle5_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle5_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle5_i16: ; CHECK-LABEL: shuffle5_i16:
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle1_f16: ; CHECK-LABEL: shuffle1_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s3 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vmov.16 q1[0], r1 ; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmov.16 q1[1], r0 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle2_f16: ; CHECK-LABEL: shuffle2_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle3_f16: ; CHECK-LABEL: shuffle3_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s3 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmovx.f16 s1, s7
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: vmov.16 q1[2], r1 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vins.f16 s5, s4
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle5_f16: ; CHECK-LABEL: shuffle5_f16:
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-shufflemov.ll

Show All 29 Lines
entry: entry:
%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1> %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) { define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: shuffle_i16_76543210: ; CHECK-LABEL: shuffle_i16_76543210:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmov.u16 r0, q0[7] ; CHECK-NEXT: vins.f16 s4, s3
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vins.f16 s5, s2
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vins.f16 s6, s1
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmovx.f16 s7, s0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_01234567(<8 x i16> %s1, <8 x i16> %s2) { define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_01234567(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: shuffle_i16_01234567: ; CHECK-LABEL: shuffle_i16_01234567:
▲ Show 20 Lines • Show All 278 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1> %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) { define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) {
; CHECK-LABEL: shuffle_f16_76543210: ; CHECK-LABEL: shuffle_f16_76543210:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s3 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vmov.16 q1[0], r1 ; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmov.16 q1[1], r0 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_01234567(<8 x half> %s1, <8 x half> %s2) { define arm_aapcs_vfpcc <8 x half> @shuffle_f16_01234567(<8 x half> %s1, <8 x half> %s2) {
; CHECK-LABEL: shuffle_f16_01234567: ; CHECK-LABEL: shuffle_f16_01234567:
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llvm/test/CodeGen/Thumb2/mve-simple-arith.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
entry: entry:
%0 = fadd nnan ninf nsz <4 x float> %src2, %src1 %0 = fadd nnan ninf nsz <4 x float> %src2, %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: add_float16_t: ; CHECK-MVE-LABEL: add_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vadd.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vadd.f16 s8, s10, s8 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vadd.f16 s12, s5, s1 ; CHECK-MVE-NEXT: vadd.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vadd.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vins.f16 s8, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vadd.f16 s9, s5, s1
; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vadd.f16 s12, s6, s2
; CHECK-MVE-NEXT: vmov.16 q2[3], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vins.f16 s9, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0 ; CHECK-MVE-NEXT: vadd.f16 s10, s6, s2
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vins.f16 s10, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmovx.f16 s2, s7 ; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vadd.f16 s12, s7, s3 ; CHECK-MVE-NEXT: vadd.f16 s11, s7, s3
; CHECK-MVE-NEXT: vmov.16 q2[5], r0 ; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vins.f16 s11, s12
; CHECK-MVE-NEXT: vadd.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: add_float16_t: ; CHECK-MVEFP-LABEL: add_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vadd.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vadd.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
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entry: entry:
%0 = fsub nnan ninf nsz <4 x float> %src2, %src1 %0 = fsub nnan ninf nsz <4 x float> %src2, %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: sub_float16_t: ; CHECK-MVE-LABEL: sub_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vsub.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vsub.f16 s8, s10, s8 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vsub.f16 s12, s5, s1 ; CHECK-MVE-NEXT: vsub.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vsub.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vins.f16 s8, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vsub.f16 s9, s5, s1
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vsub.f16 s12, s6, s2
; CHECK-MVE-NEXT: vmov.16 q2[3], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vins.f16 s9, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12
; CHECK-MVE-NEXT: vsub.f16 s10, s6, s2
; CHECK-MVE-NEXT: vins.f16 s10, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vsub.f16 s11, s7, s3
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0 ; CHECK-MVE-NEXT: vins.f16 s11, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmovx.f16 s2, s7
; CHECK-MVE-NEXT: vsub.f16 s12, s7, s3
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vsub.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: sub_float16_t: ; CHECK-MVEFP-LABEL: sub_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vsub.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vsub.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
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entry: entry:
%0 = mul nsw <2 x i64> %src1, %src2 %0 = mul nsw <2 x i64> %src1, %src2
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: mul_float16_t: ; CHECK-MVE-LABEL: mul_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmul.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vmul.f16 s8, s10, s8 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmul.f16 s12, s5, s1 ; CHECK-MVE-NEXT: vmul.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vmul.f16 s8, s4, s0
; CHECK-MVE-NEXT: vmov.16 q2[0], r0 ; CHECK-MVE-NEXT: vins.f16 s8, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vmov.16 q2[1], r1 ; CHECK-MVE-NEXT: vmul.f16 s9, s5, s1
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[2], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmul.f16 s12, s6, s2
; CHECK-MVE-NEXT: vmov.16 q2[3], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s14, s6
; CHECK-MVE-NEXT: vins.f16 s9, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmul.f16 s10, s6, s2
; CHECK-MVE-NEXT: vins.f16 s10, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmul.f16 s11, s7, s3
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmov.16 q2[4], r0 ; CHECK-MVE-NEXT: vins.f16 s11, s12
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmovx.f16 s2, s7
; CHECK-MVE-NEXT: vmul.f16 s12, s7, s3
; CHECK-MVE-NEXT: vmov.16 q2[5], r0
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: vmul.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov.16 q2[6], r0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q2[7], r0
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: mul_float16_t: ; CHECK-MVEFP-LABEL: mul_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmul.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vmul.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
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llvm/test/CodeGen/Thumb2/mve-vcmpf.ll

Show First 20 Lines • Show All 763 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 15 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 15 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vins.f16 s17, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s3
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s20
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> %src, %src2 %c = fcmp uno <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll

Show First 20 Lines • Show All 805 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
Show All 18 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
Show All 18 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
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; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
Show All 18 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
Show All 18 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
Show All 16 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
Show All 18 Lines
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s13
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s16, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s6, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s17, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s15
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s18, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vseleq.f16 s6, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s19, s6
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
Show All 11 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

Show First 20 Lines • Show All 763 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
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; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
▲ Show 20 Lines • Show All 770 Lines • ▼ Show 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 15 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
Show All 12 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
Show All 13 Lines
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s13, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s14, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s3
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s15, s16
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> zeroinitializer, %src %c = fcmp uno <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcvt.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
entry: entry:
%out = fptoui <4 x float> %src to <4 x i32> %out = fptoui <4 x float> %src to <4 x i32>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <8 x half> @foo_half_int16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x half> @foo_half_int16(<8 x i16> %src) {
; CHECK-MVE-LABEL: foo_half_int16: ; CHECK-MVE-LABEL: foo_half_int16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.s16 r0, q0[0] ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vmov.s16 r1, q0[1] ; CHECK-MVE-NEXT: vmov.s16 r0, q0[1]
; CHECK-MVE-NEXT: vmov s4, r0 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s4 ; CHECK-MVE-NEXT: vmov.s16 r0, q1[0]
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s0
; CHECK-MVE-NEXT: vmov s4, r1 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s4 ; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov.s16 r0, q1[3]
; CHECK-MVE-NEXT: vmov.16 q1[0], r0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov.s16 r0, q0[2]
; CHECK-MVE-NEXT: vmov.16 q1[1], r1
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vmov.s16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0
; CHECK-MVE-NEXT: vmov.s16 r0, q0[4]
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[2]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.16 q1[4], r0 ; CHECK-MVE-NEXT: vmov.s16 r0, q1[5]
; CHECK-MVE-NEXT: vmov.s16 r0, q0[5] ; CHECK-MVE-NEXT: vcvt.f16.s32 s1, s10
; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmov.s16 r0, q1[7]
; CHECK-MVE-NEXT: vmov.s16 r0, q0[6] ; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s10
; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[6]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vcvt.f16.s32 s3, s4
; CHECK-MVE-NEXT: vmov.s16 r0, q0[7] ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_half_int16: ; CHECK-MVEFP-LABEL: foo_half_int16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f16.s16 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f16.s16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = sitofp <8 x i16> %src to <8 x half> %out = sitofp <8 x i16> %src to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @foo_half_uint16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x half> @foo_half_uint16(<8 x i16> %src) {
; CHECK-MVE-LABEL: foo_half_uint16: ; CHECK-MVE-LABEL: foo_half_uint16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.u16 r0, q0[0] ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] ; CHECK-MVE-NEXT: vmov.u16 r0, q0[1]
; CHECK-MVE-NEXT: vmov s4, r0 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4 ; CHECK-MVE-NEXT: vmov.u16 r0, q1[0]
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s0
; CHECK-MVE-NEXT: vmov s4, r1 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4 ; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vmov.16 q1[0], r0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov.u16 r0, q0[2]
; CHECK-MVE-NEXT: vmov.16 q1[1], r1
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov.16 q1[2], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[3]
; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov.16 q1[3], r0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[4]
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[2]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.16 q1[4], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vmov.u16 r0, q0[5] ; CHECK-MVE-NEXT: vcvt.f16.u32 s1, s10
; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.16 q1[5], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vmov.u16 r0, q0[6] ; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s10
; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[6]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vmov.16 q1[6], r0 ; CHECK-MVE-NEXT: vcvt.f16.u32 s3, s4
; CHECK-MVE-NEXT: vmov.u16 r0, q0[7] ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0
; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q1[7], r0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_half_uint16: ; CHECK-MVEFP-LABEL: foo_half_uint16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f16.u16 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f16.u16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = uitofp <8 x i16> %src to <8 x half> %out = uitofp <8 x i16> %src to <8 x half>
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld2.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Linesentry:
%a = add <16 x i16> %s1, %s2 %a = add <16 x i16> %s1, %s2
store <16 x i16> %a, <16 x i16> *%dst store <16 x i16> %a, <16 x i16> *%dst
ret void ret void
} }
define void @vld2_v8i16_align1(<16 x i16> *%src, <8 x i16> *%dst) { define void @vld2_v8i16_align1(<16 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld2_v8i16_align1: ; CHECK-LABEL: vld2_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q1, [r0] ; CHECK-NEXT: vldrb.u8 q2, [r0]
; CHECK-NEXT: vldrb.u8 q2, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #16]
; CHECK-NEXT: vmov.u16 r2, q1[1] ; CHECK-NEXT: vmov.f64 d2, d4
; CHECK-NEXT: vmov.u16 r0, q2[1] ; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.u16 r2, q1[3]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vins.f16 s4, s9
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.f32 s5, s10
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vins.f16 s5, s11
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vins.f16 s6, s1
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.f32 s7, s2
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[6] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vins.f16 s7, s3
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vadd.i16 q0, q3, q0 ; CHECK-NEXT: vadd.i16 q0, q1, q3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x i16>, <16 x i16>* %src, align 1 %l1 = load <16 x i16>, <16 x i16>* %src, align 1
%s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%a = add <8 x i16> %s1, %s2 %a = add <8 x i16> %s1, %s2
store <8 x i16> %a, <8 x i16> *%dst store <8 x i16> %a, <8 x i16> *%dst
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines
define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) { define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) {
; CHECK-LABEL: vld2_v2f16: ; CHECK-LABEL: vld2_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r2, [r0] ; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: ldr r0, [r0, #4] ; CHECK-NEXT: ldr r0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmovx.f16 s4, s1 ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <4 x half>, <4 x half>* %src, align 2 %l1 = load <4 x half>, <4 x half>* %src, align 2
%s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2> %s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2>
%s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3> %s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3>
%a = fadd <2 x half> %s1, %s2 %a = fadd <2 x half> %s1, %s2
store <2 x half> %a, <2 x half> *%dst store <2 x half> %a, <2 x half> *%dst
ret void ret void
} }
define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) { define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld2_v4f16: ; CHECK-LABEL: vld2_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmovx.f16 s12, s2 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmovx.f16 s8, s3
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.16 q2[1], r2 ; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s12, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmov.16 q2[2], r0 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vadd.f16 q0, q1, q2
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x half>, <8 x half>* %src, align 2 %l1 = load <8 x half>, <8 x half>* %src, align 2
%s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
Show All 40 Linesentry:
ret void ret void
} }
define void @vld2_v8f16_align1(<16 x half> *%src, <8 x half> *%dst) { define void @vld2_v8f16_align1(<16 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld2_v8f16_align1: ; CHECK-LABEL: vld2_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8} ; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vldrb.u8 q2, [r0] ; CHECK-NEXT: vldrb.u8 q3, [r0]
; CHECK-NEXT: vldrb.u8 q1, [r0, #16] ; CHECK-NEXT: vldrb.u8 q1, [r0, #16]
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov.f64 d0, d6
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vmovx.f16 s8, s12
; CHECK-NEXT: vmov r3, s9 ; CHECK-NEXT: vins.f16 s8, s16
; CHECK-NEXT: vmov.16 q0[1], r3 ; CHECK-NEXT: vmovx.f16 s16, s15
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmovx.f16 s9, s14
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vins.f16 s0, s13
; CHECK-NEXT: vmov.16 q0[3], r2 ; CHECK-NEXT: vins.f16 s9, s16
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov.f32 s1, s14
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vins.f16 s1, s15
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmovx.f16 s11, s6
; CHECK-NEXT: vmovx.f16 s12, s9 ; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s16, s10 ; CHECK-NEXT: vins.f16 s6, s7
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vins.f16 s11, s12
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vmov.16 q3[1], r2 ; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s8, s11
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s7
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8} ; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x half>, <16 x half>* %src, align 1 %l1 = load <16 x half>, <16 x half>* %src, align 1
%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%a = fadd <8 x half> %s1, %s2 %a = fadd <8 x half> %s1, %s2
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld3.ll

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) { define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld3_v8i16: ; CHECK-LABEL: vld3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.16 q4[0], r2 ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.u16 r2, q0[5] ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.16 q4[1], r2 ; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.u16 r2, q1[0] ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[7] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.16 q4[2], r2
; CHECK-NEXT: vmov.u16 r2, q1[3]
; CHECK-NEXT: vmov.f32 s22, s8
; CHECK-NEXT: vmov.16 q4[3], r2
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmovnb.i32 q3, q4 ; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmovnb.i32 q3, q4
; CHECK-NEXT: vmov r0, s14 ; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov q3[2], q3[0], r2, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r2, r0
; CHECK-NEXT: vmov r0, s23 ; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov r2, s17 ; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov q3[3], q3[1], r2, r0 ; CHECK-NEXT: vmov q3[3], q3[1], r2, r0
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[3] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[6] ; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vins.f16 s20, s10
; CHECK-NEXT: vmovx.f16 s21, s11
; CHECK-NEXT: vins.f16 s21, s5
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s7, s1
; CHECK-NEXT: vmovnb.i32 q1, q5 ; CHECK-NEXT: vins.f16 s7, s3
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0 ; CHECK-NEXT: vmovnb.i32 q0, q5
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov r2, s21 ; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov q1[3], q1[1], r2, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
; CHECK-NEXT: vadd.i16 q0, q4, q1 ; CHECK-NEXT: vadd.i16 q0, q4, q0
; CHECK-NEXT: vadd.i16 q0, q0, q3 ; CHECK-NEXT: vadd.i16 q0, q0, q3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i16>, <24 x i16>* %src, align 4 %l1 = load <24 x i16>, <24 x i16>* %src, align 4
%s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a = add <8 x i16> %a1, %s3 %a = add <8 x i16> %a1, %s3
store <8 x i16> %a, <8 x i16> *%dst store <8 x i16> %a, <8 x i16> *%dst
ret void ret void
} }
define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) { define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vld3_v16i16: ; CHECK-LABEL: vld3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.16 q4[0], r2 ; CHECK-NEXT: vmov.u16 r2, q3[0]
; CHECK-NEXT: vmov.u16 r2, q0[5] ; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov.16 q4[1], r2 ; CHECK-NEXT: vmov.u16 r2, q3[3]
; CHECK-NEXT: vmov.u16 r2, q1[0] ; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov.16 q4[2], r2 ; CHECK-NEXT: vmov.u16 r2, q3[6]
; CHECK-NEXT: vmov.u16 r2, q1[3] ; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.16 q4[3], r2 ; CHECK-NEXT: vmov.u16 r2, q2[1]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.u16 r2, q2[4] ; CHECK-NEXT: vmov.u16 r2, q2[4]
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov.u16 r2, q4[2]
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[7] ; CHECK-NEXT: vmov.u16 r2, q4[5]
; CHECK-NEXT: vmov.16 q5[7], r2 ; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.f32 s22, s8 ; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov q3, q5 ; CHECK-NEXT: vmov.u16 r2, q4[4]
; CHECK-NEXT: vmov.16 q6[6], r2
; CHECK-NEXT: vmov.u16 r2, q3[2]
; CHECK-NEXT: vmov.f32 s7, s23
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.u16 r2, q3[5]
; CHECK-NEXT: vmov.16 q5[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.16 q5[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.u16 r2, q4[7]
; CHECK-NEXT: vmov.16 q6[7], r2
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s26, s16
; CHECK-NEXT: vmov q7, q6
; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: vmovnb.i32 q7, q5
; CHECK-NEXT: vmov r12, s27
; CHECK-NEXT: vmov r2, s30
; CHECK-NEXT: vmov q6[2], q6[0], r3, r2
; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov q6[3], q6[1], r2, r12
; CHECK-NEXT: vmov.u16 r2, q4[0]
; CHECK-NEXT: vmov.16 q5[5], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmovx.f16 s23, s17
; CHECK-NEXT: vins.f16 s23, s19
; CHECK-NEXT: vmovx.f16 s16, s12
; CHECK-NEXT: vins.f16 s16, s14
; CHECK-NEXT: vmovx.f16 s17, s15
; CHECK-NEXT: vins.f16 s17, s9
; CHECK-NEXT: vmov q2, q5
; CHECK-NEXT: vmov.16 q4[4], r2
; CHECK-NEXT: vmovnb.i32 q2, q4
; CHECK-NEXT: vmov r3, s16 ; CHECK-NEXT: vmov r3, s16
; CHECK-NEXT: vmovnb.i32 q3, q4 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r2
; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
; CHECK-NEXT: vmov r2, s23 ; CHECK-NEXT: vmov r2, s23
; CHECK-NEXT: vmov r3, s17 ; CHECK-NEXT: vmov r3, s17
; CHECK-NEXT: vmov q3[3], q3[1], r3, r2 ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vmov q2[3], q2[1], r3, r2
; CHECK-NEXT: vadd.i16 q1, q1, q2
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vadd.i16 q1, q1, q6
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.16 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.16 q3[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[0] ; CHECK-NEXT: vmov.u16 r2, q0[0]
; CHECK-NEXT: vmov.16 q4[0], r2 ; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov.16 q3[2], r2
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r2, q0[3] ; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov.f32 s26, s20
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov q4, q6
; CHECK-NEXT: vmovnb.i32 q4, q3
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmov.16 q4[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov r3, s27
; CHECK-NEXT: vmov.16 q4[1], r2 ; CHECK-NEXT: vmov.16 q4[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[6] ; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.16 q4[2], r2 ; CHECK-NEXT: vmov.16 q4[2], r2
; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmov.16 q4[3], r2
; CHECK-NEXT: vmov.u16 r2, q1[4]
; CHECK-NEXT: vmov.16 q4[4], r2
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.16 q4[5], r2
; CHECK-NEXT: vmov.u16 r2, q0[1] ; CHECK-NEXT: vmov.u16 r2, q0[1]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.16 q4[3], r2
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[4] ; CHECK-NEXT: vmov.u16 r2, q0[4]
; CHECK-NEXT: vmov.16 q5[1], r2 ; CHECK-NEXT: vmov.16 q4[4], r2
; CHECK-NEXT: vmov.u16 r2, q5[2]
; CHECK-NEXT: vmov.16 q7[6], r2
; CHECK-NEXT: vmov.u16 r2, q5[5]
; CHECK-NEXT: vmov.16 q7[7], r2
; CHECK-NEXT: vmov.u16 r2, q0[7] ; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vmov.16 q5[2], r2 ; CHECK-NEXT: vmov.16 q4[5], r2
; CHECK-NEXT: vmov.u16 r2, q1[2] ; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmovnb.i32 q1, q5
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: vmov r3, s21
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vadd.i16 q0, q4, q1
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vadd.i16 q0, q0, q3
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.u16 r2, q3[1]
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[4]
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.f32 s7, s23
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.16 q7[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov.16 q7[7], r0
; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vmov.f32 s30, s16
; CHECK-NEXT: vmov q6, q7
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmovnb.i32 q6, q5
; CHECK-NEXT: vmov r0, s26
; CHECK-NEXT: vmov q6[2], q6[0], r2, r0 ; CHECK-NEXT: vmov q6[2], q6[0], r2, r0
; CHECK-NEXT: vmov r0, s31 ; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov q6[3], q6[1], r0, r3
; CHECK-NEXT: vmov.u16 r0, q5[0]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmovx.f16 s15, s21
; CHECK-NEXT: vmov.f32 s19, s31
; CHECK-NEXT: vins.f16 s15, s23
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vins.f16 s20, s10
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s21, s11
; CHECK-NEXT: vins.f16 s21, s1
; CHECK-NEXT: vmov q0, q3
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmovnb.i32 q0, q5
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov r2, s21 ; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov q6[3], q6[1], r2, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vadd.i16 q0, q4, q0
; CHECK-NEXT: vmov.16 q5[5], r0 ; CHECK-NEXT: vadd.i16 q0, q0, q6
; CHECK-NEXT: vmov.u16 r0, q4[3] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q7[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.16 q7[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q7[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov r2, s28
; CHECK-NEXT: vmov q2, q5
; CHECK-NEXT: vmovnb.i32 q2, q7
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vmov q2[2], q2[0], r2, r0
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov r2, s29
; CHECK-NEXT: vmov q2[3], q2[1], r2, r0
; CHECK-NEXT: vadd.i16 q1, q1, q2
; CHECK-NEXT: vadd.i16 q1, q1, q6
; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i16>, <48 x i16>* %src, align 4 %l1 = load <48 x i16>, <48 x i16>* %src, align 4
%s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = add <16 x i16> %s1, %s2 %a1 = add <16 x i16> %s1, %s2
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linesentry:
%a = add <4 x i8> %a1, %s3 %a = add <4 x i8> %a1, %s3
store <4 x i8> %a, <4 x i8> *%dst store <4 x i8> %a, <4 x i8> *%dst
ret void ret void
} }
define void @vld3_v8i8(<24 x i8> *%src, <8 x i8> *%dst) { define void @vld3_v8i8(<24 x i8> *%src, <8 x i8> *%dst) {
; CHECK-LABEL: vld3_v8i8: ; CHECK-LABEL: vld3_v8i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrb.u16 q1, [r0, #16] ; CHECK-NEXT: vldrb.u16 q0, [r0, #16]
; CHECK-NEXT: vmov.u8 r2, q0[0] ; CHECK-NEXT: vmov.u8 r0, q1[1]
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.u8 r2, q0[3] ; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov.16 q2[1], r2 ; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.u8 r2, q0[6] ; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.u8 r2, q0[9] ; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.u8 r2, q0[12] ; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmov.u8 r2, q0[15] ; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.16 q2[5], r2 ; CHECK-NEXT: vmov.u8 r0, q1[0]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[4] ; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[7] ; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[10] ; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[13] ; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmovx.f16 s11, s1
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vins.f16 s11, s3
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[7], r0 ; CHECK-NEXT: vadd.i16 q2, q3, q2
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vadd.i16 q2, q2, q3
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[5] ; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11] ; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[14] ; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vadd.i16 q0, q2, q3 ; CHECK-NEXT: vadd.i16 q0, q2, q3
; CHECK-NEXT: vstrb.16 q0, [r1] ; CHECK-NEXT: vstrb.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i8>, <24 x i8>* %src, align 4 %l1 = load <24 x i8>, <24 x i8>* %src, align 4
%s1 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i8> %l1, <24 x i8> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
▲ Show 20 Lines • Show All 510 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vld3_v2f16: ; CHECK-LABEL: vld3_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r2, r3, [r0] ; CHECK-NEXT: ldrd r2, r3, [r0]
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q0[1], r3 ; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: vmov.32 q0[2], r0 ; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[0], r0 ; CHECK-NEXT: vins.f16 s4, s2
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vadd.f16 q1, q2, q1
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vadd.f16 q1, q0, q1
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x half>, <6 x half>* %src, align 4 %l1 = load <6 x half>, <6 x half>* %src, align 4
%s1 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 1, i32 4>
%s3 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 2, i32 5> %s3 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 2, i32 5>
%a1 = fadd <2 x half> %s1, %s2 %a1 = fadd <2 x half> %s1, %s2
%a = fadd <2 x half> %a1, %s3 %a = fadd <2 x half> %a1, %s3
store <2 x half> %a, <2 x half> *%dst store <2 x half> %a, <2 x half> *%dst
ret void ret void
} }
define void @vld3_v4f16(<12 x half> *%src, <4 x half> *%dst) { define void @vld3_v4f16(<12 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld3_v4f16: ; CHECK-LABEL: vld3_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmov.16 q2[0], r3
; CHECK-NEXT: vmovx.f16 s12, s1
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: ldrd r2, r0, [r0, #16] ; CHECK-NEXT: ldrd r2, r0, [r0, #16]
; CHECK-NEXT: vmov.32 q1[0], r2 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.32 q1[1], r0 ; CHECK-NEXT: vins.f16 s4, s2
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmovx.f16 s16, s4 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmovx.f16 s5, s3
; CHECK-NEXT: vmov.16 q3[0], r2 ; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vins.f16 s14, s12
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmovx.f16 s12, s2
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vins.f16 s1, s12
; CHECK-NEXT: vmov r0, s16 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov.f32 s17, s14
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vins.f16 s8, s12
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vadd.f16 q1, q4, q1
; CHECK-NEXT: vmovx.f16 s4, s5 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vadd.f16 q2, q3, q2
; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vadd.f16 q0, q2, q0
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: vpop {d8} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x half>, <12 x half>* %src, align 4 %l1 = load <12 x half>, <12 x half>* %src, align 4
%s1 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x half> %s1, %s2 %a1 = fadd <4 x half> %s1, %s2
%a = fadd <4 x half> %a1, %s3 %a = fadd <4 x half> %a1, %s3
store <4 x half> %a, <4 x half> *%dst store <4 x half> %a, <4 x half> *%dst
ret void ret void
} }
define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) { define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld3_v8f16: ; CHECK-LABEL: vld3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmovx.f16 s0, s10 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov r3, s9 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.16 q0[0], r3 ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmovx.f16 s20, s19
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmovx.f16 s24, s13
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmovx.f16 s12, s19 ; CHECK-NEXT: vmov.f32 s11, s18
; CHECK-NEXT: vmov.16 q0[3], r2 ; CHECK-NEXT: vins.f16 s11, s20
; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmovx.f16 s20, s16 ; CHECK-NEXT: vmovx.f16 s20, s16
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.16 q3[6], r3 ; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.f64 d10, d6
; CHECK-NEXT: vmov r0, s20 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmovx.f16 s24, s11 ; CHECK-NEXT: vmovx.f16 s24, s4
; CHECK-NEXT: vmov r5, s8 ; CHECK-NEXT: vmov.f32 s21, s15
; CHECK-NEXT: vmov.f32 s14, s16 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov.16 q5[4], r2 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.16 q5[5], r0 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmov r0, s19 ; CHECK-NEXT: vmovx.f16 s24, s12
; CHECK-NEXT: vmov r12, s22 ; CHECK-NEXT: vins.f16 s24, s14
; CHECK-NEXT: vmovx.f16 s20, s17 ; CHECK-NEXT: vmov r12, s2
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vmovx.f16 s25, s15
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmovx.f16 s15, s17
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vins.f16 s25, s5
; CHECK-NEXT: vmov lr, s23 ; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmovx.f16 s20, s6 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vmov r0, s20 ; CHECK-NEXT: vmovx.f16 s6, s6
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmov.16 q5[5], r2 ; CHECK-NEXT: vmov r5, s24
; CHECK-NEXT: vmov r3, s22 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmovx.f16 s20, s9
; CHECK-NEXT: vmov r0, s21
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.16 q5[0], r5
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov r4, s11
; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov r4, s8
; CHECK-NEXT: vmovx.f16 s8, s18
; CHECK-NEXT: vmov.16 q5[3], r4
; CHECK-NEXT: vmov r4, s6
; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov r4, s17
; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: vmov.16 q2[6], r4
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov r4, s0 ; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q2[7], r5
; CHECK-NEXT: vmov q1[2], q1[0], r4, r12 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r12
; CHECK-NEXT: vmov r4, s1 ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov q0[2], q0[0], r2, r3 ; CHECK-NEXT: vmov lr, s25
; CHECK-NEXT: vmov r5, s15 ; CHECK-NEXT: vmov q0[2], q0[0], r5, r2
; CHECK-NEXT: vmov q0[3], q0[1], r0, lr ; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: vmov.f32 s23, s11 ; CHECK-NEXT: vmov q0[3], q0[1], lr, r0
; CHECK-NEXT: vmov q1[3], q1[1], r4, r5 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vmov q1[3], q1[1], r4, r3
; CHECK-NEXT: vadd.f16 q0, q5, q0 ; CHECK-NEXT: vadd.f16 q0, q5, q0
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%l1 = load <24 x half>, <24 x half>* %src, align 4 %l1 = load <24 x half>, <24 x half>* %src, align 4
%s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
%a = fadd <8 x half> %a1, %s3 %a = fadd <8 x half> %a1, %s3
store <8 x half> %a, <8 x half> *%dst store <8 x half> %a, <8 x half> *%dst
ret void ret void
} }
define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) { define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vld3_v16f16: ; CHECK-LABEL: vld3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #64] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vmovx.f16 s4, s8
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vmovx.f16 s20, s17
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov r12, s4
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov r2, s13 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmov.16 q0[7], r3 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmovx.f16 s20, s19
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmovx.f16 s24, s13 ; CHECK-NEXT: vmovx.f16 s24, s13
; CHECK-NEXT: vmov.f32 s6, s19 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmovx.f16 s28, s16 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmov r4, s14 ; CHECK-NEXT: vmov.f32 s11, s18
; CHECK-NEXT: vmov r5, s4 ; CHECK-NEXT: vins.f16 s11, s20
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmov.16 q5[4], r2 ; CHECK-NEXT: vmovx.f16 s20, s16
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.16 q5[5], r12 ; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmov r12, s22 ; CHECK-NEXT: vmov.f64 d10, d6
; CHECK-NEXT: vmovx.f16 s20, s10 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmov r3, s20 ; CHECK-NEXT: vmovx.f16 s24, s4
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmov.f32 s21, s15
; CHECK-NEXT: vmov.16 q5[7], r3 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmov r3, s12 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov r2, s24 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.16 q6[0], r3 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmov.16 q6[1], r2 ; CHECK-NEXT: vmovx.f16 s24, s12
; CHECK-NEXT: vmov r2, s15 ; CHECK-NEXT: vins.f16 s24, s14
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov r12, s2
; CHECK-NEXT: vmov r2, s28 ; CHECK-NEXT: vmovx.f16 s25, s15
; CHECK-NEXT: vmov.16 q6[3], r2 ; CHECK-NEXT: vmovx.f16 s15, s17
; CHECK-NEXT: vmov r2, s18 ; CHECK-NEXT: vins.f16 s25, s5
; CHECK-NEXT: vmovx.f16 s28, s19 ; CHECK-NEXT: vmov r6, s24
; CHECK-NEXT: vmov.16 q6[4], r2 ; CHECK-NEXT: vmov lr, s25
; CHECK-NEXT: vmov r2, s28 ; CHECK-NEXT: vmovx.f16 s24, s18
; CHECK-NEXT: vmovx.f16 s28, s18 ; CHECK-NEXT: vmovx.f16 s6, s6
; CHECK-NEXT: vmov.16 q6[5], r2 ; CHECK-NEXT: vins.f16 s17, s24
; CHECK-NEXT: vmov r2, s28 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vmov.16 q7[4], r2 ; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmovx.f16 s8, s9 ; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: vmov.16 q7[5], r3 ; CHECK-NEXT: vmov q1[2], q1[0], r5, r12
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vmov r5, s1
; CHECK-NEXT: vmov r4, s15
; CHECK-NEXT: vmov q0[2], q0[0], r6, r3
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov.16 q2[6], r3 ; CHECK-NEXT: vmov q0[3], q0[1], lr, r4
; CHECK-NEXT: vmov.16 q2[7], r2 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vmov lr, s30 ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov r6, s11 ; CHECK-NEXT: vmov q1[3], q1[1], r5, r2
; CHECK-NEXT: vmovx.f16 s8, s12 ; CHECK-NEXT: vadd.f16 q0, q5, q0
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vadd.f16 q1, q0, q1
; CHECK-NEXT: vmovx.f16 s12, s15 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.16 q2[0], r3 ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov.16 q2[1], r4
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmov.16 q2[2], r3
; CHECK-NEXT: vmov r3, s17
; CHECK-NEXT: vmov.16 q2[3], r3
; CHECK-NEXT: vmov.f32 s27, s23
; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov r4, s9
; CHECK-NEXT: vmov q2[2], q2[0], r5, r12
; CHECK-NEXT: vmov r5, s3
; CHECK-NEXT: vmov q0[2], q0[0], r3, lr
; CHECK-NEXT: vmov q0[3], q0[1], r4, r6
; CHECK-NEXT: vmov q2[3], q2[1], r2, r5
; CHECK-NEXT: vadd.f16 q0, q6, q0
; CHECK-NEXT: vmovx.f16 s12, s16
; CHECK-NEXT: vadd.f16 q1, q0, q2
; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s4, s19 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov.f32 s4, s17
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vins.f16 s4, s12
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vmov.f32 s5, s8
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmovx.f16 s20, s3
; CHECK-NEXT: vmovx.f16 s12, s10 ; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov.f32 s15, s2
; CHECK-NEXT: vmov r3, s12 ; CHECK-NEXT: vins.f16 s15, s20
; CHECK-NEXT: vmov.16 q3[0], r2 ; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmov.16 q3[1], r3 ; CHECK-NEXT: vmovx.f16 s20, s0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmovx.f16 s24, s17
; CHECK-NEXT: vmovx.f16 s20, s1 ; CHECK-NEXT: vins.f16 s6, s20
; CHECK-NEXT: vmov.16 q3[2], r2 ; CHECK-NEXT: vmov.f64 d10, d8
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmovx.f16 s24, s9 ; CHECK-NEXT: vmovx.f16 s24, s8
; CHECK-NEXT: vmov.16 q3[3], r2 ; CHECK-NEXT: vmov.f32 s21, s19
; CHECK-NEXT: vmovx.f16 s28, s0 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmovx.f16 s24, s11
; CHECK-NEXT: vmov.f32 s6, s16 ; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vmov r5, s10 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmov r4, s12 ; CHECK-NEXT: vmovx.f16 s24, s16
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vins.f16 s24, s18
; CHECK-NEXT: vmov.16 q5[4], r2 ; CHECK-NEXT: vmov.f32 s14, s0
; CHECK-NEXT: vmov r2, s17 ; CHECK-NEXT: vmovx.f16 s25, s19
; CHECK-NEXT: vmov.16 q5[5], r0 ; CHECK-NEXT: vmovx.f16 s19, s1
; CHECK-NEXT: vmov r0, s22 ; CHECK-NEXT: vins.f16 s25, s9
; CHECK-NEXT: vmovx.f16 s20, s18 ; CHECK-NEXT: vmov r3, s24
; CHECK-NEXT: vmov r3, s20 ; CHECK-NEXT: vmov r2, s25
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmovx.f16 s24, s2
; CHECK-NEXT: vmov.16 q5[7], r3 ; CHECK-NEXT: vmovx.f16 s10, s10
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vins.f16 s1, s24
; CHECK-NEXT: vmov r2, s24 ; CHECK-NEXT: vins.f16 s10, s0
; CHECK-NEXT: vmov.16 q6[0], r3 ; CHECK-NEXT: vins.f16 s19, s3
; CHECK-NEXT: vmov.16 q6[1], r2 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vmov r6, s10
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov r2, s28 ; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vmov.16 q6[3], r2
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmovx.f16 s28, s3
; CHECK-NEXT: vmov.16 q6[4], r2
; CHECK-NEXT: vmov r2, s28
; CHECK-NEXT: vmovx.f16 s28, s2
; CHECK-NEXT: vmov.16 q6[5], r2
; CHECK-NEXT: vmov r2, s28
; CHECK-NEXT: vmov r3, s16
; CHECK-NEXT: vmovx.f16 s16, s17
; CHECK-NEXT: vmov.16 q7[4], r2
; CHECK-NEXT: vmov r6, s16
; CHECK-NEXT: vmov.16 q7[5], r3
; CHECK-NEXT: vmov r3, s19
; CHECK-NEXT: vmov.16 q4[6], r6
; CHECK-NEXT: vmov r2, s30
; CHECK-NEXT: vmov.16 q4[7], r3
; CHECK-NEXT: vmov.f32 s27, s23
; CHECK-NEXT: vmov r3, s19
; CHECK-NEXT: vmovx.f16 s16, s8
; CHECK-NEXT: vmov r6, s16
; CHECK-NEXT: vmovx.f16 s8, s11
; CHECK-NEXT: vmov.16 q4[0], r6
; CHECK-NEXT: vmov r6, s8
; CHECK-NEXT: vmov.16 q4[1], r5
; CHECK-NEXT: vmov.16 q4[2], r6
; CHECK-NEXT: vmov r6, s1
; CHECK-NEXT: vmov.16 q4[3], r6
; CHECK-NEXT: vmov q0[2], q0[0], r4, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r0
; CHECK-NEXT: vmov r6, s16 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov q1[2], q1[0], r3, r6
; CHECK-NEXT: vmov q1[2], q1[0], r6, r2 ; CHECK-NEXT: vmov r5, s19
; CHECK-NEXT: vmov r5, s17 ; CHECK-NEXT: vmov q1[3], q1[1], r2, r5
; CHECK-NEXT: vmov q1[3], q1[1], r5, r3 ; CHECK-NEXT: vmov r4, s15
; CHECK-NEXT: vmov r4, s13 ; CHECK-NEXT: vmov q0[3], q0[1], r0, r4
; CHECK-NEXT: vmov q0[3], q0[1], r4, r0 ; CHECK-NEXT: vadd.f16 q1, q5, q1
; CHECK-NEXT: vadd.f16 q1, q6, q1
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%l1 = load <48 x half>, <48 x half>* %src, align 4 %l1 = load <48 x half>, <48 x half>* %src, align 4
%s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = fadd <16 x half> %s1, %s2 %a1 = fadd <16 x half> %s1, %s2
%a = fadd <16 x half> %a1, %s3 %a = fadd <16 x half> %a1, %s3
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld4.ll

Show First 20 Lines • Show All 384 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vld4_v8i16_align1(<32 x i16> *%src, <8 x i16> *%dst) { define void @vld4_v8i16_align1(<32 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld4_v8i16_align1: ; CHECK-LABEL: vld4_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrb.u8 q1, [r0] ; CHECK-NEXT: vldrb.u8 q3, [r0]
; CHECK-NEXT: vldrb.u8 q0, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #32]
; CHECK-NEXT: vldrb.u8 q2, [r0, #32] ; CHECK-NEXT: vldrb.u8 q1, [r0, #48]
; CHECK-NEXT: vldrb.u8 q3, [r0, #48] ; CHECK-NEXT: vldrb.u8 q2, [r0, #16]
; CHECK-NEXT: vmov.u16 r2, q1[3]
; CHECK-NEXT: vmov.16 q4[0], r2
; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.16 q4[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q4[2], r2
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.16 q5[5], r2
; CHECK-NEXT: vmov.u16 r0, q3[3] ; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.f32 s18, s1
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.16 q5[0], r0 ; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.16 q5[1], r0 ; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[2] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q5[2], r0 ; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vins.f16 s18, s3
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[6] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.f32 s19, s5
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[2] ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vins.f16 s19, s7
; CHECK-NEXT: vmov.16 q6[6], r0 ; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[6] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.f32 s16, s13
; CHECK-NEXT: vmov.16 q6[7], r0 ; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r0, q0[6] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q5[3], r0 ; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vins.f16 s16, s15
; CHECK-NEXT: vmov.f32 s22, s26 ; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vadd.i16 q4, q5, q4
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[1] ; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.f32 s22, s26 ; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vins.f16 s17, s11
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vmov.16 q6[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vadd.i16 q4, q4, q5
; CHECK-NEXT: vmov.f64 d11, d0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q6[1], r0 ; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q6[2], r0 ; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vins.f16 s22, s2
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.f32 s23, s4
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vins.f16 s23, s6
; CHECK-NEXT: vmov.u16 r0, q3[0] ; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vins.f16 s20, s14
; CHECK-NEXT: vmov.u16 r0, q3[4] ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.16 q1[7], r0 ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.f32 s26, s6 ; CHECK-NEXT: vins.f16 s21, s10
; CHECK-NEXT: vmov.f32 s27, s7 ; CHECK-NEXT: vmov.f32 s26, s14
; CHECK-NEXT: vadd.i16 q0, q6, q5 ; CHECK-NEXT: vmov.f32 s27, s15
; CHECK-NEXT: vadd.i16 q0, q5, q6
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i16>, <32 x i16>* %src, align 1 %l1 = load <32 x i16>, <32 x i16>* %src, align 1
%s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
▲ Show 20 Lines • Show All 615 Lines • ▼ Show 20 Lines
; f16 ; f16
define void @vld4_v2f16(<8 x half> *%src, <2 x half> *%dst) { define void @vld4_v2f16(<8 x half> *%src, <2 x half> *%dst) {
; CHECK-LABEL: vld4_v2f16: ; CHECK-LABEL: vld4_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmovx.f16 s4, s3 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmovx.f16 s4, s1 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov.16 q1[1], r0 ; CHECK-NEXT: vadd.f16 q1, q1, q2
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vadd.f16 q1, q2, q1
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vins.f16 s12, s8
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x half>, <8 x half>* %src, align 2 %l1 = load <8 x half>, <8 x half>* %src, align 2
%s1 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 0, i32 4> %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 0, i32 4>
%s2 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 1, i32 5> %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 1, i32 5>
%s3 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 2, i32 6> %s3 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 2, i32 6>
%s4 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 3, i32 7> %s4 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 3, i32 7>
%a1 = fadd <2 x half> %s1, %s2 %a1 = fadd <2 x half> %s1, %s2
%a2 = fadd <2 x half> %s3, %s4 %a2 = fadd <2 x half> %s3, %s4
%a3 = fadd <2 x half> %a1, %a2 %a3 = fadd <2 x half> %a1, %a2
store <2 x half> %a3, <2 x half> *%dst store <2 x half> %a3, <2 x half> *%dst
ret void ret void
} }
define void @vld4_v4f16(<16 x half> *%src, <4 x half> *%dst) { define void @vld4_v4f16(<16 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld4_v4f16: ; CHECK-LABEL: vld4_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8} ; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vldrh.u16 q1, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vldrh.u16 q0, [r0, #16] ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmov r3, s7 ; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.16 q2[1], r3 ; CHECK-NEXT: vldrh.u16 q1, [r0, #16]
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmovx.f16 s16, s7
; CHECK-NEXT: vmov.16 q2[2], r0 ; CHECK-NEXT: vmovx.f16 s9, s5
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vmovx.f16 s12, s7 ; CHECK-NEXT: vins.f16 s9, s16
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmov.16 q3[1], r2
; CHECK-NEXT: vmovx.f16 s16, s3
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s0
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vadd.f16 q2, q2, q3
; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s6
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.16 q3[1], r2
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s2 ; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vadd.f16 q2, q3, q2
; CHECK-NEXT: vmov r0, s16 ; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vins.f16 s12, s16
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vmov.16 q1[0], r0 ; CHECK-NEXT: vmovx.f16 s13, s4
; CHECK-NEXT: vmov.16 q1[1], r2 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s13, s16
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vadd.f16 q0, q1, q3
; CHECK-NEXT: vadd.f16 q0, q0, q2 ; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: vpop {d8} ; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x half>, <16 x half>* %src, align 2 %l1 = load <16 x half>, <16 x half>* %src, align 2
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Linesentry:
%a3 = fadd <16 x half> %a1, %a2 %a3 = fadd <16 x half> %a1, %a2
store <16 x half> %a3, <16 x half> *%dst store <16 x half> %a3, <16 x half> *%dst
ret void ret void
} }
define void @vld4_v8f16_align1(<32 x half> *%src, <8 x half> *%dst) { define void @vld4_v8f16_align1(<32 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld4_v8f16_align1: ; CHECK-LABEL: vld4_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: .pad #64 ; CHECK-NEXT: vldrb.u8 q2, [r0, #32]
; CHECK-NEXT: sub sp, #64 ; CHECK-NEXT: vldrb.u8 q3, [r0, #48]
; CHECK-NEXT: vldrb.u8 q6, [r0] ; CHECK-NEXT: vmovx.f16 s4, s11
; CHECK-NEXT: vldrb.u8 q2, [r0, #16] ; CHECK-NEXT: vmovx.f16 s2, s9
; CHECK-NEXT: vldrb.u8 q4, [r0, #32] ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vldrb.u8 q5, [r0, #48] ; CHECK-NEXT: vmovx.f16 s4, s15
; CHECK-NEXT: vmov r2, s24 ; CHECK-NEXT: vmovx.f16 s3, s13
; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s9, s11
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmov r3, s26 ; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vmov.16 q0[1], r3 ; CHECK-NEXT: vmovx.f16 s28, s10
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmovx.f16 s26, s8
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vmovx.f16 s16, s7
; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmovx.f16 s0, s19 ; CHECK-NEXT: vins.f16 s0, s16
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vldrb.u8 q4, [r0, #16]
; CHECK-NEXT: vmovx.f16 s0, s17 ; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vins.f16 s26, s28
; CHECK-NEXT: vmovx.f16 s0, s21 ; CHECK-NEXT: vmovx.f16 s20, s19
; CHECK-NEXT: vmov.16 q1[4], r3 ; CHECK-NEXT: vmovx.f16 s1, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s1, s20
; CHECK-NEXT: vmov.16 q1[5], r2 ; CHECK-NEXT: vmov.f32 s22, s9
; CHECK-NEXT: vmovx.f16 s0, s23 ; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovx.f16 s28, s14
; CHECK-NEXT: vmovx.f16 s0, s25 ; CHECK-NEXT: vmovx.f16 s27, s12
; CHECK-NEXT: vmov.16 q1[7], r0 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vmovx.f16 s0, s27 ; CHECK-NEXT: vmov.f32 s11, s12
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s27, s28
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vmovx.f16 s0, s9 ; CHECK-NEXT: vmovx.f16 s28, s6
; CHECK-NEXT: vmov.16 q3[1], r2 ; CHECK-NEXT: vmovx.f16 s24, s4
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s20, s5
; CHECK-NEXT: vmovx.f16 s0, s11 ; CHECK-NEXT: vins.f16 s17, s19
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vins.f16 s24, s28
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s21, s17
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmovx.f16 s28, s18
; CHECK-NEXT: vmov r0, s17 ; CHECK-NEXT: vmovx.f16 s25, s16
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov r2, s19 ; CHECK-NEXT: vins.f16 s16, s18
; CHECK-NEXT: vmov.16 q0[5], r2 ; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: vmov r0, s21 ; CHECK-NEXT: vmov.f32 s5, s16
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vadd.f16 q0, q5, q0
; CHECK-NEXT: vmov r0, s23 ; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov r0, s25 ; CHECK-NEXT: vadd.f16 q1, q1, q6
; CHECK-NEXT: vmov.16 q7[0], r0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vmov r2, s27
; CHECK-NEXT: vmov.16 q7[1], r2
; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q7[2], r0
; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: vmovx.f16 s0, s16
; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s18
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmovx.f16 s8, s20
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s22
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s24
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s26
; CHECK-NEXT: vmov.16 q6[0], r0
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q6[1], r2
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.16 q4[5], r2
; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vmov.f32 s31, s3
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vmov.f32 s27, s7
; CHECK-NEXT: vadd.f16 q3, q7, q3
; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vadd.f16 q0, q0, q6
; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #64 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x half>, <32 x half>* %src, align 1 %l1 = load <32 x half>, <32 x half>* %src, align 1
%s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vldst4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 { define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
; CHECK-LABEL: vldst4: ; CHECK-LABEL: vldst4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #80 ; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, #80 ; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: mul r12, r3, r2 ; CHECK-NEXT: mul r12, r3, r2
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp.w r2, r12, lsr #2 ; CHECK-NEXT: cmp.w r2, r12, lsr #2
; CHECK-NEXT: beq.w .LBB0_3 ; CHECK-NEXT: beq.w .LBB0_3
; CHECK-NEXT: @ %bb.1: @ %vector.ph ; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: mvn r3, #7 ; CHECK-NEXT: mvn r3, #7
; CHECK-NEXT: ldr r5, [sp, #160] ; CHECK-NEXT: ldr r2, [sp, #96]
; CHECK-NEXT: and.w r3, r3, r12, lsr #2 ; CHECK-NEXT: and.w r3, r3, r12, lsr #2
; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: add.w lr, r3, r12, lsr #3 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3
; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: .LBB0_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q5, [r0, #32] ; CHECK-NEXT: vldrh.u16 q3, [r0, #32]
; CHECK-NEXT: vldrh.u16 q3, [r0, #48] ; CHECK-NEXT: vldrh.u16 q5, [r0, #48]
; CHECK-NEXT: vldrh.u16 q7, [r0], #64 ; CHECK-NEXT: vldrh.u16 q4, [r0], #64
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vmovx.f16 s4, s15
; CHECK-NEXT: vmovx.f16 s8, s12 ; CHECK-NEXT: vmovx.f16 s2, s13
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmov r3, s22
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov r2, s28
; CHECK-NEXT: vldrh.u16 q6, [r0, #-48]
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov r3, s30
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r2, s24
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vmov r2, s26
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmul.f16 q0, q1, r5
; CHECK-NEXT: vmovx.f16 s4, s24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s30
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s28
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmovx.f16 s4, s22
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmovx.f16 s4, s20
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov.16 q1[4], r4
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s8, s14
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s8, s26
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmovx.f16 s8, s13
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vmul.f16 q0, q0, r5
; CHECK-NEXT: vmov r3, s23
; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s19
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: vmov r3, s29
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov r2, s31
; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s25
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov r2, s15
; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vmov r2, s27
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmovx.f16 s0, s31
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s29
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmul.f16 q4, q1, r5
; CHECK-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmovx.f16 s4, s25
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmovx.f16 s4, s23 ; CHECK-NEXT: vmovx.f16 s4, s23
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vmovx.f16 s3, s21
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vldrh.u16 q7, [r0, #-48]
; CHECK-NEXT: vmovx.f16 s4, s21 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmov r4, s4 ; CHECK-NEXT: vmovx.f16 s4, s19
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q1[4], r4
; CHECK-NEXT: vmov r3, s16
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s8, s15
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s8, s27
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.16 q1[2], r3
; CHECK-NEXT: vmul.f16 q6, q0, r5
; CHECK-NEXT: vmovx.f16 s0, s16
; CHECK-NEXT: vmov r2, s24
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s24
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmov.16 q5[1], r3
; CHECK-NEXT: vmov r3, s25
; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q5[5], r2
; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov.16 q3[2], r2
; CHECK-NEXT: vmovx.f16 s0, s17 ; CHECK-NEXT: vmovx.f16 s0, s17
; CHECK-NEXT: vmov.16 q3[3], r3 ; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s0, s25 ; CHECK-NEXT: vmovx.f16 s4, s31
; CHECK-NEXT: vmov.16 q3[6], r2 ; CHECK-NEXT: vmovx.f16 s1, s29
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s21, s23
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vins.f16 s17, s19
; CHECK-NEXT: vmul.f16 q1, q0, r2
; CHECK-NEXT: vmov.f32 s2, s13
; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vins.f16 s29, s31
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: vmov.f32 s1, s29
; CHECK-NEXT: vmul.f16 q2, q0, r2
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s27, s8
; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.f32 s25, s8
; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vins.f16 s27, s0
; CHECK-NEXT: vmovx.f16 s2, s12
; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s24, s14
; CHECK-NEXT: vins.f16 s2, s24
; CHECK-NEXT: vmovx.f16 s24, s22
; CHECK-NEXT: vmovx.f16 s3, s20
; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s3, s24
; CHECK-NEXT: vmovx.f16 s24, s18
; CHECK-NEXT: vmovx.f16 s0, s16
; CHECK-NEXT: vins.f16 s20, s22
; CHECK-NEXT: vins.f16 s0, s24
; CHECK-NEXT: vmovx.f16 s24, s30
; CHECK-NEXT: vmovx.f16 s1, s28
; CHECK-NEXT: vins.f16 s16, s18
; CHECK-NEXT: vins.f16 s1, s24
; CHECK-NEXT: vins.f16 s28, s30
; CHECK-NEXT: vmul.f16 q6, q0, r2
; CHECK-NEXT: vmov.f32 s2, s12
; CHECK-NEXT: vmov.f32 s3, s20
; CHECK-NEXT: vmov.f32 s17, s28
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmovx.f16 s2, s24
; CHECK-NEXT: vmul.f16 q5, q4, r2
; CHECK-NEXT: vmovx.f16 s0, s20
; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vmov.f32 s14, s0
; CHECK-NEXT: vmovx.f16 s0, s9 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmov.16 q3[7], r2 ; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmov.16 q7[0], r2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov r3, s5 ; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vmov.16 q7[1], r3 ; CHECK-NEXT: vmov.f32 s19, s0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmovx.f16 s31, s10
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s18, s21
; CHECK-NEXT: vmov.16 q7[4], r2 ; CHECK-NEXT: vins.f16 s21, s25
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s10, s6
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s16, s21
; CHECK-NEXT: vmov.16 q7[5], r2 ; CHECK-NEXT: vmovx.f16 s0, s25
; CHECK-NEXT: vmov r3, s26 ; CHECK-NEXT: vmov.f32 s29, s10
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vins.f16 s18, s0
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vins.f16 s31, s0
; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q2[3], r3
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s26 ; CHECK-NEXT: vmovx.f16 s0, s26
; CHECK-NEXT: vmov.16 q2[6], r2 ; CHECK-NEXT: vmovx.f16 s30, s22
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s22, s26
; CHECK-NEXT: vmov.16 q2[7], r2 ; CHECK-NEXT: vmov.f32 s28, s22
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vins.f16 s30, s0
; CHECK-NEXT: vmov r3, s18 ; CHECK-NEXT: vmovx.f16 s3, s11
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vins.f16 s11, s7
; CHECK-NEXT: vmovx.f16 s4, s6 ; CHECK-NEXT: vstrh.16 q7, [r1, #32]
; CHECK-NEXT: vmov.16 q0[1], r3 ; CHECK-NEXT: vmov.f32 s1, s11
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmovx.f16 s4, s18 ; CHECK-NEXT: vmovx.f16 s4, s27
; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmovx.f16 s2, s23
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vins.f16 s23, s27
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov.f32 s0, s23
; CHECK-NEXT: vmov.16 q0[5], r2 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmov r2, s19 ; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov r3, s27 ; CHECK-NEXT: vstrh.16 q0, [r1, #48]
; CHECK-NEXT: vmov.16 q1[2], r2 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmovx.f16 s16, s19 ; CHECK-NEXT: vmov.f32 s15, s7
; CHECK-NEXT: vmov.16 q1[3], r3 ; CHECK-NEXT: vstrh.16 q3, [r1], #64
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vstrh.16 q4, [r1, #-48]
; CHECK-NEXT: vmovx.f16 s16, s27
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s16, s19
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s21, s25
; CHECK-NEXT: vstrh.16 q0, [r1, #32]
; CHECK-NEXT: vmov.16 q4[5], r2
; CHECK-NEXT: vmov.f32 s29, s13
; CHECK-NEXT: vmov q2, q4
; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vstrh.16 q2, [r1, #48]
; CHECK-NEXT: vstrh.16 q5, [r1], #64
; CHECK-NEXT: vmov.f32 s31, s15
; CHECK-NEXT: vstrh.16 q7, [r1, #-48]
; CHECK-NEXT: le lr, .LBB0_2 ; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: .LBB0_3: @ %while.end ; CHECK-NEXT: .LBB0_3: @ %while.end
; CHECK-NEXT: add sp, #80 ; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
%l0 = bitcast i16 %tmp.0.extract.trunc to half %l0 = bitcast i16 %tmp.0.extract.trunc to half
%mul = mul i32 %numCols, %numRows %mul = mul i32 %numCols, %numRows
%shr = lshr i32 %mul, 2 %shr = lshr i32 %mul, 2
%cmp38 = icmp eq i32 %shr, 0 %cmp38 = icmp eq i32 %shr, 0
br i1 %cmp38, label %while.end, label %vector.ph br i1 %cmp38, label %while.end, label %vector.ph
Show All 39 Lines

llvm/test/CodeGen/Thumb2/mve-vmovn.ll

Show First 20 Lines • Show All 387 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vmovn16_b2: ; CHECK-LABEL: vmovn16_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmovx.f16 s9, s5
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vins.f16 s9, s1
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vins.f16 s8, s0
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmovx.f16 s10, s6
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vins.f16 s10, s2
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmovx.f16 s11, s7
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vins.f16 s11, s3
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn16_b2: ; CHECKBE-LABEL: vmovn16_b2:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.16 q2, q1 ; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vrev64.16 q3, q0 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: vmov.u16 r0, q2[1] ; CHECKBE-NEXT: vmovx.f16 s5, s1
; CHECKBE-NEXT: vmov.16 q1[0], r0 ; CHECKBE-NEXT: vins.f16 s5, s9
; CHECKBE-NEXT: vmov.u16 r0, q3[0] ; CHECKBE-NEXT: vmovx.f16 s4, s0
; CHECKBE-NEXT: vmov.16 q1[1], r0 ; CHECKBE-NEXT: vins.f16 s4, s8
; CHECKBE-NEXT: vmov.u16 r0, q2[3] ; CHECKBE-NEXT: vmovx.f16 s6, s2
; CHECKBE-NEXT: vmov.16 q1[2], r0 ; CHECKBE-NEXT: vins.f16 s6, s10
; CHECKBE-NEXT: vmov.u16 r0, q3[2] ; CHECKBE-NEXT: vmovx.f16 s7, s3
; CHECKBE-NEXT: vmov.16 q1[3], r0 ; CHECKBE-NEXT: vins.f16 s7, s11
; CHECKBE-NEXT: vmov.u16 r0, q2[5]
; CHECKBE-NEXT: vmov.16 q1[4], r0
; CHECKBE-NEXT: vmov.u16 r0, q3[4]
; CHECKBE-NEXT: vmov.16 q1[5], r0
; CHECKBE-NEXT: vmov.u16 r0, q2[7]
; CHECKBE-NEXT: vmov.16 q1[6], r0
; CHECKBE-NEXT: vmov.u16 r0, q3[6]
; CHECKBE-NEXT: vmov.16 q1[7], r0
; CHECKBE-NEXT: vrev64.16 q0, q1 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vmovn16_b3: ; CHECK-LABEL: vmovn16_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmovx.f16 s1, s9
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vins.f16 s1, s5
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.u16 r0, q2[3] ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmovx.f16 s2, s10
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmovx.f16 s3, s11
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vins.f16 s3, s7
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn16_b3: ; CHECKBE-LABEL: vmovn16_b3:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.16 q3, q0 ; CHECKBE-NEXT: vrev64.16 q3, q0
; CHECKBE-NEXT: vrev64.16 q2, q1
; CHECKBE-NEXT: vmovx.f16 s5, s13
; CHECKBE-NEXT: vins.f16 s5, s9
; CHECKBE-NEXT: vmovx.f16 s4, s12
; CHECKBE-NEXT: vins.f16 s4, s8
; CHECKBE-NEXT: vmovx.f16 s6, s14
; CHECKBE-NEXT: vins.f16 s6, s10
; CHECKBE-NEXT: vmovx.f16 s7, s15
; CHECKBE-NEXT: vins.f16 s7, s11
; CHECKBE-NEXT: vrev64.16 q0, q1 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: vmov.u16 r0, q3[1]
; CHECKBE-NEXT: vmov.16 q2[0], r0
; CHECKBE-NEXT: vmov.u16 r0, q0[0]
; CHECKBE-NEXT: vmov.16 q2[1], r0
; CHECKBE-NEXT: vmov.u16 r0, q3[3]
; CHECKBE-NEXT: vmov.16 q2[2], r0
; CHECKBE-NEXT: vmov.u16 r0, q0[2]
; CHECKBE-NEXT: vmov.16 q2[3], r0
; CHECKBE-NEXT: vmov.u16 r0, q3[5]
; CHECKBE-NEXT: vmov.16 q2[4], r0
; CHECKBE-NEXT: vmov.u16 r0, q0[4]
; CHECKBE-NEXT: vmov.16 q2[5], r0
; CHECKBE-NEXT: vmov.u16 r0, q3[7]
; CHECKBE-NEXT: vmov.16 q2[6], r0
; CHECKBE-NEXT: vmov.u16 r0, q0[6]
; CHECKBE-NEXT: vmov.16 q2[7], r0
; CHECKBE-NEXT: vrev64.16 q0, q2
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vmovn16_b4: ; CHECK-LABEL: vmovn16_b4:
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llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll

Show First 20 Lines • Show All 308 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) {
; CHECK-LABEL: vmovn16_b2: ; CHECK-LABEL: vmovn16_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r1, q1[1] ; CHECK-NEXT: vmovx.f16 s9, s5
; CHECK-NEXT: vmov.16 q2[0], r1 ; CHECK-NEXT: vins.f16 s9, s1
; CHECK-NEXT: vmov.u16 r1, q0[0] ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmov.16 q2[1], r1 ; CHECK-NEXT: vins.f16 s8, s0
; CHECK-NEXT: vmov.u16 r1, q1[3] ; CHECK-NEXT: vmovx.f16 s10, s6
; CHECK-NEXT: vmov.16 q2[2], r1 ; CHECK-NEXT: vins.f16 s10, s2
; CHECK-NEXT: vmov.u16 r1, q0[2] ; CHECK-NEXT: vmovx.f16 s11, s7
; CHECK-NEXT: vmov.16 q2[3], r1 ; CHECK-NEXT: vins.f16 s11, s3
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov.16 q2[4], r1
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov.16 q2[5], r1
; CHECK-NEXT: vmov.u16 r1, q1[7]
; CHECK-NEXT: vmov.16 q2[6], r1
; CHECK-NEXT: vmov.u16 r1, q0[6]
; CHECK-NEXT: vmov.16 q2[7], r1
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q2, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) {
; CHECK-LABEL: vmovn16_b3: ; CHECK-LABEL: vmovn16_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r1, q0[1] ; CHECK-NEXT: vmovx.f16 s9, s1
; CHECK-NEXT: vmov.16 q2[0], r1 ; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q2[1], r1 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.u16 r1, q0[3] ; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vmov.16 q2[2], r1 ; CHECK-NEXT: vins.f16 s10, s6
; CHECK-NEXT: vmov.u16 r1, q1[2] ; CHECK-NEXT: vmovx.f16 s11, s3
; CHECK-NEXT: vmov.16 q2[3], r1 ; CHECK-NEXT: vins.f16 s11, s7
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov.16 q2[4], r1
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmov.16 q2[5], r1
; CHECK-NEXT: vmov.u16 r1, q0[7]
; CHECK-NEXT: vmov.16 q2[6], r1
; CHECK-NEXT: vmov.u16 r1, q1[6]
; CHECK-NEXT: vmov.16 q2[7], r1
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q2, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst2.ll

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Linesentry:
store <32 x i16> %s, <32 x i16> *%dst, align 2 store <32 x i16> %s, <32 x i16> *%dst, align 2
ret void ret void
} }
define void @vst2_v8i16_align1(<8 x i16> *%src, <16 x i16> *%dst) { define void @vst2_v8i16_align1(<8 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vst2_v8i16_align1: ; CHECK-LABEL: vst2_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.u16 r2, q1[4] ; CHECK-NEXT: vmov.f64 d4, d3
; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vins.f16 s8, s2
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmov.f64 d6, d2
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.u16 r0, q2[7] ; CHECK-NEXT: vins.f16 s12, s0
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vins.f16 s10, s3
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q2[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vstrb.8 q2, [r1, #16]
; CHECK-NEXT: vins.f16 s14, s1
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[3] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vstrb.8 q3, [r1] ; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
%s = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
▲ Show 20 Lines • Show All 264 Lines • ▼ Show 20 Lines
} }
; f16 ; f16
define void @vst2_v2f16(<2 x half> *%src, <4 x half> *%dst) { define void @vst2_v2f16(<2 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vst2_v2f16: ; CHECK-LABEL: vst2_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r2, r0, [r0] ; CHECK-NEXT: ldrd r2, r0, [r0]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.32 q1[0], r0 ; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmovx.f16 s5, s4
; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s0, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: str r2, [r1, #4] ; CHECK-NEXT: str r2, [r1, #4]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
%s = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %s = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
store <4 x half> %s, <4 x half> *%dst, align 2 store <4 x half> %s, <4 x half> *%dst, align 2
ret void ret void
} }
define void @vst2_v4f16(<4 x half> *%src, <8 x half> *%dst) { define void @vst2_v4f16(<4 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vst2_v4f16: ; CHECK-LABEL: vst2_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldm.w r0, {r2, r3, r12} ; CHECK-NEXT: ldrd r2, r12, [r0]
; CHECK-NEXT: vmov.32 q0[0], r12 ; CHECK-NEXT: ldrd r3, r0, [r0, #8]
; CHECK-NEXT: ldr r0, [r0, #12] ; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.32 q2[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: vmov.32 q2[1], r3 ; CHECK-NEXT: vmov.32 q1[1], r12
; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vins.f16 s12, s8
; CHECK-NEXT: vmov.16 q1[1], r0 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s8, s9
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s5, s1
; CHECK-NEXT: vmov.16 q1[7], r0 ; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vstrh.16 q1, [r1] ; CHECK-NEXT: vins.f16 s11, s0
; CHECK-NEXT: vstrh.16 q2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %s = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x half> %s, <8 x half> *%dst, align 2 store <8 x half> %s, <8 x half> *%dst, align 2
Show All 38 Linesentry:
%s = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %s = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x half> %s, <32 x half> *%dst, align 2 store <32 x half> %s, <32 x half> *%dst, align 2
ret void ret void
} }
define void @vst2_v8f16_align1(<8 x half> *%src, <16 x half> *%dst) { define void @vst2_v8f16_align1(<8 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vst2_v8f16_align1: ; CHECK-LABEL: vst2_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmovx.f16 s12, s6 ; CHECK-NEXT: vmovx.f16 s9, s6
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vins.f16 s6, s2
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s2 ; CHECK-NEXT: vmovx.f16 s12, s2
; CHECK-NEXT: vmov.16 q2[2], r0 ; CHECK-NEXT: vins.f16 s9, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s3 ; CHECK-NEXT: vmovx.f16 s12, s3
; CHECK-NEXT: vmov.16 q2[6], r0 ; CHECK-NEXT: vmovx.f16 s11, s7
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vins.f16 s7, s3
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vins.f16 s11, s12
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vstrb.8 q2, [r1, #16] ; CHECK-NEXT: vstrb.8 q2, [r1, #16]
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s4, s5 ; CHECK-NEXT: vins.f16 s12, s8
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vins.f16 s5, s1
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vins.f16 s11, s0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vstrb.8 q2, [r1] ; CHECK-NEXT: vstrb.8 q2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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llvm/test/CodeGen/Thumb2/mve-vst3.ll

Show First 20 Lines • Show All 379 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) { define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) {
; CHECK-LABEL: vst3_v8i16: ; CHECK-LABEL: vst3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.u16 r2, q1[2] ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.u16 r2, q1[4] ; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.16 q0[6], r2 ; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.u16 r2, q2[5] ; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.16 q0[7], r2 ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.u16 r2, q2[0] ; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.16 q3[0], r2 ; CHECK-NEXT: vins.f16 s16, s8
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.u16 r0, q4[1] ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.f32 s19, s5
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vdup.32 q5, r2 ; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s13, s8 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.u16 r2, q5[2] ; CHECK-NEXT: vmov.u16 r2, q5[2]
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4] ; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q5[5] ; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[5] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q5[0], r0 ; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q5[1], r0 ; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q4[6] ; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.16 q5[3], r0 ; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[7] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.f32 s13, s25 ; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.f32 s14, s26 ; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vdup.32 q6, r2 ; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s1, s5 ; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vmov.u16 r2, q6[2] ; CHECK-NEXT: vmov.u16 r2, q6[2]
; CHECK-NEXT: vmov.f32 s22, s7
; CHECK-NEXT: vrev32.16 q4, q4
; CHECK-NEXT: vmov.16 q7[2], r2
; CHECK-NEXT: vmov.u16 r0, q5[3] ; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov.u16 r2, q4[2] ; CHECK-NEXT: vmov.16 q7[2], r2
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s1, s13
; CHECK-NEXT: vmov.16 q7[3], r0 ; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vstrw.32 q3, [r1] ; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vmov.16 q3[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q7[4], r0 ; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.u16 r0, q6[5] ; CHECK-NEXT: vmov.u16 r0, q6[5]
; CHECK-NEXT: vmov.16 q3[3], r2 ; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.u16 r2, q0[4] ; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.16 q7[5], r0 ; CHECK-NEXT: vmov.16 q7[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[5] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q3[4], r2 ; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.f32 s21, s29 ; CHECK-NEXT: vmov.f32 s21, s29
; CHECK-NEXT: vmov.f32 s1, s13 ; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[4]
; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.f32 s22, s30 ; CHECK-NEXT: vmov.f32 s22, s30
; CHECK-NEXT: vmov.f32 s2, s14 ; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vstrw.32 q5, [r1, #32] ; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
Show All 9 Lines
define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) { define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) {
; CHECK-LABEL: vst3_v16i16: ; CHECK-LABEL: vst3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #160
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #160
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vmov.u16 r2, q0[0] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f64 d4, d0
; CHECK-NEXT: vmov.u16 r2, q7[1]
; CHECK-NEXT: vstrw.32 q0, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r2, q1[0] ; CHECK-NEXT: vins.f16 s8, s28
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov.16 q2[6], r2 ; CHECK-NEXT: vins.f16 s11, s29
; CHECK-NEXT: vmov.u16 r2, q1[2] ; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vmov.16 q2[7], r2 ; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov q7, q1
; CHECK-NEXT: vmov.f32 s9, s0
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.u16 r2, q4[3]
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r3, q0[2] ; CHECK-NEXT: vmov.u16 r3, q0[2]
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.16 q3[2], r3
; CHECK-NEXT: vmov.16 q2[2], r3 ; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.u16 r2, q4[4]
; CHECK-NEXT: vmov.u16 r2, q3[4] ; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.u16 r2, q0[5]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.16 q2[5], r2
; CHECK-NEXT: vmov.u16 r2, q3[5]
; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[5] ; CHECK-NEXT: vmov.u16 r2, q0[5]
; CHECK-NEXT: vmov.16 q5[1], r2
; CHECK-NEXT: vmov.u16 r2, q3[6]
; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[7]
; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s22, s3
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vmov.16 q3[5], r2
; CHECK-NEXT: vmov.u16 r2, q5[3] ; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov.f64 d12, d0
; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s24, s4
; CHECK-NEXT: vmov.16 q6[4], r2
; CHECK-NEXT: vmov.f32 s27, s1
; CHECK-NEXT: vins.f16 s27, s5
; CHECK-NEXT: vmov.f32 s25, s0
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.u16 r2, q6[3]
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r0, q0[2] ; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.u16 r0, q6[4]
; CHECK-NEXT: vmov.16 q4[3], r2 ; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[0] ; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q6[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[1] ; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: vmov.16 q6[6], r0 ; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[2] ; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vdup.32 q0, r2 ; CHECK-NEXT: vdup.32 q0, r2
; CHECK-NEXT: vmov.16 q6[7], r0 ; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.f32 s25, s8 ; CHECK-NEXT: vmov.f32 s18, s23
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.u16 r0, q6[3] ; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u16 r0, q6[4] ; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u16 r0, q7[5] ; CHECK-NEXT: vmov.u16 r0, q7[5]
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q7[6] ; CHECK-NEXT: vmov.u16 r0, q7[6]
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u16 r0, q7[7] ; CHECK-NEXT: vmov.u16 r0, q7[7]
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q2, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov.f32 s2, s19 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vrev32.16 q3, q3
; CHECK-NEXT: vmov.u16 r2, q7[2]
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q7[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vdup.32 q0, r2
; CHECK-NEXT: vmov.u16 r0, q4[4] ; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmov.16 q5[2], r2
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vrev32.16 q7, q7 ; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vrev32.16 q0, q7
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q7[0], r0 ; CHECK-NEXT: vmov.16 q7[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[3] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.f32 s1, s9 ; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q7[1], r0 ; CHECK-NEXT: vmov.16 q7[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q7[6], r0 ; CHECK-NEXT: vmov.16 q7[6], r0
; CHECK-NEXT: vmov.f32 s25, s5 ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.u16 r0, q4[5] ; CHECK-NEXT: vldrw.u32 q2, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s6 ; CHECK-NEXT: vldrw.u32 q3, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vstrw.32 q0, [r1, #80]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.16 q7[7], r0 ; CHECK-NEXT: vmov.16 q7[7], r0
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.f32 s5, s21
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vldrw.u32 q2, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s25, s9
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vstrw.32 q6, [r1]
; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: vmov.f32 s14, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.u16 r2, q1[2]
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vldrw.u32 q2, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[4]
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s5
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.f32 s9, s5 ; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s29, s5
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s18
; CHECK-NEXT: vstrw.32 q6, [r1]
; CHECK-NEXT: vmov.u16 r2, q7[3] ; CHECK-NEXT: vmov.u16 r2, q7[3]
; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.16 q0[3], r2 ; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q7[4] ; CHECK-NEXT: vmov.u16 r2, q7[4]
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.f32 s29, s1 ; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vmov.f32 s30, s2 ; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q7, [r1, #64]
; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vstrw.32 q7, [r1, #16]
; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.u16 r2, q3[3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vstrw.32 q3, [r1, #64]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0 %s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0
%l1 = load <16 x i16>, <16 x i16>* %s1, align 4 %l1 = load <16 x i16>, <16 x i16>* %s1, align 4
%s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1 %s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1
%l2 = load <16 x i16>, <16 x i16>* %s2, align 4 %l2 = load <16 x i16>, <16 x i16>* %s2, align 4
▲ Show 20 Lines • Show All 744 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; f16 ; f16
define void @vst3_v2f16(<2 x half> *%src, <6 x half> *%dst) { define void @vst3_v2f16(<2 x half> *%src, <6 x half> *%dst) {
; CHECK-LABEL: vst3_v2f16: ; CHECK-LABEL: vst3_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldmia r0, {s4, s5} ; CHECK-NEXT: vldmia r0, {s0, s1}
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmovx.f16 s6, s8
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.f32 s13, s8
; CHECK-NEXT: vmovx.f16 s14, s1
; CHECK-NEXT: vins.f16 s14, s6
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s4, s5 ; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov r3, s14
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s8
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: stm r1!, {r0, r2, r3} ; CHECK-NEXT: stm r1!, {r0, r2, r3}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
%s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2 %s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2
Show All 9 Lines
; CHECK-LABEL: vst3_v4f16: ; CHECK-LABEL: vst3_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd lr, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16] ; CHECK-NEXT: ldrd r4, r0, [r0, #16]
; CHECK-NEXT: vmov q0[2], q0[0], lr, r3 ; CHECK-NEXT: vmov q0[2], q0[0], lr, r3
; CHECK-NEXT: vmov q0[3], q0[1], r12, r2
; CHECK-NEXT: vmov.32 q1[0], r4 ; CHECK-NEXT: vmov.32 q1[0], r4
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov q0[3], q0[1], r12, r2
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.32 q1[1], r0 ; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov.16 q2[0], r3
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s2
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmov.f32 s9, s4
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmov.16 q2[6], r0 ; CHECK-NEXT: vmovx.f16 s12, s1
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmov.16 q2[7], r0 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vmovx.f16 s5, s3
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q2[2], r0 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: strd r2, r0, [r1, #16] ; CHECK-NEXT: strd r2, r0, [r1, #16]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
%l3 = load <4 x half>, <4 x half>* %s3, align 4 %l3 = load <4 x half>, <4 x half>* %s3, align 4
%t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x half> %l3, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x half> %l3, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x half> %t1, <8 x half> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x half> %t1, <8 x half> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x half> %s, <12 x half> *%dst store <12 x half> %s, <12 x half> *%dst
ret void ret void
} }
define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) { define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) {
; CHECK-LABEL: vst3_v8f16: ; CHECK-LABEL: vst3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vmovx.f16 s20, s12
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s24, s6
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov.f64 d0, d6
; CHECK-NEXT: vmov.16 q0[0], r3 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov.16 q0[6], r2 ; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vins.f16 s3, s9
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s20, s18
; CHECK-NEXT: vmov r0, s17 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.16 q0[7], r2 ; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmovx.f16 s20, s10
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: vmov.16 q3[3], r2 ; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmovx.f16 s16, s18
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s22
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmovx.f16 s23, s11
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q4[0], r2 ; CHECK-NEXT: vins.f16 s23, s24
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.f32 s22, s7
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmovx.f16 s28, s21
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmovx.f16 s28, s26
; CHECK-NEXT: vmovx.f16 s24, s23 ; CHECK-NEXT: vins.f16 s22, s28
; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vmovx.f16 s28, s13
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vdup.32 q7, r2 ; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vmov.16 q4[7], r0 ; CHECK-NEXT: vins.f16 s4, s28
; CHECK-NEXT: vmov r2, s29 ; CHECK-NEXT: vmovx.f16 s28, s14
; CHECK-NEXT: vmov.f32 s18, s23 ; CHECK-NEXT: vins.f16 s6, s28
; CHECK-NEXT: vmovx.f16 s24, s17 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov.f32 s7, s6
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmovx.f16 s28, s30 ; CHECK-NEXT: vins.f16 s9, s12
; CHECK-NEXT: vmovx.f16 s4, s10 ; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vmov.f32 s1, s13 ; CHECK-NEXT: vins.f16 s6, s12
; CHECK-NEXT: vmov.f32 s2, s14 ; CHECK-NEXT: vmov.f32 s26, s22
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s21, s25
; CHECK-NEXT: vmov.f32 s5, s9
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vmov r0, s28 ; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s28, s9 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vmov r0, s21
; CHECK-NEXT: vmov r2, s28
; CHECK-NEXT: vmov.16 q7[0], r0
; CHECK-NEXT: vmov.16 q7[1], r2
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: vmov.16 q7[6], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q7[7], r0
; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vmov.f32 s29, s21
; CHECK-NEXT: vmov.f32 s30, s10
; CHECK-NEXT: vmovx.f16 s4, s29
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vrev32.16 q2, q1
; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmovx.f16 s8, s10
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov r0, s30
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.f32 s29, s5
; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vstrw.32 q7, [r1, #16]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2 %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
%l3 = load <8 x half>, <8 x half>* %s3, align 4 %l3 = load <8 x half>, <8 x half>* %s3, align 4
%t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x half> %s, <24 x half> *%dst store <24 x half> %s, <24 x half> *%dst
ret void ret void
} }
define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) { define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) {
; CHECK-LABEL: vst3_v16f16: ; CHECK-LABEL: vst3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #144 ; CHECK-NEXT: .pad #144
; CHECK-NEXT: sub sp, #144 ; CHECK-NEXT: sub sp, #144
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s12 ; CHECK-NEXT: vmovx.f16 s0, s12
; CHECK-NEXT: vmov.16 q1[4], r2 ; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q3[2], r3
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vmovx.f16 s20, s14
; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s0, s12
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vins.f16 s3, s13
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.f32 s5, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov r2, s15
; CHECK-NEXT: vins.f16 s17, s0
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vmovx.f16 s0, s18
; CHECK-NEXT: vmov.16 q3[5], r2 ; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s10 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vins.f16 s20, s0
; CHECK-NEXT: vmovx.f16 s0, s11 ; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vmov.16 q1[0], r3 ; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov r3, s23 ; CHECK-NEXT: vmov r2, s27
; CHECK-NEXT: vmov.16 q1[1], r2 ; CHECK-NEXT: vmovx.f16 s23, s15
; CHECK-NEXT: vmov r2, s11 ; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vins.f16 s23, s0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s19 ; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vmovx.f16 s0, s21
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vdup.32 q1, r2
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmov.f32 s6, s19 ; CHECK-NEXT: vins.f16 s22, s0
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s0, s12
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vldrw.u32 q6, [r0, #80]
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q2[2], r3
; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.16 q7[0], r3
; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q4, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q2[5], r2
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.16 q7[1], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d14, d2
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vins.f16 s28, s12
; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: vmov.16 q7[4], r2 ; CHECK-NEXT: vmov.16 q7[4], r2
; CHECK-NEXT: vmov r2, s21 ; CHECK-NEXT: vmov.f32 s8, s9
; CHECK-NEXT: vmov.16 q7[6], r2 ; CHECK-NEXT: vmov.f32 s31, s5
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vins.f16 s31, s13
; CHECK-NEXT: vmovx.f16 s0, s20 ; CHECK-NEXT: vmov.f32 s29, s4
; CHECK-NEXT: vmov.16 q7[7], r2 ; CHECK-NEXT: vdup.32 q1, r0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.f32 s29, s20
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov r0, s30
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmovx.f16 s0, s14
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov q1, q2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vins.f16 s30, s0
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmov q0, q3
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov.f32 s6, s30
; CHECK-NEXT: vmov r2, s23 ; CHECK-NEXT: vmovx.f16 s12, s26
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vins.f16 s4, s12
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmovx.f16 s0, s15
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q0, r2
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmovx.f16 s0, s21
; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s22
; CHECK-NEXT: vmov.16 q4[1], r2
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.f32 s9, s25
; CHECK-NEXT: vmov.f32 s17, s13
; CHECK-NEXT: vldrw.u32 q3, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmovx.f16 s0, s17
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vrev32.16 q0, q1
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.f32 s10, s26
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vldrw.u32 q6, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q2, [r1, #80] ; CHECK-NEXT: vmovx.f16 s7, s3
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vmovx.f16 s12, s27
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s7, s12
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmovx.f16 s0, s13 ; CHECK-NEXT: vmov.f32 s6, s27
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vdup.32 q3, r0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov.f32 s24, s25
; CHECK-NEXT: vmovx.f16 s0, s14 ; CHECK-NEXT: vins.f16 s13, s16
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmovx.f16 s16, s14
; CHECK-NEXT: vmov.16 q5[0], r0 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmovx.f16 s16, s1
; CHECK-NEXT: vmov.16 q5[1], r2 ; CHECK-NEXT: vins.f16 s24, s16
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vmov.f32 s21, s5 ; CHECK-NEXT: vmov.f32 s27, s26
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s22, s14 ; CHECK-NEXT: vmov.f32 s26, s2
; CHECK-NEXT: vmovx.f16 s0, s21 ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovx.f16 s16, s25
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vins.f16 s8, s16
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q3, q0 ; CHECK-NEXT: vmovx.f16 s16, s14
; CHECK-NEXT: vmov r2, s13 ; CHECK-NEXT: vins.f16 s10, s16
; CHECK-NEXT: vmovx.f16 s12, s14 ; CHECK-NEXT: vrev32.16 q4, q0
; CHECK-NEXT: vmov.16 q0[2], r2 ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vmov r0, s22 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vldrw.u32 q3, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s13, s25 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vmov.f32 s14, s26 ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q6, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmov.f32 s25, s5 ; CHECK-NEXT: vldrw.u32 q3, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vstrw.32 q3, [r1] ; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: vmov.f32 s21, s1 ; CHECK-NEXT: vmov.f32 s21, s1
; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s22, s2 ; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s5 ; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vstrw.32 q6, [r1, #32] ; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vmov.f32 s17, s1 ; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vstrw.32 q5, [r1, #16] ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s6 ; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vstrw.32 q7, [r1, #48] ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vstrw.32 q4, [r1, #64] ; CHECK-NEXT: vmov.f32 s25, s1
; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s26, s2
; CHECK-NEXT: vstrw.32 q6, [r1, #64]
; CHECK-NEXT: add sp, #144 ; CHECK-NEXT: add sp, #144
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0 %s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0
%l1 = load <16 x half>, <16 x half>* %s1, align 4 %l1 = load <16 x half>, <16 x half>* %s1, align 4
%s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1 %s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1
%l2 = load <16 x half>, <16 x half>* %s2, align 4 %l2 = load <16 x half>, <16 x half>* %s2, align 4
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llvm/test/CodeGen/Thumb2/mve-vst4.ll

Show First 20 Lines • Show All 416 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vst4_v8i16_align1(<8 x i16> *%src, <32 x i16> *%dst) { define void @vst4_v8i16_align1(<8 x i16> *%src, <32 x i16> *%dst) {
; CHECK-LABEL: vst4_v8i16_align1: ; CHECK-LABEL: vst4_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.u16 r0, q3[2] ; CHECK-NEXT: vmov.f64 d0, d8
; CHECK-NEXT: vmov.u16 r2, q2[2] ; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov.u16 r2, q1[2] ; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vins.f16 s21, s21
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.f32 s12, s17
; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vins.f16 s12, s9
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.f32 s25, s4
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vins.f16 s25, s25
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[6]
; CHECK-NEXT: vmov.f32 s17, s21
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vstrb.8 q4, [r1]
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.16 q6[6], r0 ; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.f32 s13, s21
; CHECK-NEXT: vmov.16 q6[7], r0 ; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vmov.f32 s20, s19
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov.f32 s1, s25
; CHECK-NEXT: vins.f16 s20, s11
; CHECK-NEXT: vmov.f32 s3, s27
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vins.f16 s25, s25
; CHECK-NEXT: vstrb.8 q3, [r1, #16]
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vstrb.8 q0, [r1]
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q5[5], r0 ; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.f32 s21, s25 ; CHECK-NEXT: vmov.f32 s21, s25
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vmov.f64 d12, d9
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vstrb.8 q5, [r1, #48] ; CHECK-NEXT: vstrb.8 q5, [r1, #48]
; CHECK-NEXT: vmov.16 q6[1], r0 ; CHECK-NEXT: vmov.f32 s17, s6
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vins.f16 s24, s10
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[4] ; CHECK-NEXT: vins.f16 s17, s17
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.f32 s25, s9 ; CHECK-NEXT: vmov.f32 s25, s17
; CHECK-NEXT: vmov.f32 s27, s11 ; CHECK-NEXT: vmov.f32 s27, s19
; CHECK-NEXT: vstrb.8 q6, [r1, #32] ; CHECK-NEXT: vstrb.8 q6, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
▲ Show 20 Lines • Show All 549 Lines • ▼ Show 20 Lines
} }
; f16 ; f16
define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) { define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vst4_v2f16: ; CHECK-LABEL: vst4_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldmia r0, {s4, s5} ; CHECK-NEXT: vldmia r0, {s4, s5}
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vins.f16 s0, s5
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vins.f16 s1, s9
; CHECK-NEXT: vmov r0, s9 ; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s8
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s9 ; CHECK-NEXT: vmovx.f16 s4, s9
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vins.f16 s2, s12
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmovx.f16 s3, s8
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
%s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2 %s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2
Show All 10 Lines
define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) { define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vst4_v4f16: ; CHECK-LABEL: vst4_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd lr, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16] ; CHECK-NEXT: ldrd r4, r0, [r0, #16]
; CHECK-NEXT: vmov q1[2], q1[0], lr, r3 ; CHECK-NEXT: vmov q0[2], q0[0], lr, r3
; CHECK-NEXT: vmov q1[3], q1[1], r12, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r12, r2
; CHECK-NEXT: vmov q0[2], q0[0], r4, r4 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r4
; CHECK-NEXT: vmov r3, s5 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov q0[3], q0[1], r0, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r0, r0
; CHECK-NEXT: vmov r2, s7 ; CHECK-NEXT: vins.f16 s8, s3
; CHECK-NEXT: vmov.16 q2[0], r3
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s3 ; CHECK-NEXT: vmovx.f16 s12, s3
; CHECK-NEXT: vmov.16 q2[6], r0 ; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vins.f16 s9, s7
; CHECK-NEXT: vmov.16 q2[7], r0 ; CHECK-NEXT: vmovx.f16 s10, s1
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vins.f16 s11, s12
; CHECK-NEXT: vstrh.16 q2, [r1, #16] ; CHECK-NEXT: vstrh.16 q2, [r1, #16]
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.16 q2[2], r0 ; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s4, s6 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vstrh.16 q2, [r1]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
%l3 = load <4 x half>, <4 x half>* %s3, align 4 %l3 = load <4 x half>, <4 x half>* %s3, align 4
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesentry:
%s = shufflevector <32 x half> %t1, <32 x half> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> %s = shufflevector <32 x half> %t1, <32 x half> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
store <64 x half> %s, <64 x half> *%dst, align 2 store <64 x half> %s, <64 x half> *%dst, align 2
ret void ret void
} }
define void @vst4_v8f16_align1(<8 x half> *%src, <32 x half> *%dst) { define void @vst4_v8f16_align1(<8 x half> *%src, <32 x half> *%dst) {
; CHECK-LABEL: vst4_v8f16_align1: ; CHECK-LABEL: vst4_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12}
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: vldrw.u32 q5, [r0]
; CHECK-NEXT: vldrw.u32 q7, [r0] ; CHECK-NEXT: vmovx.f16 s2, s21
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vins.f16 s21, s17
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vmov.f32 s0, s21
; CHECK-NEXT: vmov r3, s30 ; CHECK-NEXT: vmovx.f16 s4, s17
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmovx.f16 s8, s20
; CHECK-NEXT: vmov.16 q1[0], r3 ; CHECK-NEXT: vmovx.f16 s4, s16
; CHECK-NEXT: vmovx.f16 s0, s30 ; CHECK-NEXT: vins.f16 s20, s16
; CHECK-NEXT: vmov.16 q1[1], r2 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov q1, q5
; CHECK-NEXT: vmovx.f16 s0, s21 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.16 q1[4], r2 ; CHECK-NEXT: vmovx.f16 s10, s23
; CHECK-NEXT: vmov r0, s21 ; CHECK-NEXT: vins.f16 s23, s19
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s12, s19
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmov.f32 s8, s23
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vmovx.f16 s16, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vmovx.f16 s14, s22
; CHECK-NEXT: vmov r2, s29 ; CHECK-NEXT: vins.f16 s22, s18
; CHECK-NEXT: vmov.16 q1[7], r0 ; CHECK-NEXT: vmov.f32 s12, s22
; CHECK-NEXT: vmov.16 q3[0], r2 ; CHECK-NEXT: vins.f16 s14, s16
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov q1, q2 ; CHECK-NEXT: vmov.f32 s13, s18
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmovx.f16 s24, s17
; CHECK-NEXT: vmovx.f16 s0, s29 ; CHECK-NEXT: vins.f16 s17, s17
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vins.f16 s24, s24
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov q5, q4
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s7, s16
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.f32 s23, s24
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vins.f16 s16, s16
; CHECK-NEXT: vmovx.f16 s0, s20 ; CHECK-NEXT: vmov.f32 s5, s16
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmovx.f16 s11, s19
; CHECK-NEXT: vmov r0, s20 ; CHECK-NEXT: vins.f16 s19, s19
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vins.f16 s13, s13
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov.f32 s9, s19
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmovx.f16 s15, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s1, s21
; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vins.f16 s7, s7
; CHECK-NEXT: vmovx.f16 s0, s28 ; CHECK-NEXT: vins.f16 s11, s11
; CHECK-NEXT: vmov.16 q4[7], r0 ; CHECK-NEXT: vins.f16 s15, s15
; CHECK-NEXT: vmov r0, s28 ; CHECK-NEXT: vstrb.8 q2, [r1, #48]
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vstrb.8 q3, [r1, #32]
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s3, s23
; CHECK-NEXT: vmov.16 q6[1], r2 ; CHECK-NEXT: vstrb.8 q1, [r1]
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12}
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmovx.f16 s0, s23
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r2, s31
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmovx.f16 s28, s31
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov r0, s28
; CHECK-NEXT: vmovx.f16 s28, s7
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s28
; CHECK-NEXT: vmovx.f16 s20, s22
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: vmov.16 q7[2], r0
; CHECK-NEXT: vmov.f32 s25, s17
; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vmov.16 q7[6], r0
; CHECK-NEXT: vmovx.f16 s20, s6
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q7[7], r0
; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vldrw.u32 q5, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vmov.f32 s13, s21
; CHECK-NEXT: vmov.f32 s5, s29
; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vmov.f32 s27, s19
; CHECK-NEXT: vstrb.8 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vstrb.8 q6, [r1]
; CHECK-NEXT: vmov.f32 s7, s31
; CHECK-NEXT: vstrb.8 q0, [r1, #48]
; CHECK-NEXT: vstrb.8 q1, [r1, #32]
; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2 %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
%l3 = load <8 x half>, <8 x half>* %s3, align 4 %l3 = load <8 x half>, <8 x half>* %s3, align 4
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