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Differential D95326

[GlobalISel] Implement widenScalar for carry-in add/sub
ClosedPublic

Authored by porglezomp on Jan 24 2021, 6:05 PM.

Details

Reviewers
paquette
aemerson
Commits
rGf22f4557a749: [GlobalISel] Implement widenScalar for carry-in add/sub
Summary

These are widened to a wider UADDE/USUBE, with the overflow value
unused, and with the same synthesis of a new overflow value as for the
O operations.

Diff Detail

Event Timeline

porglezomp created this revision.Jan 24 2021, 6:05 PM
Herald added subscribers: kerbowa, hiraditya, rovka and 2 others. · View Herald TranscriptJan 24 2021, 6:05 PM
porglezomp requested review of this revision.Jan 24 2021, 6:05 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2021, 6:05 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B86494: Diff 318887.Jan 24 2021, 6:06 PM
porglezomp added a parent revision: D95325: [AArch64][GlobalISel] Make G_SADDE and G_SSUBE legal.Jan 24 2021, 6:06 PM
porglezomp updated this revision to Diff 319063.Jan 25 2021, 10:55 AM

Update tests to match run-line changes

Harbormaster completed remote builds in B86602: Diff 319063.Jan 25 2021, 10:56 AM
arsenm added a subscriber: arsenm.Jan 25 2021, 11:08 AM
arsenm added inline comments.
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1768

Should just use a plain Register here, MachineOperand values are generally bad

1817–1818

This is .getReg(0)

porglezomp updated this revision to Diff 319072.Jan 25 2021, 11:36 AM

Change MachineOperand variable to Register, use getReg(0) on MachineInstrBuilder

Harbormaster completed remote builds in B86605: Diff 319072.Jan 25 2021, 11:37 AM
porglezomp updated this revision to Diff 319228.Jan 26 2021, 12:35 AM

Add unit-tests in LegalizerHelperTest

Harbormaster completed remote builds in B86684: Diff 319228.Jan 26 2021, 1:30 AM
paquette added inline comments.Jan 26 2021, 9:59 AM
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1769

Can you add an unreachable case to make sure nobody passes an unexpected instruction here?

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
5

Can these testcases have slightly more descriptive names?

32

Nit: we can give virtual registers names, and it usually makes it way easier to read + understand testcases (IMO).

Since the new testcases here are all pretty similar, do you think you could add names to the virtual registers?

porglezomp updated this revision to Diff 319633.Jan 27 2021, 11:19 AM

Add unreachable case, give vregs names in tests

Harbormaster completed remote builds in B86886: Diff 319633.Jan 27 2021, 12:39 PM
paquette accepted this revision.Jan 28 2021, 9:45 AM

LGTM

This revision is now accepted and ready to land.Jan 28 2021, 9:45 AM
This revision was landed with ongoing or failed builds.Jan 28 2021, 2:06 PM
Closed by commit rGf22f4557a749: [GlobalISel] Implement widenScalar for carry-in add/sub (authored by porglezomp). · Explain Why
This revision was automatically updated to reflect the committed changes.
porglezomp added a commit: rGf22f4557a749: [GlobalISel] Implement widenScalar for carry-in add/sub.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
4 lines
lib/
CodeGen/
GlobalISel/
75 lines
test/
CodeGen/
AArch64/
GlobalISel/
34 lines
34 lines
35 lines
35 lines
AMDGPU/
GlobalISel/
17 lines
17 lines
18 lines
18 lines

Diff 318887

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Linesprivate:
LegalizeResult LegalizeResult
widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx, LegalizeResult widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy); LLT WideTy);
LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy); LLT WideTy);
/// Helper function to split a wide generic register into bitwise blocks with /// Helper function to split a wide generic register into bitwise blocks with
/// the given Type (which implies the number of blocks needed). The generic /// the given Type (which implies the number of blocks needed). The generic
/// registers created are appended to Ops, starting at bit 0 of Reg. /// registers created are appended to Ops, starting at bit 0 of Reg.
void extractParts(Register Reg, LLT Ty, int NumParts, void extractParts(Register Reg, LLT Ty, int NumParts,
SmallVectorImpl<Register> &VRegs); SmallVectorImpl<Register> &VRegs);
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 1,752 Lines • ▼ Show 20 LinesLegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
LegalizerHelper::widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx, LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy) { LLT WideTy) {
if (TypeIdx == 1) if (TypeIdx == 1)
return UnableToLegalize; // TODO return UnableToLegalize; // TODO
unsigned Op = MI.getOpcode();
unsigned Opcode = Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_SADDO unsigned Opcode;
? TargetOpcode::G_ADD unsigned ExtOpcode;
: TargetOpcode::G_SUB; Optional<MachineOperand> CarryIn = None;
arsenmUnsubmitted
Not Done
ReplyInline Actions

Should just use a plain Register here, MachineOperand values are generally bad

arsenm: Should just use a plain Register here, MachineOperand values are generally bad
unsigned ExtOpcode = switch (MI.getOpcode()) {
paquetteUnsubmitted
Not Done
ReplyInline Actions
Optional<Register> CarryIn = None;
switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Unexpected opcode!");
case TargetOpcode::G_SADDO:

Can you add an unreachable case to make sure nobody passes an unexpected instruction here?

paquette: Can you add an unreachable case to make sure nobody passes an unexpected instruction here?
Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_USUBO case TargetOpcode::G_SADDO:
? TargetOpcode::G_ZEXT Opcode = TargetOpcode::G_ADD;
: TargetOpcode::G_SEXT; ExtOpcode = TargetOpcode::G_SEXT;
break;
case TargetOpcode::G_SSUBO:
Opcode = TargetOpcode::G_SUB;
ExtOpcode = TargetOpcode::G_SEXT;
break;
case TargetOpcode::G_UADDO:
Opcode = TargetOpcode::G_ADD;
ExtOpcode = TargetOpcode::G_ZEXT;
break;
case TargetOpcode::G_USUBO:
Opcode = TargetOpcode::G_SUB;
ExtOpcode = TargetOpcode::G_ZEXT;
break;
case TargetOpcode::G_SADDE:
Opcode = TargetOpcode::G_UADDE;
ExtOpcode = TargetOpcode::G_SEXT;
CarryIn = MI.getOperand(4);
break;
case TargetOpcode::G_SSUBE:
Opcode = TargetOpcode::G_USUBE;
ExtOpcode = TargetOpcode::G_SEXT;
CarryIn = MI.getOperand(4);
break;
case TargetOpcode::G_UADDE:
Opcode = TargetOpcode::G_UADDE;
ExtOpcode = TargetOpcode::G_ZEXT;
CarryIn = MI.getOperand(4);
break;
case TargetOpcode::G_USUBE:
Opcode = TargetOpcode::G_USUBE;
ExtOpcode = TargetOpcode::G_ZEXT;
CarryIn = MI.getOperand(4);
break;
}
auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)});
auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)});
// Do the arithmetic in the larger type. // Do the arithmetic in the larger type.
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}); Register NewOp;
if (CarryIn) {
LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg());
NewOp = MIRBuilder
.buildInstr(Opcode, {WideTy, CarryOutTy},
{LHSExt, RHSExt, *CarryIn})
->getOperand(0)
.getReg();
arsenmUnsubmitted
Not Done
ReplyInline Actions

This is .getReg(0)

arsenm: This is .getReg(0)
} else {
NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt})
->getOperand(0)
.getReg();
}
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp);
auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp});
// There is no overflow if the ExtOp is the same as NewOp. // There is no overflow if the ExtOp is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
// Now trunc the NewOp to the original result. // Now trunc the NewOp to the original result.
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
MI.eraseFromParent(); MI.eraseFromParent();
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 LinesLegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_MERGE_VALUES: case TargetOpcode::G_MERGE_VALUES:
return widenScalarMergeValues(MI, TypeIdx, WideTy); return widenScalarMergeValues(MI, TypeIdx, WideTy);
case TargetOpcode::G_UNMERGE_VALUES: case TargetOpcode::G_UNMERGE_VALUES:
return widenScalarUnmergeValues(MI, TypeIdx, WideTy); return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
case TargetOpcode::G_SADDO: case TargetOpcode::G_SADDO:
case TargetOpcode::G_SSUBO: case TargetOpcode::G_SSUBO:
case TargetOpcode::G_UADDO: case TargetOpcode::G_UADDO:
case TargetOpcode::G_USUBO: case TargetOpcode::G_USUBO:
return widenScalarAddoSubo(MI, TypeIdx, WideTy); case TargetOpcode::G_SADDE:
case TargetOpcode::G_SSUBE:
case TargetOpcode::G_UADDE:
case TargetOpcode::G_USUBE:
return widenScalarAddSubOverflow(MI, TypeIdx, WideTy);
case TargetOpcode::G_SADDSAT: case TargetOpcode::G_SADDSAT:
case TargetOpcode::G_SSUBSAT: case TargetOpcode::G_SSUBSAT:
case TargetOpcode::G_SSHLSAT: case TargetOpcode::G_SSHLSAT:
case TargetOpcode::G_UADDSAT: case TargetOpcode::G_UADDSAT:
case TargetOpcode::G_USUBSAT: case TargetOpcode::G_USUBSAT:
case TargetOpcode::G_USHLSAT: case TargetOpcode::G_USHLSAT:
return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); return widenScalarAddSubShlSat(MI, TypeIdx, WideTy);
case TargetOpcode::G_CTTZ: case TargetOpcode::G_CTTZ:
▲ Show 20 Lines • Show All 4,399 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_scalar_sadde_small
paquetteUnsubmitted
Not Done
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# RUN: llc -mtriple aarch64 -verify-machineinstrs -run-pass=legalizer -debugify-and-strip-all-safe %s -o - | FileCheck %s
---
- name: test_scalar_sadde_small
+ name: widen_scalar_sadde_s8
body: |

Can these testcases have slightly more descriptive names?

paquette: Can these testcases have slightly more descriptive names?
body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_sadde_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC2]], 8
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[TRUNC]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UADDE]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s8) = G_TRUNC %0(s64)
%4:_(s8) = G_TRUNC %1(s64)
%5:_(s1) = G_TRUNC %2(s64)
%6:_(s8), %7:_(s1) = G_SADDE %3, %4, %5
%8:_(s64) = G_ANYEXT %6(s8)
paquetteUnsubmitted
Not Done
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%4:_(s8) = G_TRUNC %1(s64)
- %5:_(s1) = G_TRUNC %2(s64)
+ %carry_in:_(s1) = G_TRUNC %2(s64)
%6:_(s8), %7:_(s1) = G_SADDE %3, %4, %5

Nit: we can give virtual registers names, and it usually makes it way easier to read + understand testcases (IMO).

Since the new testcases here are all pretty similar, do you think you could add names to the virtual registers?

paquette: Nit: we can give virtual registers names, and it usually makes it way easier to read +…
%9:_(s64) = G_ANYEXT %7(s1)
$x0 = COPY %8(s64)
$x1 = COPY %9(s64)
...
---
name: test_scalar_sadde_32 name: test_scalar_sadde_32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_scalar_sadde_32 ; CHECK-LABEL: name: test_scalar_sadde_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
Show All 14 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_scalar_ssube_small
body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_ssube_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC2]], 8
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[TRUNC]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[USUBE]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s8) = G_TRUNC %0(s64)
%4:_(s8) = G_TRUNC %1(s64)
%5:_(s1) = G_TRUNC %2(s64)
%6:_(s8), %7:_(s1) = G_SSUBE %3, %4, %5
%8:_(s64) = G_ANYEXT %6(s8)
%9:_(s64) = G_ANYEXT %7(s1)
$x0 = COPY %8(s64)
$x1 = COPY %9(s64)
...
---
name: test_scalar_ssube_32 name: test_scalar_ssube_32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_scalar_ssube_32 ; CHECK-LABEL: name: test_scalar_ssube_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
Show All 14 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_scalar_uadde_small
body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_uadde_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], [[TRUNC]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UADDE]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s8) = G_TRUNC %0(s64)
%4:_(s8) = G_TRUNC %1(s64)
%5:_(s1) = G_TRUNC %2(s64)
%6:_(s8), %7:_(s1) = G_UADDE %3, %4, %5
%8:_(s64) = G_ANYEXT %6(s8)
%9:_(s64) = G_ANYEXT %7(s1)
$x0 = COPY %8(s64)
$x1 = COPY %9(s64)
...
---
name: test_scalar_uadde_32 name: test_scalar_uadde_32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_scalar_uadde_32 ; CHECK-LABEL: name: test_scalar_uadde_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
Show All 14 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_scalar_usube_small
body: |
bb.0.entry:
; CHECK-LABEL: name: test_scalar_usube_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], [[TRUNC]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[USUBE]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s8) = G_TRUNC %0(s64)
%4:_(s8) = G_TRUNC %1(s64)
%5:_(s1) = G_TRUNC %2(s64)
%6:_(s8), %7:_(s1) = G_USUBE %3, %4, %5
%8:_(s64) = G_ANYEXT %6(s8)
%9:_(s64) = G_ANYEXT %7(s1)
$x0 = COPY %8(s64)
$x1 = COPY %9(s64)
...
---
name: test_scalar_usube_32 name: test_scalar_usube_32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_scalar_usube_32 ; CHECK-LABEL: name: test_scalar_usube_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_sadde_s16 ; CHECK-LABEL: name: test_sadde_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[SADDE:%[0-9]+]]:_(s16), [[SADDE1:%[0-9]+]]:_(s1) = G_SADDE [[TRUNC1]], [[SADDE]], [[ICMP]] ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDE]](s16) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SADDE1]](s1) ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[ICMP]]
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0 %3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3 %4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s16) = G_TRUNC %0 %5:_(s16) = G_TRUNC %0
%6:_(s16) = G_TRUNC %1 %6:_(s16) = G_TRUNC %1
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_ssube_s16 ; CHECK-LABEL: name: test_ssube_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[SSUBE:%[0-9]+]]:_(s16), [[SSUBE1:%[0-9]+]]:_(s1) = G_SSUBE [[TRUNC1]], [[SSUBE]], [[ICMP]] ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBE]](s16) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SSUBE1]](s1) ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[ICMP]]
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0 %3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3 %4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s16) = G_TRUNC %0 %5:_(s16) = G_TRUNC %0
%6:_(s16) = G_TRUNC %1 %6:_(s16) = G_TRUNC %1
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_uadde_s16 ; CHECK-LABEL: name: test_uadde_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[UADDE:%[0-9]+]]:_(s16), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[TRUNC1]], [[UADDE]], [[ICMP]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDE]](s16) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDE1]](s1) ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], [[ICMP]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0 %3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3 %4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s16) = G_TRUNC %0 %5:_(s16) = G_TRUNC %0
%6:_(s16) = G_TRUNC %1 %6:_(s16) = G_TRUNC %1
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_usube_s16 ; CHECK-LABEL: name: test_usube_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[USUBE:%[0-9]+]]:_(s16), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[TRUNC1]], [[USUBE]], [[ICMP]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBE]](s16) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBE1]](s1) ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], [[ICMP]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0 %3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3 %4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s16) = G_TRUNC %0 %5:_(s16) = G_TRUNC %0
%6:_(s16) = G_TRUNC %1 %6:_(s16) = G_TRUNC %1
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines