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Differential D95115

[PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and Tests
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Authored by amyk on Jan 20 2021, 10:56 PM.

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power-llvm-team
nemanjai
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rGba627a32e125: [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and…
Summary

This patch includes the following updates to the load/store refactoring effort introduced in D93370:

  • Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible)
  • Update pattern and test case for the LXVD2X/STXVD2X intrinsics
  • Update LIT test cases that use to use the XForm instruction to use the DForm instruction

Depends on D93370 and D105661

Diff Detail

Event Timeline

amyk created this revision.Jan 20 2021, 10:56 PM
Herald added subscribers: shchenz, hiraditya, qcolombet. · View Herald TranscriptJan 20 2021, 10:56 PM
amyk requested review of this revision.Jan 20 2021, 10:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2021, 10:56 PM
amyk added a child revision: D95116: [PowerPC] Update PC-Relative Load/Store Patterns to use the refactored Load/Store Implementation.Jan 20 2021, 11:01 PM
Harbormaster completed remote builds in B86044: Diff 318113.Jan 21 2021, 1:11 AM
amyk updated this revision to Diff 319727.Jan 27 2021, 6:11 PM

Rebase patch and also add additional handling for frame index (if the frame index is not aligned, match to an XForm instruction).

Harbormaster completed remote builds in B86937: Diff 319727.Jan 27 2021, 6:50 PM
amyk updated this revision to Diff 322977.Feb 11 2021, 6:03 AM
  • Rebase the patch with the latest trunk.
  • Updated alignment checks for the frame index.
Harbormaster completed remote builds in B88796: Diff 322977.Feb 11 2021, 6:56 AM
amyk updated this revision to Diff 323859.Feb 15 2021, 6:04 PM

Update patch based on dependent patch changes.

Harbormaster completed remote builds in B89299: Diff 323859.Feb 15 2021, 7:10 PM
NeHuang added a subscriber: NeHuang.Feb 19 2021, 8:19 AM
NeHuang added inline comments.
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
16647 ↗(On Diff #323859)

nit: remove duplicate only

16657 ↗(On Diff #323859)

nit: double check if the frame index is aligned

amyk updated this revision to Diff 330638.EditedMar 15 2021, 6:42 AM

Update patch based on dependent patch (D93370), update newly added test cases, address review on comment updates.

Harbormaster completed remote builds in B93802: Diff 330638.Mar 15 2021, 6:51 AM
nemanjai requested changes to this revision.Mar 22 2021, 5:04 AM

It is really nice to see us getting rid of all these unnecessary X-Forms in so many test cases. But I think the patch needs a bit more tweaking.

Also, it seems that if we commit the first patch in this series before we commit this one, there is a possibility of emitting an impossible DSForm/DQForm instruction (since the alignment check for the FI is only added here). Can you explain why that is not the case? I think for DQ-Form it is because we only produce DQ-Forms starting with this patch, but I think it is possibly a problem with DS-Form.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp
16812 ↗(On Diff #330638)

Similarly to my comment on the other lambda in the first patch in the series, please turn this lambda into a static function. Also, the name is not appropriate. If a function is named as a query, it should be a query - calling IsFrameIndexAligned() seems like the caller is asking a question and would expect an answer.
Perhaps setAlignFlagsForFI()?

16814 ↗(On Diff #330638)

How about if the address is computed using OR? I am fairly certain that the original code handles this case.

16819 ↗(On Diff #330638)

A comment explaining something like this seems appropriate:

If this is (add $FI, $S16Imm), the alignment flags are already set based on the immediate. We just need to clear the alignment flags if the FI alignment is weaker.
16824 ↗(On Diff #330638)
// If the address is a plain FrameIndex, set alignment flags based on FI alignment.
16939 ↗(On Diff #330638)

I don't really follow why we need this at all. This function is meant to set the flags. This preemptive look at which addressing mode we will produce for the flags we computed so far seems out of place.
Presumably simply calling IsFrameIndexAligned(N) ensure that PPC::MOF_RPlusSImm16Mult4/FlagSet & PPC::MOF_RPlusSImm16Mult16 are not set on unaligned frame indices. And presumably, if those flags are not set, we'd never try to match AM_DSForm/AM_DQForm and would simply fall back to AM_XForm. It might help if you provide a test case that requires this code.

This revision now requires changes to proceed.Mar 22 2021, 5:04 AM
amyk updated this revision to Diff 333292.Mar 25 2021, 6:59 AM
amyk marked 4 inline comments as done.
amyk edited the summary of this revision. (Show Details)
  • Moved setting FrameIndex alignment flags implementation to D93370 (with added comments from Nemanja's review)
Harbormaster completed remote builds in B95687: Diff 333292.Mar 25 2021, 6:59 AM
amyk updated this revision to Diff 338418.Apr 18 2021, 7:48 PM
  • Rebase patch in order to update test cases
Harbormaster completed remote builds in B99411: Diff 338418.Apr 18 2021, 9:04 PM
nemanjai accepted this revision.May 7 2021, 6:26 AM

LGTM. This turned out very nice.

This revision is now accepted and ready to land.May 7 2021, 6:26 AM
amyk updated this revision to Diff 357347.Jul 8 2021, 2:30 PM
amyk mentioned this in D105661: [PowerPC] Add frame index alignment check if the the addressing mode is DS/DQ-Form, and fall back to X-Form if necessary..
amyk edited the summary of this revision. (Show Details)
amyk added a parent revision: D105661: [PowerPC] Add frame index alignment check if the the addressing mode is DS/DQ-Form, and fall back to X-Form if necessary..

Rebase patch based on D105661.

Harbormaster completed remote builds in B113095: Diff 357347.Jul 8 2021, 4:10 PM
nemanjai added a comment.Jul 16 2021, 6:01 AM

Is there anything additional I should be reviewing here? Were there any changes required when rebasing that you need me to look at specifically?

Closed by commit rGba627a32e125: [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and… (authored by amyk). · Explain WhyJul 16 2021, 7:29 AM
This revision was automatically updated to reflect the committed changes.
amyk added a commit: rGba627a32e125: [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and….
amyk added a comment.Jul 16 2021, 7:30 AM
In D95115#2882979, @nemanjai wrote:

Is there anything additional I should be reviewing here? Were there any changes required when rebasing that you need me to look at specifically?

Sorry Nemanja, I just seen this. This patch didn't change, I just needed to commit it (which I just did). Thanks.

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Diff 333292

llvm/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Lines def LXSDX : XX1Form_memOp<31, 588,
(outs vsfrc:$XT), (ins memrr:$src), (outs vsfrc:$XT), (ins memrr:$src),
"lxsdx $XT, $src", IIC_LdStLFD, "lxsdx $XT, $src", IIC_LdStLFD,
[]>; []>;
// Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
let CodeSize = 3 in let CodeSize = 3 in
def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#XFLOADf64", "#XFLOADf64",
[(set f64:$XT, (load ForceXForm:$src))]>; [(set f64:$XT, (load XForm:$src))]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in let Predicates = [HasVSX, HasOnlySwappingMemOps] in
def LXVD2X : XX1Form_memOp<31, 844, def LXVD2X : XX1Form_memOp<31, 844,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins memrr:$src),
"lxvd2x $XT, $src", IIC_LdStLFD, "lxvd2x $XT, $src", IIC_LdStLFD,
[(set v2f64:$XT, (int_ppc_vsx_lxvd2x ForceXForm:$src))]>; []>;
def LXVDSX : XX1Form_memOp<31, 332, def LXVDSX : XX1Form_memOp<31, 332,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins memrr:$src),
"lxvdsx $XT, $src", IIC_LdStLFD, []>; "lxvdsx $XT, $src", IIC_LdStLFD, []>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in let Predicates = [HasVSX, HasOnlySwappingMemOps] in
def LXVW4X : XX1Form_memOp<31, 780, def LXVW4X : XX1Form_memOp<31, 780,
(outs vsrc:$XT), (ins memrr:$src), (outs vsrc:$XT), (ins memrr:$src),
"lxvw4x $XT, $src", IIC_LdStLFD, "lxvw4x $XT, $src", IIC_LdStLFD,
[]>; []>;
} // mayLoad } // mayLoad
// Store indexed instructions // Store indexed instructions
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def STXSDX : XX1Form_memOp<31, 716, def STXSDX : XX1Form_memOp<31, 716,
(outs), (ins vsfrc:$XT, memrr:$dst), (outs), (ins vsfrc:$XT, memrr:$dst),
"stxsdx $XT, $dst", IIC_LdStSTFD, "stxsdx $XT, $dst", IIC_LdStSTFD,
[]>; []>;
// Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
let CodeSize = 3 in let CodeSize = 3 in
def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
"#XFSTOREf64", "#XFSTOREf64",
[(store f64:$XT, ForceXForm:$dst)]>; [(store f64:$XT, XForm:$dst)]>;
let Predicates = [HasVSX, HasOnlySwappingMemOps] in { let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
// The behaviour of this instruction is endianness-specific so we provide no // The behaviour of this instruction is endianness-specific so we provide no
// pattern to match it without considering endianness. // pattern to match it without considering endianness.
def STXVD2X : XX1Form_memOp<31, 972, def STXVD2X : XX1Form_memOp<31, 972,
(outs), (ins vsrc:$XT, memrr:$dst), (outs), (ins vsrc:$XT, memrr:$dst),
"stxvd2x $XT, $dst", IIC_LdStSTFD, "stxvd2x $XT, $dst", IIC_LdStSTFD,
[]>; []>;
▲ Show 20 Lines • Show All 762 Lines • ▼ Show 20 Lines def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
"lxsiwax $XT, $src", IIC_LdStLFD, []>; "lxsiwax $XT, $src", IIC_LdStLFD, []>;
def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
"lxsiwzx $XT, $src", IIC_LdStLFD, []>; "lxsiwzx $XT, $src", IIC_LdStLFD, []>;
// Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later
let CodeSize = 3 in let CodeSize = 3 in
def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),
"#XFLOADf32", "#XFLOADf32",
[(set f32:$XT, (load ForceXForm:$src))]>; [(set f32:$XT, (load XForm:$src))]>;
// Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later
def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#LIWAX", "#LIWAX",
[(set f64:$XT, (PPClfiwax ForceXForm:$src))]>; [(set f64:$XT, (PPClfiwax ForceXForm:$src))]>;
// Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later
def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#LIWZX", "#LIWZX",
[(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>; [(set f64:$XT, (PPClfiwzx ForceXForm:$src))]>;
} // mayLoad } // mayLoad
// VSX scalar stores introduced in ISA 2.07 // VSX scalar stores introduced in ISA 2.07
let mayStore = 1, mayLoad = 0 in { let mayStore = 1, mayLoad = 0 in {
let CodeSize = 3 in let CodeSize = 3 in
def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
"stxsspx $XT, $dst", IIC_LdStSTFD, []>; "stxsspx $XT, $dst", IIC_LdStSTFD, []>;
def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
"stxsiwx $XT, $dst", IIC_LdStSTFD, []>; "stxsiwx $XT, $dst", IIC_LdStSTFD, []>;
// Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later
let CodeSize = 3 in let CodeSize = 3 in
def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),
"#XFSTOREf32", "#XFSTOREf32",
[(store f32:$XT, ForceXForm:$dst)]>; [(store f32:$XT, XForm:$dst)]>;
// Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later
def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
"#STIWX", "#STIWX",
[(PPCstfiwx f64:$XT, ForceXForm:$dst)]>; [(PPCstfiwx f64:$XT, ForceXForm:$dst)]>;
} // mayStore } // mayStore
// VSX Elementary Scalar FP arithmetic (SP) // VSX Elementary Scalar FP arithmetic (SP)
let mayRaiseFPException = 1 in { let mayRaiseFPException = 1 in {
▲ Show 20 Lines • Show All 1,257 Lines • ▼ Show 20 Lines
// Predicate combinations available: // Predicate combinations available:
// [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr. // [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr.
// [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr. // [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr.
// [HasVSX] // [HasVSX]
// [HasVSX, IsBigEndian] // [HasVSX, IsBigEndian]
// [HasVSX, IsLittleEndian] // [HasVSX, IsLittleEndian]
// [HasVSX, NoP9Vector] // [HasVSX, NoP9Vector]
// [HasVSX, NoP9Vector, IsLittleEndian] // [HasVSX, NoP9Vector, IsLittleEndian]
// [HasVSX, NoP9Vector, IsBigEndian]
// [HasVSX, HasOnlySwappingMemOps] // [HasVSX, HasOnlySwappingMemOps]
// [HasVSX, HasOnlySwappingMemOps, IsBigEndian] // [HasVSX, HasOnlySwappingMemOps, IsBigEndian]
// [HasVSX, HasP8Vector] // [HasVSX, HasP8Vector]
// [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] // [HasVSX, HasP8Vector, IsBigEndian, IsPPC64]
// [HasVSX, HasP8Vector, IsLittleEndian] // [HasVSX, HasP8Vector, IsLittleEndian]
// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64] // [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64]
// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] // [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian]
// [HasVSX, HasDirectMove] // [HasVSX, HasDirectMove]
▲ Show 20 Lines • Show All 604 Lines • ▼ Show 20 Linesdefm : ScalToVecWPermute<
(XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
(SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
defm : ScalToVecWPermute< defm : ScalToVecWPermute<
v2f64, (f64 (load ForceXForm:$src)), v2f64, (f64 (load ForceXForm:$src)),
(XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
(SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
} // HasVSX, NoP9Vector, IsLittleEndian } // HasVSX, NoP9Vector, IsLittleEndian
let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in {
def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)),
(LXVD2X ForceXForm:$src)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
(STXVD2X $rS, ForceXForm:$dst)>;
} // HasVSX, NoP9Vector, IsBigEndian
// Any VSX subtarget that only has loads and stores that load in big endian // Any VSX subtarget that only has loads and stores that load in big endian
// order regardless of endianness. This is really pre-Power9 subtargets. // order regardless of endianness. This is really pre-Power9 subtargets.
let Predicates = [HasVSX, HasOnlySwappingMemOps] in { let Predicates = [HasVSX, HasOnlySwappingMemOps] in {
def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
// Stores. // Stores.
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
(STXVD2X $rS, ForceXForm:$dst)>;
def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
} // HasVSX, HasOnlySwappingMemOps } // HasVSX, HasOnlySwappingMemOps
// Big endian VSX subtarget that only has loads and stores that always // Big endian VSX subtarget that only has loads and stores that always
// load in big endian order. Really big endian pre-Power9 subtargets. // load in big endian order. Really big endian pre-Power9 subtargets.
let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in {
def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; def : Pat<(v2f64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; def : Pat<(v2i64 (load ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; def : Pat<(v4i32 (load ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>; def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; def : Pat<(store v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; def : Pat<(store v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>; def : Pat<(store v4i32:$XT, ForceXForm:$dst), (STXVW4X $XT, ForceXForm:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst),
(STXVW4X $rS, ForceXForm:$dst)>; (STXVW4X $rS, ForceXForm:$dst)>;
} // HasVSX, HasOnlySwappingMemOps, IsBigEndian } // HasVSX, HasOnlySwappingMemOps, IsBigEndian
// Any Power8 VSX subtarget. // Any Power8 VSX subtarget.
let Predicates = [HasVSX, HasP8Vector] in { let Predicates = [HasVSX, HasP8Vector] in {
def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
(XXLEQV $A, $B)>; (XXLEQV $A, $B)>;
def : Pat<(f64 (extloadf32 ForceXForm:$src)), def : Pat<(f64 (extloadf32 XForm:$src)),
(COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$src), VSFRC)>; (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>;
def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))), def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))),
(f32 (XFLOADf32 ForceXForm:$src))>; (f32 (XFLOADf32 ForceXForm:$src))>;
def : Pat<(f64 (any_fpextend f32:$src)), def : Pat<(f64 (any_fpextend f32:$src)),
(COPY_TO_REGCLASS $src, VSFRC)>; (COPY_TO_REGCLASS $src, VSFRC)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
(SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
▲ Show 20 Lines • Show All 604 Lines • ▼ Show 20 Lines
// Vector Reverse // Vector Reverse
def : Pat<(v8i16 (bswap v8i16 :$A)), def : Pat<(v8i16 (bswap v8i16 :$A)),
(v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
def : Pat<(v1i128 (bswap v1i128 :$A)), def : Pat<(v1i128 (bswap v1i128 :$A)),
(v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
// D-Form Load/Store // D-Form Load/Store
def : Pat<(v4i32 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; foreach Ty = [v4i32, v4f32, v2i64, v2f64] in {
def : Pat<(v4f32 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>;
def : Pat<(v2i64 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>;
def : Pat<(v2f64 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>;
def : Pat<(f128 (quadwOffsetLoad DQForm:$src)), def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>;
}
def : Pat<(f128 (load DQForm:$src)),
(COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>;
def : Pat<(f128 (load XForm:$src)),
(COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>;
def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>;
def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>;
def : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>;
def : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>;
def : Pat<(quadwOffsetStore v4f32:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; def : Pat<(store f128:$rS, DQForm:$dst),
def : Pat<(quadwOffsetStore v4i32:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>;
def : Pat<(quadwOffsetStore v2f64:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>;
def : Pat<(quadwOffsetStore f128:$rS, DQForm:$dst),
(STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>;
def : Pat<(quadwOffsetStore v2i64:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; def : Pat<(store f128:$rS, XForm:$dst),
(STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst), def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst),
(STXV $rS, memrix16:$dst)>; (STXV $rS, memrix16:$dst)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst), def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst),
(STXV $rS, memrix16:$dst)>; (STXV $rS, memrix16:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst),
def : Pat<(v2f64 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; (STXVX $rS, XForm:$dst)>;
def : Pat<(v2i64 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst),
def : Pat<(v4f32 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; (STXVX $rS, XForm:$dst)>;
def : Pat<(v4i32 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>;
def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVX ForceXForm:$src)>;
def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)), (LXVX ForceXForm:$src)>;
def : Pat<(f128 (nonQuadwOffsetLoad ForceXForm:$src)),
(COPY_TO_REGCLASS (LXVX ForceXForm:$src), VRRC)>;
def : Pat<(nonQuadwOffsetStore f128:$rS, ForceXForm:$dst),
(STXVX (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;
def : Pat<(nonQuadwOffsetStore v2f64:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
def : Pat<(nonQuadwOffsetStore v2i64:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
def : Pat<(nonQuadwOffsetStore v4f32:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
def : Pat<(nonQuadwOffsetStore v4i32:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
(STXVX $rS, ForceXForm:$dst)>;
// Build vectors from i8 loads // Build vectors from i8 loads
defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8, defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
(VSPLTHs 3, (LXSIBZX ForceXForm:$src)), (VSPLTHs 3, (LXSIBZX ForceXForm:$src)),
(VSPLTHs 3, (LXSIBZX ForceXForm:$src))>; (VSPLTHs 3, (LXSIBZX ForceXForm:$src))>;
defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8, defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
(XXSPLTWs (LXSIBZX ForceXForm:$src), 1), (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),
(XXSPLTWs (LXSIBZX ForceXForm:$src), 1)>; (XXSPLTWs (LXSIBZX ForceXForm:$src), 1)>;
▲ Show 20 Lines • Show All 990 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/PR33671.ll

Show All 19 Linesentry:
%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1 %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
%0 = bitcast i32* %arrayidx to <4 x i32>* %0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>* %1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 16 %2 = load <4 x i32>, <4 x i32>* %1, align 16
store <4 x i32> %2, <4 x i32>* %0, align 16 store <4 x i32> %2, <4 x i32>* %0, align 16
ret void ret void
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
; CHECK: addi 3, 3, 8 ; CHECK: li [[REG:[0-9]+]], 8
; CHECK: addi [[REG:[0-9]+]], 4, 4 ; CHECK: lxvx [[LD:[0-9]+]], 3, [[REG]]
; CHECK: lxvx [[LD:[0-9]+]], 0, 3 ; CHECK: li [[REG2:[0-9]+]], 4
; CHECK: stxvx [[LD]], 0, [[REG]] ; CHECK: stxvx [[LD]], 4, [[REG2]]
} }

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

Show All 23 Lines
; CHECK-P8: stfsx f0, r3, r4 ; CHECK-P8: stfsx f0, r3, r4
; CHECK-P8: blr ; CHECK-P8: blr
; ;
; CHECK-P9-LABEL: testExpandPostRAPseudo: ; CHECK-P9-LABEL: testExpandPostRAPseudo:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r4, r2, .LC0@toc@ha ; CHECK-P9: addis r4, r2, .LC0@toc@ha
; CHECK-P9: lxvwsx vs0, 0, r3 ; CHECK-P9: lxvwsx vs0, 0, r3
; CHECK-P9: ld r4, .LC0@toc@l(r4) ; CHECK-P9: ld r4, .LC0@toc@l(r4)
; CHECK-P9: stxvx vs0, 0, r4 ; CHECK-P9: stxv vs0, 0(r4)
; CHECK-P9: lis r4, 1024 ; CHECK-P9: lis r4, 1024
; CHECK-P9: lfiwax f0, 0, r3 ; CHECK-P9: lfiwax f0, 0, r3
; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: xscvsxdsp f0, f0 ; CHECK-P9: xscvsxdsp f0, f0
; CHECK-P9: ld r3, 0(r3) ; CHECK-P9: ld r3, 0(r3)
; CHECK-P9: stfsx f0, r3, r4 ; CHECK-P9: stfsx f0, r3, r4
; CHECK-P9: blr ; CHECK-P9: blr
Show All 13 Lines

llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll

Show All 35 Lines
; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR32: - { id: 1, type: default, offset: 152, size: 4, alignment: 8, stack-id: default, ; MIR32: - { id: 1, type: default, offset: 152, size: 4, alignment: 8, stack-id: default,
; MIR32: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, ; MIR32: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR32: - { id: 2, type: default, offset: 48, size: 16, alignment: 16, stack-id: default, ; MIR32: - { id: 2, type: default, offset: 48, size: 16, alignment: 16, stack-id: default,
; MIR32: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, ; MIR32: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR32: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR32: renamable $[[GPR1:r[0-9]+]] = ADDI %fixed-stack.2, 0 ; MIR32: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.2
; MIR32: renamable $[[GPR2:r[0-9]+]] = ADDI %fixed-stack.0, 0 ; MIR32: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.0
; MIR32: renamable $f{{[0-9]+}} = XFLOADf64 $zero, killed renamable $[[GPR1]]
; MIR32: renamable $f{{[0-9]+}} = XFLOADf64 $zero, killed renamable $[[GPR2]]
; 64BIT-LABEL: .test: ; 64BIT-LABEL: .test:
; 64BIT-DAG: lfd {{[0-9]+}}, 80(1) ; 64BIT-DAG: lfd {{[0-9]+}}, 80(1)
; 64BIT-DAG: lfd {{[0-9]+}}, 192(1) ; 64BIT-DAG: lfd {{[0-9]+}}, 192(1)
; MIR64: name: test ; MIR64: name: test
; MIR64: fixedStack: ; MIR64: fixedStack:
; MIR64: - { id: 0, type: default, offset: 192, size: 32, alignment: 16, stack-id: default, ; MIR64: - { id: 0, type: default, offset: 192, size: 32, alignment: 16, stack-id: default,
; MIR64: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, ; MIR64: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true,
; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR64: - { id: 1, type: default, offset: 188, size: 4, alignment: 4, stack-id: default, ; MIR64: - { id: 1, type: default, offset: 188, size: 4, alignment: 4, stack-id: default,
; MIR64: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, ; MIR64: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR64: - { id: 2, type: default, offset: 80, size: 16, alignment: 16, stack-id: default, ; MIR64: - { id: 2, type: default, offset: 80, size: 16, alignment: 16, stack-id: default,
; MIR64: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, ; MIR64: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } ; MIR64: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
; MIR64: renamable $[[GPR1:x[0-9]+]] = ADDI8 %fixed-stack.2, 0 ; MIR64: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.2
; MIR64: renamable $[[GPR2:x[0-9]+]] = ADDI8 %fixed-stack.0, 0 ; MIR64: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.0
; MIR64: renamable $f{{[0-9]+}} = XFLOADf64 $zero8, killed renamable $[[GPR1]]
; MIR64: renamable $f{{[0-9]+}} = XFLOADf64 $zero8, killed renamable $[[GPR2]]

llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ ; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \
; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefix=32BIT %s ; RUN: FileCheck --check-prefix=32BIT %s
; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ ; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \
; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefix=64BIT %s ; RUN: FileCheck --check-prefix=64BIT %s
define void @caller() { define void @caller() {
; 32BIT-LABEL: name: caller ; 32BIT-LABEL: name: caller
; 32BIT: bb.0.entry: ; 32BIT: bb.0.entry:
; 32BIT: ADJCALLSTACKDOWN 88, 0, implicit-def dead $r1, implicit $r1 ; 32BIT: ADJCALLSTACKDOWN 88, 0, implicit-def dead $r1, implicit $r1
; 32BIT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load 4 from got) ; 32BIT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load 4 from got)
; 32BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc]] :: (load 16 from constant-pool) ; 32BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc]] :: (load 16 from constant-pool)
; 32BIT: [[LI:%[0-9]+]]:gprc = LI 64 ; 32BIT: [[LI:%[0-9]+]]:gprc = LI 64
; 32BIT: STXVW4X killed [[LXVW4X]], $r1, killed [[LI]] :: (store 16) ; 32BIT: STXVW4X killed [[LXVW4X]], $r1, killed [[LI]] :: (store 16)
; 32BIT: [[LIS:%[0-9]+]]:gprc = LIS 38314 ; 32BIT: [[LIS:%[0-9]+]]:gprc = LIS 38314
; 32BIT: [[ORI:%[0-9]+]]:gprc = ORI killed [[LIS]], 63376 ; 32BIT: [[ORI:%[0-9]+]]:gprc = ORI killed [[LIS]], 63376
; 32BIT: STW killed [[ORI]], 84, $r1 :: (store 4 into unknown-address + 4, basealign 8) ; 32BIT: STW killed [[ORI]], 84, $r1 :: (store 4 into unknown-address + 4, basealign 8)
; 32BIT: [[LIS1:%[0-9]+]]:gprc = LIS 16389 ; 32BIT: [[LIS1:%[0-9]+]]:gprc = LIS 16389
; 32BIT: [[ORI1:%[0-9]+]]:gprc = ORI killed [[LIS1]], 48905 ; 32BIT: [[ORI1:%[0-9]+]]:gprc = ORI killed [[LIS1]], 48905
; 32BIT: STW killed [[ORI1]], 80, $r1 :: (store 4, align 8) ; 32BIT: STW killed [[ORI1]], 80, $r1 :: (store 4, align 8)
; 32BIT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc %const.1, $r2 :: (load 4 from got) ; 32BIT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc %const.1, $r2 :: (load 4 from got)
; 32BIT: [[LXVW4X1:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc1]] :: (load 16 from constant-pool) ; 32BIT: [[LXVW4X1:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc1]] :: (load 16 from constant-pool)
; 32BIT: [[LWZtoc2:%[0-9]+]]:gprc = LWZtoc %const.2, $r2 :: (load 4 from got) ; 32BIT: [[LWZtoc2:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.2, $r2 :: (load 4 from got)
; 32BIT: [[XFLOADf64_:%[0-9]+]]:vsfrc = XFLOADf64 $zero, killed [[LWZtoc2]] :: (load 8 from constant-pool) ; 32BIT: [[LFD:%[0-9]+]]:f8rc = LFD 0, killed [[LWZtoc2]] :: (load 8 from constant-pool)
; 32BIT: [[LIS2:%[0-9]+]]:gprc = LIS 16393 ; 32BIT: [[LIS2:%[0-9]+]]:gprc = LIS 16393
; 32BIT: [[ORI2:%[0-9]+]]:gprc = ORI killed [[LIS2]], 8697 ; 32BIT: [[ORI2:%[0-9]+]]:gprc = ORI killed [[LIS2]], 8697
; 32BIT: [[LIS3:%[0-9]+]]:gprc = LIS 61467 ; 32BIT: [[LIS3:%[0-9]+]]:gprc = LIS 61467
; 32BIT: [[ORI3:%[0-9]+]]:gprc = ORI killed [[LIS3]], 34414 ; 32BIT: [[ORI3:%[0-9]+]]:gprc = ORI killed [[LIS3]], 34414
; 32BIT: [[LWZtoc3:%[0-9]+]]:gprc = LWZtoc %const.3, $r2 :: (load 4 from got) ; 32BIT: [[LWZtoc3:%[0-9]+]]:gprc_and_gprc_nor0 = LWZtoc %const.3, $r2 :: (load 4 from got)
; 32BIT: [[XFLOADf64_1:%[0-9]+]]:vsfrc = XFLOADf64 $zero, killed [[LWZtoc3]] :: (load 8 from constant-pool) ; 32BIT: [[LFD1:%[0-9]+]]:f8rc = LFD 0, killed [[LWZtoc3]] :: (load 8 from constant-pool)
; 32BIT: [[LI1:%[0-9]+]]:gprc = LI 55 ; 32BIT: [[LI1:%[0-9]+]]:gprc = LI 55
; 32BIT: $r3 = COPY [[LI1]] ; 32BIT: $r3 = COPY [[LI1]]
; 32BIT: $v2 = COPY [[LXVW4X1]] ; 32BIT: $v2 = COPY [[LXVW4X1]]
; 32BIT: $f1 = COPY [[XFLOADf64_]] ; 32BIT: $f1 = COPY [[LFD]]
; 32BIT: $r9 = COPY [[ORI2]] ; 32BIT: $r9 = COPY [[ORI2]]
; 32BIT: $r10 = COPY [[ORI3]] ; 32BIT: $r10 = COPY [[ORI3]]
; 32BIT: $f2 = COPY [[XFLOADf64_1]] ; 32BIT: $f2 = COPY [[LFD1]]
; 32BIT: BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $v2, implicit $f1, implicit $r9, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1, implicit-def $v2 ; 32BIT: BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $v2, implicit $f1, implicit $r9, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1, implicit-def $v2
; 32BIT: ADJCALLSTACKUP 88, 0, implicit-def dead $r1, implicit $r1 ; 32BIT: ADJCALLSTACKUP 88, 0, implicit-def dead $r1, implicit $r1
; 32BIT: [[COPY:%[0-9]+]]:vsrc = COPY $v2 ; 32BIT: [[COPY:%[0-9]+]]:vsrc = COPY $v2
; 32BIT: BLR implicit $lr, implicit $rm ; 32BIT: BLR implicit $lr, implicit $rm
; 64BIT-LABEL: name: caller ; 64BIT-LABEL: name: caller
; 64BIT: bb.0.entry: ; 64BIT: bb.0.entry:
; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT: [[LDtocCPT:%[0-9]+]]:g8rc = LDtocCPT %const.0, $x2 :: (load 8 from got) ; 64BIT: [[LDtocCPT:%[0-9]+]]:g8rc = LDtocCPT %const.0, $x2 :: (load 8 from got)
; 64BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero8, killed [[LDtocCPT]] :: (load 16 from constant-pool) ; 64BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero8, killed [[LDtocCPT]] :: (load 16 from constant-pool)
; 64BIT: [[LI8_:%[0-9]+]]:g8rc = LI8 96 ; 64BIT: [[LI8_:%[0-9]+]]:g8rc = LI8 96
; 64BIT: STXVW4X killed [[LXVW4X]], $x1, killed [[LI8_]] :: (store 16) ; 64BIT: STXVW4X killed [[LXVW4X]], $x1, killed [[LI8_]] :: (store 16)
; 64BIT: [[LIS8_:%[0-9]+]]:g8rc = LIS8 16389 ; 64BIT: [[LIS8_:%[0-9]+]]:g8rc = LIS8 16389
; 64BIT: [[ORI8_:%[0-9]+]]:g8rc = ORI8 killed [[LIS8_]], 48905 ; 64BIT: [[ORI8_:%[0-9]+]]:g8rc = ORI8 killed [[LIS8_]], 48905
; 64BIT: [[RLDIC:%[0-9]+]]:g8rc = RLDIC killed [[ORI8_]], 32, 1 ; 64BIT: [[RLDIC:%[0-9]+]]:g8rc = RLDIC killed [[ORI8_]], 32, 1
; 64BIT: [[ORIS8_:%[0-9]+]]:g8rc = ORIS8 killed [[RLDIC]], 38314 ; 64BIT: [[ORIS8_:%[0-9]+]]:g8rc = ORIS8 killed [[RLDIC]], 38314
; 64BIT: [[ORI8_1:%[0-9]+]]:g8rc = ORI8 killed [[ORIS8_]], 63376 ; 64BIT: [[ORI8_1:%[0-9]+]]:g8rc = ORI8 killed [[ORIS8_]], 63376
; 64BIT: STD killed [[ORI8_1]], 112, $x1 :: (store 8) ; 64BIT: STD killed [[ORI8_1]], 112, $x1 :: (store 8)
; 64BIT: [[LDtocCPT1:%[0-9]+]]:g8rc = LDtocCPT %const.1, $x2 :: (load 8 from got) ; 64BIT: [[LDtocCPT1:%[0-9]+]]:g8rc = LDtocCPT %const.1, $x2 :: (load 8 from got)
; 64BIT: [[LXVW4X1:%[0-9]+]]:vsrc = LXVW4X $zero8, killed [[LDtocCPT1]] :: (load 16 from constant-pool) ; 64BIT: [[LXVW4X1:%[0-9]+]]:vsrc = LXVW4X $zero8, killed [[LDtocCPT1]] :: (load 16 from constant-pool)
; 64BIT: [[LD:%[0-9]+]]:g8rc = LD 104, $x1 :: (load 8) ; 64BIT: [[LD:%[0-9]+]]:g8rc = LD 104, $x1 :: (load 8)
; 64BIT: [[LD1:%[0-9]+]]:g8rc = LD 96, $x1 :: (load 8) ; 64BIT: [[LD1:%[0-9]+]]:g8rc = LD 96, $x1 :: (load 8)
; 64BIT: [[LDtocCPT2:%[0-9]+]]:g8rc = LDtocCPT %const.2, $x2 :: (load 8 from got) ; 64BIT: [[LDtocCPT2:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.2, $x2 :: (load 8 from got)
; 64BIT: [[XFLOADf64_:%[0-9]+]]:vsfrc = XFLOADf64 $zero8, killed [[LDtocCPT2]] :: (load 8 from constant-pool) ; 64BIT: [[LFD:%[0-9]+]]:f8rc = LFD 0, killed [[LDtocCPT2]] :: (load 8 from constant-pool)
; 64BIT: [[LDtocCPT3:%[0-9]+]]:g8rc = LDtocCPT %const.3, $x2 :: (load 8 from got) ; 64BIT: [[LDtocCPT3:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.3, $x2 :: (load 8 from got)
; 64BIT: [[XFLOADf64_1:%[0-9]+]]:vsfrc = XFLOADf64 $zero8, killed [[LDtocCPT3]] :: (load 8 from constant-pool) ; 64BIT: [[LFD1:%[0-9]+]]:f8rc = LFD 0, killed [[LDtocCPT3]] :: (load 8 from constant-pool)
; 64BIT: [[LIS8_1:%[0-9]+]]:g8rc = LIS8 16393 ; 64BIT: [[LIS8_1:%[0-9]+]]:g8rc = LIS8 16393
; 64BIT: [[ORI8_2:%[0-9]+]]:g8rc = ORI8 killed [[LIS8_1]], 8697 ; 64BIT: [[ORI8_2:%[0-9]+]]:g8rc = ORI8 killed [[LIS8_1]], 8697
; 64BIT: [[RLDIC1:%[0-9]+]]:g8rc = RLDIC killed [[ORI8_2]], 32, 1 ; 64BIT: [[RLDIC1:%[0-9]+]]:g8rc = RLDIC killed [[ORI8_2]], 32, 1
; 64BIT: [[ORIS8_1:%[0-9]+]]:g8rc = ORIS8 killed [[RLDIC1]], 61467 ; 64BIT: [[ORIS8_1:%[0-9]+]]:g8rc = ORIS8 killed [[RLDIC1]], 61467
; 64BIT: [[ORI8_3:%[0-9]+]]:g8rc = ORI8 killed [[ORIS8_1]], 34414 ; 64BIT: [[ORI8_3:%[0-9]+]]:g8rc = ORI8 killed [[ORIS8_1]], 34414
; 64BIT: [[LI8_1:%[0-9]+]]:g8rc = LI8 55 ; 64BIT: [[LI8_1:%[0-9]+]]:g8rc = LI8 55
; 64BIT: $x3 = COPY [[LI8_1]] ; 64BIT: $x3 = COPY [[LI8_1]]
; 64BIT: $v2 = COPY [[LXVW4X1]] ; 64BIT: $v2 = COPY [[LXVW4X1]]
; 64BIT: $f1 = COPY [[XFLOADf64_]] ; 64BIT: $f1 = COPY [[LFD]]
; 64BIT: $x7 = COPY [[ORI8_3]] ; 64BIT: $x7 = COPY [[ORI8_3]]
; 64BIT: $x9 = COPY [[LD1]] ; 64BIT: $x9 = COPY [[LD1]]
; 64BIT: $x10 = COPY [[LD]] ; 64BIT: $x10 = COPY [[LD]]
; 64BIT: $f2 = COPY [[XFLOADf64_1]] ; 64BIT: $f2 = COPY [[LFD1]]
; 64BIT: BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $v2, implicit $f1, implicit $x7, implicit $x9, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1, implicit-def $v2 ; 64BIT: BL8_NOP <mcsymbol .callee[PR]>, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $v2, implicit $f1, implicit $x7, implicit $x9, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1, implicit-def $v2
; 64BIT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT: [[COPY:%[0-9]+]]:vsrc = COPY $v2 ; 64BIT: [[COPY:%[0-9]+]]:vsrc = COPY $v2
; 64BIT: BLR8 implicit $lr8, implicit $rm ; 64BIT: BLR8 implicit $lr8, implicit $rm
entry: entry:
%call = tail call <4 x i32> (i32, <4 x i32>, double, ...) @callee(i32 signext 55, <4 x i32> <i32 170, i32 187, i32 204, i32 221>, double 3.141590e+00, <4 x i32> <i32 10, i32 20, i32 30, i32 40>, double 2.718280e+00) %call = tail call <4 x i32> (i32, <4 x i32>, double, ...) @callee(i32 signext 55, <4 x i32> <i32 170, i32 187, i32 204, i32 221>, double 3.141590e+00, <4 x i32> <i32 10, i32 20, i32 30, i32 40>, double 2.718280e+00)
ret void ret void
} }
declare <4 x i32> @callee(i32 signext, <4 x i32>, double, ...) declare <4 x i32> @callee(i32 signext, <4 x i32>, double, ...)

llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \ ; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \
; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
;; Fixed vector arguments to variadic functions are passed differently than ;; Fixed vector arguments to variadic functions are passed differently than
;; either arguments to non-variadic functions or arguments passed through ;; either arguments to non-variadic functions or arguments passed through
;; ellipses. ;; ellipses.
define double @callee(i32 %count, <4 x i32> %vsi, double %next, ...) { define double @callee(i32 %count, <4 x i32> %vsi, double %next, ...) {
; CHECK-LABEL: name: callee ; CHECK-LABEL: name: callee
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: LIFETIME_START %stack.0.arg_list ; CHECK: LIFETIME_START %stack.0.arg_list
; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0 ; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0
; CHECK: STW killed [[ADDI]], 0, %stack.0.arg_list :: (store 4 into %ir.0) ; CHECK: STW killed [[ADDI]], 0, %stack.0.arg_list :: (store 4 into %ir.0)
; CHECK: [[ADDI1:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 15 ; CHECK: [[ADDI1:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 15
; CHECK: [[RLWINM:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM killed [[ADDI1]], 0, 0, 27 ; CHECK: [[RLWINM:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM killed [[ADDI1]], 0, 0, 27
; CHECK: [[ADDI2:%[0-9]+]]:gprc = nuw ADDI killed [[RLWINM]], 16 ; CHECK: [[LFD:%[0-9]+]]:f8rc = LFD 16, killed [[RLWINM]] :: (load 8 from %ir.4, align 16)
; CHECK: [[XFLOADf64_:%[0-9]+]]:vsfrc = XFLOADf64 $zero, killed [[ADDI2]] :: (load 8 from %ir.4, align 16)
; CHECK: LIFETIME_END %stack.0.arg_list ; CHECK: LIFETIME_END %stack.0.arg_list
; CHECK: $f1 = COPY [[XFLOADf64_]] ; CHECK: $f1 = COPY [[LFD]]
; CHECK: BLR implicit $lr, implicit $rm, implicit $f1 ; CHECK: BLR implicit $lr, implicit $rm, implicit $f1
entry: entry:
%arg_list = alloca i8*, align 4 %arg_list = alloca i8*, align 4
%0 = bitcast i8** %arg_list to i8* %0 = bitcast i8** %arg_list to i8*
call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0) call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
call void @llvm.va_start(i8* nonnull %0) call void @llvm.va_start(i8* nonnull %0)
%argp.cur = load i8*, i8** %arg_list, align 4 %argp.cur = load i8*, i8** %arg_list, align 4
%1 = ptrtoint i8* %argp.cur to i32 %1 = ptrtoint i8* %argp.cur to i32
Show All 21 Lines

llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll

Show All 15 Linesdefine double @callee(i32 signext %count, <4 x i32> %vsi, double %next, ...) {
; CHECK: STD [[COPY2]], 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0) ; CHECK: STD [[COPY2]], 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0)
; CHECK: STD [[COPY1]], 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8) ; CHECK: STD [[COPY1]], 8, %fixed-stack.0 :: (store 8 into %fixed-stack.0 + 8)
; CHECK: STD [[COPY]], 16, %fixed-stack.0 :: (store 8) ; CHECK: STD [[COPY]], 16, %fixed-stack.0 :: (store 8)
; CHECK: LIFETIME_START %stack.0.arg_list ; CHECK: LIFETIME_START %stack.0.arg_list
; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 0 ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 0
; CHECK: STD killed [[ADDI8_]], 0, %stack.0.arg_list :: (store 8 into %ir.0) ; CHECK: STD killed [[ADDI8_]], 0, %stack.0.arg_list :: (store 8 into %ir.0)
; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 15 ; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 %fixed-stack.0, 15
; CHECK: [[RLDICR:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICR killed [[ADDI8_1]], 0, 59 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICR killed [[ADDI8_1]], 0, 59
; CHECK: [[LI8_:%[0-9]+]]:g8rc = LI8 16 ; CHECK: [[LFD:%[0-9]+]]:f8rc = LFD 16, killed [[RLDICR]] :: (load 8 from %ir.4, align 16)
; CHECK: [[XFLOADf64_:%[0-9]+]]:vsfrc = XFLOADf64 killed [[RLDICR]], killed [[LI8_]] :: (load 8 from %ir.4, align 16)
; CHECK: LIFETIME_END %stack.0.arg_list ; CHECK: LIFETIME_END %stack.0.arg_list
; CHECK: $f1 = COPY [[XFLOADf64_]] ; CHECK: $f1 = COPY [[LFD]]
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $f1 ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $f1
entry: entry:
%arg_list = alloca i8*, align 8 %arg_list = alloca i8*, align 8
%0 = bitcast i8** %arg_list to i8* %0 = bitcast i8** %arg_list to i8*
call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
call void @llvm.va_start(i8* nonnull %0) call void @llvm.va_start(i8* nonnull %0)
%argp.cur = load i8*, i8** %arg_list, align 8 %argp.cur = load i8*, i8** %arg_list, align 8
%1 = ptrtoint i8* %argp.cur to i64 %1 = ptrtoint i8* %argp.cur to i64
Show All 20 Lines

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

Show First 20 Lines • Show All 852 Lines • ▼ Show 20 Linesentry:
ret <4 x i32> %vecinit3 ret <4 x i32> %vecinit3
} }
define <4 x i32> @fromDiffConstsi() { define <4 x i32> @fromDiffConstsi() {
; P9BE-LABEL: fromDiffConstsi: ; P9BE-LABEL: fromDiffConstsi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsi: ; P9LE-LABEL: fromDiffConstsi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsi: ; P8BE-LABEL: fromDiffConstsi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
} }
define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromDiffMemConsDi: ; P9BE-LABEL: fromDiffMemConsDi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDi: ; P9LE-LABEL: fromDiffMemConsDi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxvw4x v2, 0, r3 ; P9LE-NEXT: lxvw4x v2, 0, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
ret <4 x i32> %vecinit11 ret <4 x i32> %vecinit11
} }
define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) {
; P9BE-LABEL: fromDiffMemVarDi: ; P9BE-LABEL: fromDiffMemVarDi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: sldi r4, r4, 2
; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: add r3, r3, r4
; P9BE-NEXT: addi r3, r3, -12 ; P9BE-NEXT: li r4, -12
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxvx v2, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemVarDi: ; P9LE-LABEL: fromDiffMemVarDi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: sldi r4, r4, 2
; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -12 ; P9LE-NEXT: li r4, -12
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxvx v2, r3, r4
; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: lxv v3, 0(r3)
; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemVarDi: ; P8BE-LABEL: fromDiffMemVarDi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha ; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
▲ Show 20 Lines • Show All 329 Lines • ▼ Show 20 Linesentry:
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
} }
define <4 x i32> @fromDiffConstsConvftoi() { define <4 x i32> @fromDiffConstsConvftoi() {
; P9BE-LABEL: fromDiffConstsConvftoi: ; P9BE-LABEL: fromDiffConstsConvftoi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvftoi: ; P9LE-LABEL: fromDiffConstsConvftoi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvftoi: ; P8BE-LABEL: fromDiffConstsConvftoi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
} }
define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsDConvftoi: ; P9BE-LABEL: fromDiffMemConsDConvftoi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: xvcvspsxws v2, v2 ; P9BE-NEXT: xvcvspsxws v2, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDConvftoi: ; P9LE-LABEL: fromDiffMemConsDConvftoi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: lxv v3, 0(r3)
; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: xvcvspsxws v2, v2 ; P9LE-NEXT: xvcvspsxws v2, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvftoi: ; P8BE-LABEL: fromDiffMemConsDConvftoi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
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ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
} }
define <4 x i32> @fromDiffConstsConvdtoi() { define <4 x i32> @fromDiffConstsConvdtoi() {
; P9BE-LABEL: fromDiffConstsConvdtoi: ; P9BE-LABEL: fromDiffConstsConvdtoi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvdtoi: ; P9LE-LABEL: fromDiffConstsConvdtoi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvdtoi: ; P8BE-LABEL: fromDiffConstsConvdtoi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
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; P9LE-NEXT: xvcvdpsxws v2, vs0 ; P9LE-NEXT: xvcvdpsxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
; P9LE-NEXT: xvcvdpsxws v3, vs0 ; P9LE-NEXT: xvcvdpsxws v3, vs0
; P9LE-NEXT: vmrgew v2, v3, v2 ; P9LE-NEXT: vmrgew v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvdtoi: ; P8BE-LABEL: fromDiffMemConsDConvdtoi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfdx f3, 0, r3 ; P8BE-NEXT: lfd f0, 16(r3)
; P8BE-NEXT: lfd f0, 24(r3) ; P8BE-NEXT: lfd f1, 0(r3)
; P8BE-NEXT: lfd f1, 8(r3) ; P8BE-NEXT: lfd f2, 24(r3)
; P8BE-NEXT: lfd f2, 16(r3) ; P8BE-NEXT: lfd f3, 8(r3)
; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
; P8BE-NEXT: xxmrghd vs1, vs2, vs3 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
; P8BE-NEXT: xvcvdpsxws v2, vs0 ; P8BE-NEXT: xvcvdpsxws v2, vs0
; P8BE-NEXT: xvcvdpsxws v3, vs1 ; P8BE-NEXT: xvcvdpsxws v3, vs1
; P8BE-NEXT: vmrgew v2, v2, v3 ; P8BE-NEXT: vmrgew v2, v3, v2
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDConvdtoi: ; P8LE-LABEL: fromDiffMemConsDConvdtoi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfdx f3, 0, r3
; P8LE-NEXT: lfd f0, 24(r3) ; P8LE-NEXT: lfd f0, 24(r3)
; P8LE-NEXT: lfd f1, 8(r3) ; P8LE-NEXT: lfd f1, 8(r3)
; P8LE-NEXT: lfd f2, 16(r3) ; P8LE-NEXT: lfd f2, 16(r3)
; P8LE-NEXT: lfd f3, 0(r3)
; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
; P8LE-NEXT: xxmrghd vs1, vs3, vs2 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
; P8LE-NEXT: xvcvdpsxws v2, vs0 ; P8LE-NEXT: xvcvdpsxws v2, vs0
; P8LE-NEXT: xvcvdpsxws v3, vs1 ; P8LE-NEXT: xvcvdpsxws v3, vs1
; P8LE-NEXT: vmrgew v2, v3, v2 ; P8LE-NEXT: vmrgew v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds double, double* %ptr, i64 3 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
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ret <4 x i32> %vecinit3 ret <4 x i32> %vecinit3
} }
define <4 x i32> @fromDiffConstsui() { define <4 x i32> @fromDiffConstsui() {
; P9BE-LABEL: fromDiffConstsui: ; P9BE-LABEL: fromDiffConstsui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsui: ; P9LE-LABEL: fromDiffConstsui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsui: ; P8BE-LABEL: fromDiffConstsui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
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} }
define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromDiffMemConsDui: ; P9BE-LABEL: fromDiffMemConsDui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDui: ; P9LE-LABEL: fromDiffMemConsDui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxvw4x v2, 0, r3 ; P9LE-NEXT: lxvw4x v2, 0, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
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ret <4 x i32> %vecinit11 ret <4 x i32> %vecinit11
} }
define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) {
; P9BE-LABEL: fromDiffMemVarDui: ; P9BE-LABEL: fromDiffMemVarDui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: sldi r4, r4, 2
; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: add r3, r3, r4
; P9BE-NEXT: addi r3, r3, -12 ; P9BE-NEXT: li r4, -12
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxvx v2, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemVarDui: ; P9LE-LABEL: fromDiffMemVarDui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: sldi r4, r4, 2
; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: addi r3, r3, -12 ; P9LE-NEXT: li r4, -12
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxvx v2, r3, r4
; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: lxv v3, 0(r3)
; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemVarDui: ; P8BE-LABEL: fromDiffMemVarDui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha ; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
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ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
} }
define <4 x i32> @fromDiffConstsConvftoui() { define <4 x i32> @fromDiffConstsConvftoui() {
; P9BE-LABEL: fromDiffConstsConvftoui: ; P9BE-LABEL: fromDiffConstsConvftoui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvftoui: ; P9LE-LABEL: fromDiffConstsConvftoui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvftoui: ; P8BE-LABEL: fromDiffConstsConvftoui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
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} }
define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
; P9BE-LABEL: fromDiffMemConsDConvftoui: ; P9BE-LABEL: fromDiffMemConsDConvftoui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
; P9BE-NEXT: lxvx v3, 0, r3 ; P9BE-NEXT: lxv v3, 0(r3)
; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: vperm v2, v2, v2, v3
; P9BE-NEXT: xvcvspuxws v2, v2 ; P9BE-NEXT: xvcvspuxws v2, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffMemConsDConvftoui: ; P9LE-LABEL: fromDiffMemConsDConvftoui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l
; P9LE-NEXT: lxvx v3, 0, r3 ; P9LE-NEXT: lxv v3, 0(r3)
; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: vperm v2, v2, v2, v3
; P9LE-NEXT: xvcvspuxws v2, v2 ; P9LE-NEXT: xvcvspuxws v2, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvftoui: ; P8BE-LABEL: fromDiffMemConsDConvftoui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha ; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
▲ Show 20 Lines • Show All 361 Lines • ▼ Show 20 Linesentry:
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
} }
define <4 x i32> @fromDiffConstsConvdtoui() { define <4 x i32> @fromDiffConstsConvdtoui() {
; P9BE-LABEL: fromDiffConstsConvdtoui: ; P9BE-LABEL: fromDiffConstsConvdtoui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvdtoui: ; P9LE-LABEL: fromDiffConstsConvdtoui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvdtoui: ; P8BE-LABEL: fromDiffConstsConvdtoui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
; P8BE-NEXT: lxvw4x v2, 0, r3 ; P8BE-NEXT: lxvw4x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
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; P9LE-NEXT: xvcvdpuxws v2, vs0 ; P9LE-NEXT: xvcvdpuxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
; P9LE-NEXT: xvcvdpuxws v3, vs0 ; P9LE-NEXT: xvcvdpuxws v3, vs0
; P9LE-NEXT: vmrgew v2, v3, v2 ; P9LE-NEXT: vmrgew v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsDConvdtoui: ; P8BE-LABEL: fromDiffMemConsDConvdtoui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfdx f3, 0, r3 ; P8BE-NEXT: lfd f0, 16(r3)
; P8BE-NEXT: lfd f0, 24(r3) ; P8BE-NEXT: lfd f1, 0(r3)
; P8BE-NEXT: lfd f1, 8(r3) ; P8BE-NEXT: lfd f2, 24(r3)
; P8BE-NEXT: lfd f2, 16(r3) ; P8BE-NEXT: lfd f3, 8(r3)
; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
; P8BE-NEXT: xxmrghd vs1, vs2, vs3 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
; P8BE-NEXT: xvcvdpuxws v2, vs0 ; P8BE-NEXT: xvcvdpuxws v2, vs0
; P8BE-NEXT: xvcvdpuxws v3, vs1 ; P8BE-NEXT: xvcvdpuxws v3, vs1
; P8BE-NEXT: vmrgew v2, v2, v3 ; P8BE-NEXT: vmrgew v2, v3, v2
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsDConvdtoui: ; P8LE-LABEL: fromDiffMemConsDConvdtoui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfdx f3, 0, r3
; P8LE-NEXT: lfd f0, 24(r3) ; P8LE-NEXT: lfd f0, 24(r3)
; P8LE-NEXT: lfd f1, 8(r3) ; P8LE-NEXT: lfd f1, 8(r3)
; P8LE-NEXT: lfd f2, 16(r3) ; P8LE-NEXT: lfd f2, 16(r3)
; P8LE-NEXT: lfd f3, 0(r3)
; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
; P8LE-NEXT: xxmrghd vs1, vs3, vs2 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
; P8LE-NEXT: xvcvdpuxws v2, vs0 ; P8LE-NEXT: xvcvdpuxws v2, vs0
; P8LE-NEXT: xvcvdpuxws v3, vs1 ; P8LE-NEXT: xvcvdpuxws v3, vs1
; P8LE-NEXT: vmrgew v2, v3, v2 ; P8LE-NEXT: vmrgew v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds double, double* %ptr, i64 3 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> zeroinitializer ret <2 x i64> zeroinitializer
} }
define <2 x i64> @spltConst1ll() { define <2 x i64> @spltConst1ll() {
; P9BE-LABEL: spltConst1ll: ; P9BE-LABEL: spltConst1ll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst1ll: ; P9LE-LABEL: spltConst1ll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst1ll: ; P8BE-LABEL: spltConst1ll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 9 Linesentry:
ret <2 x i64> <i64 1, i64 1> ret <2 x i64> <i64 1, i64 1>
} }
define <2 x i64> @spltConst16kll() { define <2 x i64> @spltConst16kll() {
; P9BE-LABEL: spltConst16kll: ; P9BE-LABEL: spltConst16kll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst16kll: ; P9LE-LABEL: spltConst16kll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst16kll: ; P8BE-LABEL: spltConst16kll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 9 Linesentry:
ret <2 x i64> <i64 32767, i64 32767> ret <2 x i64> <i64 32767, i64 32767>
} }
define <2 x i64> @spltConst32kll() { define <2 x i64> @spltConst32kll() {
; P9BE-LABEL: spltConst32kll: ; P9BE-LABEL: spltConst32kll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst32kll: ; P9LE-LABEL: spltConst32kll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst32kll: ; P8BE-LABEL: spltConst32kll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 39 Linesentry:
ret <2 x i64> %vecinit1 ret <2 x i64> %vecinit1
} }
define <2 x i64> @fromDiffConstsll() { define <2 x i64> @fromDiffConstsll() {
; P9BE-LABEL: fromDiffConstsll: ; P9BE-LABEL: fromDiffConstsll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsll: ; P9LE-LABEL: fromDiffConstsll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsll: ; P8BE-LABEL: fromDiffConstsll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 310 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
define <2 x i64> @spltCnstConvftoll() { define <2 x i64> @spltCnstConvftoll() {
; P9BE-LABEL: spltCnstConvftoll: ; P9BE-LABEL: spltCnstConvftoll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltCnstConvftoll: ; P9LE-LABEL: spltCnstConvftoll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltCnstConvftoll: ; P8BE-LABEL: spltCnstConvftoll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %vecinit2 ret <2 x i64> %vecinit2
} }
define <2 x i64> @fromDiffConstsConvftoll() { define <2 x i64> @fromDiffConstsConvftoll() {
; P9BE-LABEL: fromDiffConstsConvftoll: ; P9BE-LABEL: fromDiffConstsConvftoll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvftoll: ; P9LE-LABEL: fromDiffConstsConvftoll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvftoll: ; P8BE-LABEL: fromDiffConstsConvftoll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 23 Lines
; P9LE-NEXT: lfs f0, 0(r3) ; P9LE-NEXT: lfs f0, 0(r3)
; P9LE-NEXT: lfs f1, 4(r3) ; P9LE-NEXT: lfs f1, 4(r3)
; P9LE-NEXT: xxmrghd vs0, vs1, vs0 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
; P9LE-NEXT: xvcvdpsxds v2, vs0 ; P9LE-NEXT: xvcvdpsxds v2, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsAConvftoll: ; P8BE-LABEL: fromDiffMemConsAConvftoll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfsx f0, 0, r3 ; P8BE-NEXT: lfs f0, 0(r3)
; P8BE-NEXT: lfs f1, 4(r3) ; P8BE-NEXT: lfs f1, 4(r3)
; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
; P8BE-NEXT: xvcvdpsxds v2, vs0 ; P8BE-NEXT: xvcvdpsxds v2, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsAConvftoll: ; P8LE-LABEL: fromDiffMemConsAConvftoll:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfsx f0, 0, r3 ; P8LE-NEXT: lfs f0, 0(r3)
; P8LE-NEXT: lfs f1, 4(r3) ; P8LE-NEXT: lfs f1, 4(r3)
; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
; P8LE-NEXT: xvcvdpsxds v2, vs0 ; P8LE-NEXT: xvcvdpsxds v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%0 = load float, float* %ptr, align 4 %0 = load float, float* %ptr, align 4
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
define <2 x i64> @spltCnstConvdtoll() { define <2 x i64> @spltCnstConvdtoll() {
; P9BE-LABEL: spltCnstConvdtoll: ; P9BE-LABEL: spltCnstConvdtoll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltCnstConvdtoll: ; P9LE-LABEL: spltCnstConvdtoll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltCnstConvdtoll: ; P8BE-LABEL: spltCnstConvdtoll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %vecinit2 ret <2 x i64> %vecinit2
} }
define <2 x i64> @fromDiffConstsConvdtoll() { define <2 x i64> @fromDiffConstsConvdtoll() {
; P9BE-LABEL: fromDiffConstsConvdtoll: ; P9BE-LABEL: fromDiffConstsConvdtoll:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvdtoll: ; P9LE-LABEL: fromDiffConstsConvdtoll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvdtoll: ; P8BE-LABEL: fromDiffConstsConvdtoll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 266 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> zeroinitializer ret <2 x i64> zeroinitializer
} }
define <2 x i64> @spltConst1ull() { define <2 x i64> @spltConst1ull() {
; P9BE-LABEL: spltConst1ull: ; P9BE-LABEL: spltConst1ull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst1ull: ; P9LE-LABEL: spltConst1ull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst1ull: ; P8BE-LABEL: spltConst1ull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 9 Linesentry:
ret <2 x i64> <i64 1, i64 1> ret <2 x i64> <i64 1, i64 1>
} }
define <2 x i64> @spltConst16kull() { define <2 x i64> @spltConst16kull() {
; P9BE-LABEL: spltConst16kull: ; P9BE-LABEL: spltConst16kull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst16kull: ; P9LE-LABEL: spltConst16kull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst16kull: ; P8BE-LABEL: spltConst16kull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 9 Linesentry:
ret <2 x i64> <i64 32767, i64 32767> ret <2 x i64> <i64 32767, i64 32767>
} }
define <2 x i64> @spltConst32kull() { define <2 x i64> @spltConst32kull() {
; P9BE-LABEL: spltConst32kull: ; P9BE-LABEL: spltConst32kull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltConst32kull: ; P9LE-LABEL: spltConst32kull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltConst32kull: ; P8BE-LABEL: spltConst32kull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 39 Linesentry:
ret <2 x i64> %vecinit1 ret <2 x i64> %vecinit1
} }
define <2 x i64> @fromDiffConstsull() { define <2 x i64> @fromDiffConstsull() {
; P9BE-LABEL: fromDiffConstsull: ; P9BE-LABEL: fromDiffConstsull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsull: ; P9LE-LABEL: fromDiffConstsull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsull: ; P8BE-LABEL: fromDiffConstsull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 310 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
define <2 x i64> @spltCnstConvftoull() { define <2 x i64> @spltCnstConvftoull() {
; P9BE-LABEL: spltCnstConvftoull: ; P9BE-LABEL: spltCnstConvftoull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltCnstConvftoull: ; P9LE-LABEL: spltCnstConvftoull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltCnstConvftoull: ; P8BE-LABEL: spltCnstConvftoull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %vecinit2 ret <2 x i64> %vecinit2
} }
define <2 x i64> @fromDiffConstsConvftoull() { define <2 x i64> @fromDiffConstsConvftoull() {
; P9BE-LABEL: fromDiffConstsConvftoull: ; P9BE-LABEL: fromDiffConstsConvftoull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvftoull: ; P9LE-LABEL: fromDiffConstsConvftoull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvftoull: ; P8BE-LABEL: fromDiffConstsConvftoull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
Show All 23 Lines
; P9LE-NEXT: lfs f0, 0(r3) ; P9LE-NEXT: lfs f0, 0(r3)
; P9LE-NEXT: lfs f1, 4(r3) ; P9LE-NEXT: lfs f1, 4(r3)
; P9LE-NEXT: xxmrghd vs0, vs1, vs0 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
; P9LE-NEXT: xvcvdpuxds v2, vs0 ; P9LE-NEXT: xvcvdpuxds v2, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffMemConsAConvftoull: ; P8BE-LABEL: fromDiffMemConsAConvftoull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfsx f0, 0, r3 ; P8BE-NEXT: lfs f0, 0(r3)
; P8BE-NEXT: lfs f1, 4(r3) ; P8BE-NEXT: lfs f1, 4(r3)
; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
; P8BE-NEXT: xvcvdpuxds v2, vs0 ; P8BE-NEXT: xvcvdpuxds v2, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromDiffMemConsAConvftoull: ; P8LE-LABEL: fromDiffMemConsAConvftoull:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfsx f0, 0, r3 ; P8LE-NEXT: lfs f0, 0(r3)
; P8LE-NEXT: lfs f1, 4(r3) ; P8LE-NEXT: lfs f1, 4(r3)
; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
; P8LE-NEXT: xvcvdpuxds v2, vs0 ; P8LE-NEXT: xvcvdpuxds v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%0 = load float, float* %ptr, align 4 %0 = load float, float* %ptr, align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
define <2 x i64> @spltCnstConvdtoull() { define <2 x i64> @spltCnstConvdtoull() {
; P9BE-LABEL: spltCnstConvdtoull: ; P9BE-LABEL: spltCnstConvdtoull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: spltCnstConvdtoull: ; P9LE-LABEL: spltCnstConvdtoull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltCnstConvdtoull: ; P8BE-LABEL: spltCnstConvdtoull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %vecinit2 ret <2 x i64> %vecinit2
} }
define <2 x i64> @fromDiffConstsConvdtoull() { define <2 x i64> @fromDiffConstsConvdtoull() {
; P9BE-LABEL: fromDiffConstsConvdtoull: ; P9BE-LABEL: fromDiffConstsConvdtoull:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r3 ; P9BE-NEXT: lxv v2, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromDiffConstsConvdtoull: ; P9LE-LABEL: fromDiffConstsConvdtoull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l ; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l
; P9LE-NEXT: lxvx v2, 0, r3 ; P9LE-NEXT: lxv v2, 0(r3)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromDiffConstsConvdtoull: ; P8BE-LABEL: fromDiffConstsConvdtoull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l ; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
; P8BE-NEXT: lxvd2x v2, 0, r3 ; P8BE-NEXT: lxvd2x v2, 0, r3
; P8BE-NEXT: blr ; P8BE-NEXT: blr
▲ Show 20 Lines • Show All 653 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesentry:
%b.addr = alloca i64, align 8 %b.addr = alloca i64, align 8
store i64 %b, i64* %b.addr, align 8 store i64 %b, i64* %b.addr, align 8
%0 = load fp128, fp128* @A, align 16 %0 = load fp128, fp128* @A, align 16
%1 = load i64, i64* %b.addr, align 8 %1 = load i64, i64* %b.addr, align 8
%2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1) %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
ret fp128 %2 ret fp128 %2
; CHECK-LABEL: insert_exp_qp ; CHECK-LABEL: insert_exp_qp
; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3 ; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
; CHECK-DAG: lxvx [[VECREG:v[0-9]+]] ; CHECK-DAG: lxv [[VECREG:v[0-9]+]]
; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]] ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64) declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define i64 @extract_exp() { define i64 @extract_exp() {
entry: entry:
%0 = load fp128, fp128* @A, align 16 %0 = load fp128, fp128* @A, align 16
%1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0) %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0)
ret i64 %1 ret i64 %1
; CHECK-LABEL: extract_exp ; CHECK-LABEL: extract_exp
; CHECK: lxvx [[VECIN:v[0-9]+]] ; CHECK: lxv [[VECIN:v[0-9]+]]
; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]] ; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]]
; CHECK: mfvsrd r3, [[VECOUT]] ; CHECK: mfvsrd r3, [[VECOUT]]
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.ppc.scalar.extract.expq(fp128) declare i64 @llvm.ppc.scalar.extract.expq(fp128)

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

Show First 20 Lines • Show All 472 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vmrgow v2, v3, v2 ; CHECK-P8-NEXT: vmrgow v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: replace_undefs_in_splat: ; CHECK-P9-LABEL: replace_undefs_in_splat:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vmrgow v2, v3, v2 ; CHECK-P9-NEXT: vmrgow v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-NOVSX-LABEL: replace_undefs_in_splat: ; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
; CHECK-NOVSX: # %bb.0: # %entry ; CHECK-NOVSX: # %bb.0: # %entry
; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI15_1@toc@ha ; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI15_1@toc@ha
; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI15_0@toc@l
Show All 32 Lines
; ;
; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize: ; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: sldi r4, r4, 2 ; CHECK-P9-NEXT: sldi r4, r4, 2
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P9-NEXT: lxsiwzx v2, r3, r4
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize: ; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize:
; CHECK-NOVSX: # %bb.0: # %entry ; CHECK-NOVSX: # %bb.0: # %entry
; CHECK-NOVSX-NEXT: sldi r4, r4, 2 ; CHECK-NOVSX-NEXT: sldi r4, r4, 2
; CHECK-NOVSX-NEXT: vxor v2, v2, v2 ; CHECK-NOVSX-NEXT: vxor v2, v2, v2
; CHECK-NOVSX-NEXT: lwzx r3, r3, r4 ; CHECK-NOVSX-NEXT: lwzx r3, r3, r4
▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/constant-pool.ll

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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI3_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI3_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: __Float128ConstantPool: ; CHECK-P9-LABEL: __Float128ConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret fp128 0xL00000000000000003C00FFFFC5D02B3A ret fp128 0xL00000000000000003C00FFFFC5D02B3A
} }
define <16 x i8> @VectorCharConstantPool() { define <16 x i8> @VectorCharConstantPool() {
; CHECK-LABEL: VectorCharConstantPool: ; CHECK-LABEL: VectorCharConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI4_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI4_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorCharConstantPool: ; CHECK-P9-LABEL: VectorCharConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113> ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
} }
define <8 x i16> @VectorShortConstantPool() { define <8 x i16> @VectorShortConstantPool() {
; CHECK-LABEL: VectorShortConstantPool: ; CHECK-LABEL: VectorShortConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI5_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI5_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorShortConstantPool: ; CHECK-P9-LABEL: VectorShortConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761> ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
} }
define <4 x i32> @VectorIntConstantPool() { define <4 x i32> @VectorIntConstantPool() {
; CHECK-LABEL: VectorIntConstantPool: ; CHECK-LABEL: VectorIntConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI6_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI6_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorIntConstantPool: ; CHECK-P9-LABEL: VectorIntConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645> ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
} }
define <2 x i64> @VectorLongLongConstantPool() { define <2 x i64> @VectorLongLongConstantPool() {
; CHECK-LABEL: VectorLongLongConstantPool: ; CHECK-LABEL: VectorLongLongConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI7_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI7_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorLongLongConstantPool: ; CHECK-P9-LABEL: VectorLongLongConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807> ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
} }
define <1 x i128> @VectorInt128ConstantPool() { define <1 x i128> @VectorInt128ConstantPool() {
; CHECK-LABEL: VectorInt128ConstantPool: ; CHECK-LABEL: VectorInt128ConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI8_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI8_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorInt128ConstantPool: ; CHECK-P9-LABEL: VectorInt128ConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <1 x i128> <i128 -27670116110564327424> ret <1 x i128> <i128 -27670116110564327424>
} }
define <4 x float> @VectorFloatConstantPool() { define <4 x float> @VectorFloatConstantPool() {
; CHECK-LABEL: VectorFloatConstantPool: ; CHECK-LABEL: VectorFloatConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI9_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI9_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorFloatConstantPool: ; CHECK-P9-LABEL: VectorFloatConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000> ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
} }
define <2 x double> @VectorDoubleConstantPool() { define <2 x double> @VectorDoubleConstantPool() {
; CHECK-LABEL: VectorDoubleConstantPool: ; CHECK-LABEL: VectorDoubleConstantPool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1 ; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: VectorDoubleConstantPool: ; CHECK-P9-LABEL: VectorDoubleConstantPool:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P9-NEXT: lxvx vs34, 0, r3 ; CHECK-P9-NEXT: lxv vs34, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
ret <2 x double> <double 2.225070e-308, double 2.225000e-308> ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
} }
define double @two_constants(double %a) { define double @two_constants(double %a) {
; CHECK-LABEL: two_constants: ; CHECK-LABEL: two_constants:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs35, .LCPI15_2@PCREL(0), 1 ; CHECK-NEXT: plxv vs35, .LCPI15_2@PCREL(0), 1
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: three_constants_f128: ; CHECK-P9-LABEL: three_constants_f128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: lxv vs35, 0(r3)
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l
; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: xsaddqp v2, v2, v3
; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: lxv vs35, 0(r3)
; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l
; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: xsaddqp v2, v2, v3
; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: lxv vs35, 0(r3)
; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: xsaddqp v2, v2, v3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
%0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB %0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB
%1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB %1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB
%2 = fadd fp128 %1, 0xL8000000000000000400123851EB771EB %2 = fadd fp128 %1, 0xL8000000000000000400123851EB771EB
ret fp128 %2 ret fp128 %2
} }
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; CHECK-NEXT: xvadddp vs1, vs1, vs2 ; CHECK-NEXT: xvadddp vs1, vs1, vs2
; CHECK-NEXT: xvadddp vs34, vs1, vs0 ; CHECK-NEXT: xvadddp vs34, vs1, vs0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: three_constants_vector: ; CHECK-P9-LABEL: three_constants_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l
; CHECK-P9-NEXT: lxvx vs0, 0, r3 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l
; CHECK-P9-NEXT: lxvx vs2, 0, r3 ; CHECK-P9-NEXT: lxv vs2, 0(r3)
; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0 ; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0
; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2 ; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2
; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0 ; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
%0 = fadd <2 x double> %a, <double 4.555000e+00, double 9.880000e+00> %0 = fadd <2 x double> %a, <double 4.555000e+00, double 9.880000e+00>
%1 = fadd <2 x double> %0, <double 4.555000e+00, double 9.980000e+00> %1 = fadd <2 x double> %0, <double 4.555000e+00, double 9.980000e+00>
%2 = fadd <2 x double> %1, <double 4.555000e+00, double 9.880000e+00> %2 = fadd <2 x double> %1, <double 4.555000e+00, double 9.880000e+00>
ret <2 x double> %2 ret <2 x double> %2
} }

llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll

Show All 17 Lines
; CHECK-NEXT: addi 29, 3, -8 ; CHECK-NEXT: addi 29, 3, -8
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfdu 1, 8(29) ; CHECK-NEXT: lfdu 1, 8(29)
; CHECK-NEXT: bl cos ; CHECK-NEXT: bl cos
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 30, 30, 8 ; CHECK-NEXT: addi 30, 30, 8
; CHECK-NEXT: stfdx 1, 0, 29 ; CHECK-NEXT: stfd 1, 0(29)
; CHECK-NEXT: cmpldi 30, 2040 ; CHECK-NEXT: cmpldi 30, 2040
; CHECK-NEXT: bne 0, .LBB0_1 ; CHECK-NEXT: bne 0, .LBB0_1
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
Show All 22 Lines
; CHECK-NEXT: li 4, 255 ; CHECK-NEXT: li 4, 255
; CHECK-NEXT: addi 3, 3, -8 ; CHECK-NEXT: addi 3, 3, -8
; CHECK-NEXT: mtctr 4 ; CHECK-NEXT: mtctr 4
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB1_1: # %for.body ; CHECK-NEXT: .LBB1_1: # %for.body
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfdu 0, 8(3) ; CHECK-NEXT: lfdu 0, 8(3)
; CHECK-NEXT: xssqrtdp 0, 0 ; CHECK-NEXT: xssqrtdp 0, 0
; CHECK-NEXT: stfdx 0, 0, 3 ; CHECK-NEXT: stfd 0, 0(3)
; CHECK-NEXT: bdnz .LBB1_1 ; CHECK-NEXT: bdnz .LBB1_1
; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: # %bb.2: # %exit
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
%i = phi i64 [ 0, %entry ], [ %next, %for.body ] %i = phi i64 [ 0, %entry ], [ %next, %for.body ]
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llvm/test/CodeGen/PowerPC/extract-and-store.ll

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; CHECK-BE-NEXT: stxvw4x vs0, 0, r5 ; CHECK-BE-NEXT: stxvw4x vs0, 0, r5
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_stores_exceed_vec_size: ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P9-NEXT: lxvx vs35, 0, r3 ; CHECK-P9-NEXT: lxv vs35, 0(r3)
; CHECK-P9-NEXT: li r3, 16 ; CHECK-P9-NEXT: li r3, 16
; CHECK-P9-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-NEXT: stfiwx f0, r5, r3
; CHECK-P9-NEXT: li r3, 20 ; CHECK-P9-NEXT: li r3, 20
; CHECK-P9-NEXT: stxsiwx vs34, r5, r3 ; CHECK-P9-NEXT: stxsiwx vs34, r5, r3
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs35, 0(r5) ; CHECK-P9-NEXT: stxv vs35, 0(r5)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
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llvm/test/CodeGen/PowerPC/f128-aggregates.ll

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; CHECK-NEXT: std r4, 40(r1) ; CHECK-NEXT: std r4, 40(r1)
; CHECK-NEXT: addis r4, r2, .LCPI17_0@toc@ha ; CHECK-NEXT: addis r4, r2, .LCPI17_0@toc@ha
; CHECK-NEXT: cmpwi r3, 1 ; CHECK-NEXT: cmpwi r3, 1
; CHECK-NEXT: std r5, 48(r1) ; CHECK-NEXT: std r5, 48(r1)
; CHECK-NEXT: addi r4, r4, .LCPI17_0@toc@l ; CHECK-NEXT: addi r4, r4, .LCPI17_0@toc@l
; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r6, 56(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r7, 64(r1)
; CHECK-NEXT: std r8, 72(r1) ; CHECK-NEXT: std r8, 72(r1)
; CHECK-NEXT: lxvx v2, 0, r4 ; CHECK-NEXT: lxv v2, 0(r4)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r9, 80(r1)
; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: std r10, 88(r1)
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: li r3, 40
; CHECK-NEXT: lxvx v3, r1, r3
; CHECK-NEXT: addi r3, r1, 72
; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: addi r4, r1, 72
; CHECK-NEXT: lxvx v3, 0, r3
; CHECK-NEXT: std r4, -8(r1)
; CHECK-NEXT: xsaddqp v2, v3, v2 ; CHECK-NEXT: xsaddqp v2, v3, v2
; CHECK-NEXT: lxv v3, 16(r3) ; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: sum_float128: ; CHECK-BE-LABEL: sum_float128:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: std r4, 56(r1) ; CHECK-BE-NEXT: std r4, 56(r1)
; CHECK-BE-NEXT: addis r4, r2, .LCPI17_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI17_0@toc@ha
; CHECK-BE-NEXT: cmpwi r3, 1 ; CHECK-BE-NEXT: cmpwi r3, 1
; CHECK-BE-NEXT: std r5, 64(r1) ; CHECK-BE-NEXT: std r5, 64(r1)
; CHECK-BE-NEXT: addi r4, r4, .LCPI17_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI17_0@toc@l
; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r6, 72(r1)
; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r7, 80(r1)
; CHECK-BE-NEXT: std r8, 88(r1) ; CHECK-BE-NEXT: std r8, 88(r1)
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-NEXT: std r9, 96(r1)
; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: std r10, 104(r1)
; CHECK-BE-NEXT: bltlr cr0 ; CHECK-BE-NEXT: bltlr cr0
; CHECK-BE-NEXT: # %bb.1: # %if.end ; CHECK-BE-NEXT: # %bb.1: # %if.end
; CHECK-BE-NEXT: li r3, 56
; CHECK-BE-NEXT: lxvx v3, r1, r3
; CHECK-BE-NEXT: addi r3, r1, 88
; CHECK-BE-NEXT: std r3, -8(r1)
; CHECK-BE-NEXT: addi r3, r1, 56 ; CHECK-BE-NEXT: addi r3, r1, 56
; CHECK-BE-NEXT: addi r4, r1, 88
; CHECK-BE-NEXT: lxvx v3, 0, r3
; CHECK-BE-NEXT: std r4, -8(r1)
; CHECK-BE-NEXT: xsaddqp v2, v3, v2 ; CHECK-BE-NEXT: xsaddqp v2, v3, v2
; CHECK-BE-NEXT: lxv v3, 16(r3) ; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: xsaddqp v2, v2, v3 ; CHECK-BE-NEXT: xsaddqp v2, v2, v3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: sum_float128: ; CHECK-P8-LABEL: sum_float128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
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llvm/test/CodeGen/PowerPC/f128-arith.ll

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Linesentry:
%div = fdiv fp128 %0, %0 %div = fdiv fp128 %0, %0
store fp128 %div, fp128* %res, align 16 store fp128 %div, fp128* %res, align 16
ret void ret void
} }
define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) { define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
; CHECK-LABEL: testLdNSt: ; CHECK-LABEL: testLdNSt:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 4 ; CHECK-NEXT: li r5, 4
; CHECK-NEXT: addi r4, r4, 8 ; CHECK-NEXT: lxvx vs0, r3, r5
; CHECK-NEXT: lxvx vs0, 0, r3 ; CHECK-NEXT: li r3, 8
; CHECK-NEXT: stxvx vs0, 0, r4 ; CHECK-NEXT: stxvx vs0, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: testLdNSt: ; CHECK-P8-LABEL: testLdNSt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addi r3, r3, 4 ; CHECK-P8-NEXT: addi r3, r3, 4
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: addi r3, r4, 8 ; CHECK-P8-NEXT: addi r3, r4, 8
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis r3, r2, a@toc@ha ; CHECK-NEXT: addis r3, r2, a@toc@ha
; CHECK-NEXT: addi r3, r3, a@toc@l ; CHECK-NEXT: addi r3, r3, a@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b@toc@ha ; CHECK-NEXT: addis r3, r2, b@toc@ha
; CHECK-NEXT: addi r3, r3, b@toc@l ; CHECK-NEXT: addi r3, r3, b@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: bl fmodf128 ; CHECK-NEXT: bl fmodf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_frem: ; CHECK-P8-LABEL: qp_frem:
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llvm/test/CodeGen/PowerPC/f128-compare.ll

Show All 9 Lines
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @greater_qp() { define dso_local signext i32 @greater_qp() {
; CHECK-LABEL: greater_qp: ; CHECK-LABEL: greater_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iselgt r3, r4, r3 ; CHECK-NEXT: iselgt r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_qp: ; CHECK-P8-LABEL: greater_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
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; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @less_qp() { define dso_local signext i32 @less_qp() {
; CHECK-LABEL: less_qp: ; CHECK-LABEL: less_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: isellt r3, r4, r3 ; CHECK-NEXT: isellt r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_qp: ; CHECK-P8-LABEL: less_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
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} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @greater_eq_qp() { define dso_local signext i32 @greater_eq_qp() {
; CHECK-LABEL: greater_eq_qp: ; CHECK-LABEL: greater_eq_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: cror 4*cr5+lt, un, lt ; CHECK-NEXT: cror 4*cr5+lt, un, lt
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_eq_qp: ; CHECK-P8-LABEL: greater_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
Show All 27 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @less_eq_qp() { define dso_local signext i32 @less_eq_qp() {
; CHECK-LABEL: less_eq_qp: ; CHECK-LABEL: less_eq_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: cror 4*cr5+lt, un, gt ; CHECK-NEXT: cror 4*cr5+lt, un, gt
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_eq_qp: ; CHECK-P8-LABEL: less_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
Show All 30 Lines
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @equal_qp() { define dso_local signext i32 @equal_qp() {
; CHECK-LABEL: equal_qp: ; CHECK-LABEL: equal_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iseleq r3, r4, r3 ; CHECK-NEXT: iseleq r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: equal_qp: ; CHECK-P8-LABEL: equal_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
Show All 26 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @not_greater_qp() { define dso_local signext i32 @not_greater_qp() {
; CHECK-LABEL: not_greater_qp: ; CHECK-LABEL: not_greater_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iselgt r3, 0, r3 ; CHECK-NEXT: iselgt r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_greater_qp: ; CHECK-P8-LABEL: not_greater_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
Show All 29 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @not_less_qp() { define dso_local signext i32 @not_less_qp() {
; CHECK-LABEL: not_less_qp: ; CHECK-LABEL: not_less_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: isellt r3, 0, r3 ; CHECK-NEXT: isellt r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_less_qp: ; CHECK-P8-LABEL: not_less_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
Show All 27 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @not_greater_eq_qp() { define dso_local signext i32 @not_greater_eq_qp() {
; CHECK-LABEL: not_greater_eq_qp: ; CHECK-LABEL: not_greater_eq_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, lt, un ; CHECK-NEXT: crnor 4*cr5+lt, lt, un
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_greater_eq_qp: ; CHECK-P8-LABEL: not_greater_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
Show All 27 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @not_less_eq_qp() { define dso_local signext i32 @not_less_eq_qp() {
; CHECK-LABEL: not_less_eq_qp: ; CHECK-LABEL: not_less_eq_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, gt, un ; CHECK-NEXT: crnor 4*cr5+lt, gt, un
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_less_eq_qp: ; CHECK-P8-LABEL: not_less_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
Show All 29 Lines
} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @not_equal_qp() { define dso_local signext i32 @not_equal_qp() {
; CHECK-LABEL: not_equal_qp: ; CHECK-LABEL: not_equal_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iseleq r3, 0, r3 ; CHECK-NEXT: iseleq r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_equal_qp: ; CHECK-P8-LABEL: not_equal_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
Show All 27 Lines
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @greater_sel_qp() { define fp128 @greater_sel_qp() {
; CHECK-LABEL: greater_sel_qp: ; CHECK-LABEL: greater_sel_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: bgtlr cr0 ; CHECK-NEXT: bgtlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_sel_qp: ; CHECK-P8-LABEL: greater_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
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} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define fp128 @less_sel_qp() { define fp128 @less_sel_qp() {
; CHECK-LABEL: less_sel_qp: ; CHECK-LABEL: less_sel_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_sel_qp: ; CHECK-P8-LABEL: less_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
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} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define fp128 @greater_eq_sel_qp() { define fp128 @greater_eq_sel_qp() {
; CHECK-LABEL: greater_eq_sel_qp: ; CHECK-LABEL: greater_eq_sel_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, un, lt ; CHECK-NEXT: crnor 4*cr5+lt, un, lt
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_eq_sel_qp: ; CHECK-P8-LABEL: greater_eq_sel_qp:
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} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define fp128 @less_eq_sel_qp() { define fp128 @less_eq_sel_qp() {
; CHECK-LABEL: less_eq_sel_qp: ; CHECK-LABEL: less_eq_sel_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, un, gt ; CHECK-NEXT: crnor 4*cr5+lt, un, gt
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_eq_sel_qp: ; CHECK-P8-LABEL: less_eq_sel_qp:
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} }
; Function Attrs: noinline nounwind optnone ; Function Attrs: noinline nounwind optnone
define fp128 @equal_sel_qp() { define fp128 @equal_sel_qp() {
; CHECK-LABEL: equal_sel_qp: ; CHECK-LABEL: equal_sel_qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha
; CHECK-NEXT: addi r3, r3, b_qp@toc@l ; CHECK-NEXT: addi r3, r3, b_qp@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: beqlr cr0 ; CHECK-NEXT: beqlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: equal_sel_qp: ; CHECK-P8-LABEL: equal_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/f128-conv.ll

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} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2dp_02(double* nocapture %res) { define void @qpConv2dp_02(double* nocapture %res) {
; CHECK-LABEL: qpConv2dp_02: ; CHECK-LABEL: qpConv2dp_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-NEXT: lxvx v2, 0, r4 ; CHECK-NEXT: lxv v2, 0(r4)
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r3) ; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2dp_02: ; CHECK-P8-LABEL: qpConv2dp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfdx f1, 0, r30 ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* @f128global, align 16 %0 = load fp128, fp128* @f128global, align 16
%conv = fptrunc fp128 %0 to double %conv = fptrunc fp128 %0 to double
store double %conv, double* %res, align 8 store double %conv, double* %res, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) { define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2dp_03: ; CHECK-LABEL: qpConv2dp_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha
; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC7@toc@l(r5) ; CHECK-NEXT: ld r5, .LC7@toc@l(r5)
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxv v2, 0(r5)
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2dp_03: ; CHECK-P8-LABEL: qpConv2dp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
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; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lvx v3, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfdx f1, 0, r30 ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16 %1 = load fp128, fp128* %b, align 16
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} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2sp_02(float* nocapture %res) { define void @qpConv2sp_02(float* nocapture %res) {
; CHECK-LABEL: qpConv2sp_02: ; CHECK-LABEL: qpConv2sp_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-NEXT: lxvx v2, 0, r4 ; CHECK-NEXT: lxv v2, 0(r4)
; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xscvqpdpo v2, v2
; CHECK-NEXT: xsrsp f0, v2 ; CHECK-NEXT: xsrsp f0, v2
; CHECK-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sp_02: ; CHECK-P8-LABEL: qpConv2sp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: lvx v2, 0, r4
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfsx f1, 0, r30 ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* @f128global, align 16 %0 = load fp128, fp128* @f128global, align 16
%conv = fptrunc fp128 %0 to float %conv = fptrunc fp128 %0 to float
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; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: lvx v3, 0, r4
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfsx f1, 0, r30 ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, fp128* %a, align 16 %0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16 %1 = load fp128, fp128* %b, align 16
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2qp_02(double* nocapture readonly %a) { define void @dpConv2qp_02(double* nocapture readonly %a) {
; CHECK-LABEL: dpConv2qp_02: ; CHECK-LABEL: dpConv2qp_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v2, 0(r3) ; CHECK-NEXT: lxsd v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: dpConv2qp_02: ; CHECK-P8-LABEL: dpConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfdx f1, 0, r3 ; CHECK-P8-NEXT: lfd f1, 0(r3)
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
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define void @dpConv2qp_02b(double* nocapture readonly %a, i32 signext %idx) { define void @dpConv2qp_02b(double* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: dpConv2qp_02b: ; CHECK-LABEL: dpConv2qp_02b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: lxsdx v2, r3, r4 ; CHECK-NEXT: lxsdx v2, r3, r4
; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: dpConv2qp_02b: ; CHECK-P8-LABEL: dpConv2qp_02b:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2qp_02(float* nocapture readonly %a) { define void @spConv2qp_02(float* nocapture readonly %a) {
; CHECK-LABEL: spConv2qp_02: ; CHECK-LABEL: spConv2qp_02:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxssp v2, 0(r3) ; CHECK-NEXT: lxssp v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: spConv2qp_02: ; CHECK-P8-LABEL: spConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfsx f1, 0, r3 ; CHECK-P8-NEXT: lfs f1, 0(r3)
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
define void @spConv2qp_02b(float* nocapture readonly %a, i32 signext %idx) { define void @spConv2qp_02b(float* nocapture readonly %a, i32 signext %idx) {
; CHECK-LABEL: spConv2qp_02b: ; CHECK-LABEL: spConv2qp_02b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 2 ; CHECK-NEXT: sldi r4, r4, 2
; CHECK-NEXT: lxsspx v2, r3, r4 ; CHECK-NEXT: lxsspx v2, r3, r4
; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: spConv2qp_02b: ; CHECK-P8-LABEL: spConv2qp_02b:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
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llvm/test/CodeGen/PowerPC/f128-passByValue.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: -check-prefix=CHECK-P8 ; RUN: -check-prefix=CHECK-P8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @loadConstant() { define fp128 @loadConstant() {
; CHECK-LABEL: loadConstant: ; CHECK-LABEL: loadConstant:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: loadConstant: ; CHECK-P8-LABEL: loadConstant:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 1 ; CHECK-P8-NEXT: lis r3, 1
; CHECK-P8-NEXT: ori r3, r3, 5 ; CHECK-P8-NEXT: ori r3, r3, 5
; CHECK-P8-NEXT: rldic r4, r3, 46, 1 ; CHECK-P8-NEXT: rldic r4, r3, 46, 1
; CHECK-P8-NEXT: li r3, 0 ; CHECK-P8-NEXT: li r3, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
ret fp128 0xL00000000000000004001400000000000 ret fp128 0xL00000000000000004001400000000000
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define fp128 @loadConstant2(fp128 %a, fp128 %b) { define fp128 @loadConstant2(fp128 %a, fp128 %b) {
; CHECK-LABEL: loadConstant2: ; CHECK-LABEL: loadConstant2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: loadConstant2: ; CHECK-P8-LABEL: loadConstant2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
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; Passing a mix of float128 and vector parameters. ; Passing a mix of float128 and vector parameters.
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1, define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
; CHECK-LABEL: mixParam_03: ; CHECK-LABEL: mixParam_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld r3, 104(r1) ; CHECK-NEXT: ld r3, 104(r1)
; CHECK-NEXT: stxv v2, 0(r9) ; CHECK-NEXT: stxv v2, 0(r9)
; CHECK-NEXT: stxvx v3, 0, r3 ; CHECK-NEXT: stxv v3, 0(r3)
; CHECK-NEXT: mtvsrwa v3, r10 ; CHECK-NEXT: mtvsrwa v3, r10
; CHECK-NEXT: lxv v2, 0(r9) ; CHECK-NEXT: lxv v2, 0(r9)
; CHECK-NEXT: xscvsdqp v3, v3 ; CHECK-NEXT: xscvsdqp v3, v3
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r5) ; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
Show All 23 Lines
; CHECK-P8-NEXT: mr r5, r3 ; CHECK-P8-NEXT: mr r5, r3
; CHECK-P8-NEXT: mr r6, r4 ; CHECK-P8-NEXT: mr r6, r4
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
; CHECK-P8-NEXT: mr r4, r29 ; CHECK-P8-NEXT: mr r4, r29
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfdx f1, 0, r28 ; CHECK-P8-NEXT: stfd f1, 0(r28)
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
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; CHECK-P8-NEXT: mr r5, r3 ; CHECK-P8-NEXT: mr r5, r3
; CHECK-P8-NEXT: mr r6, r4 ; CHECK-P8-NEXT: mr r6, r4
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
; CHECK-P8-NEXT: mr r4, r29 ; CHECK-P8-NEXT: mr r4, r29
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfdx f1, 0, r28 ; CHECK-P8-NEXT: stfd f1, 0(r28)
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1, fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
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llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

Show First 20 Lines • Show All 407 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) { define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) {
; CHECK-LABEL: qpConv2udw_testXForm: ; CHECK-LABEL: qpConv2udw_testXForm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxv v2, 0(r5)
; CHECK-NEXT: xscvqpudz v2, v2 ; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2udw_testXForm: ; CHECK-P8-LABEL: qpConv2udw_testXForm:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
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llvm/test/CodeGen/PowerPC/f128_ldst.ll

Show All 25 Linesentry:
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_unalign16___float128___float128(i8* nocapture readonly %ptr) { define dso_local fp128 @ld_unalign16___float128___float128(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_unalign16___float128___float128: ; CHECK-LABEL: ld_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1
%0 = bitcast i8* %add.ptr to fp128* %0 = bitcast i8* %add.ptr to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_align16___float128___float128(i8* nocapture readonly %ptr) { define dso_local fp128 @ld_align16___float128___float128(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16___float128___float128: ; CHECK-LABEL: ld_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: li r4, 8
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
%0 = bitcast i8* %add.ptr to fp128* %0 = bitcast i8* %add.ptr to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesentry:
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_or___float128___float128(i64 %ptr, i8 zeroext %off) { define dso_local fp128 @ld_or___float128___float128(i64 %ptr, i8 zeroext %off) {
; CHECK-LABEL: ld_or___float128___float128: ; CHECK-LABEL: ld_or___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
Show All 14 Linesentry:
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_not_disjoint16___float128___float128(i64 %ptr) { define dso_local fp128 @ld_not_disjoint16___float128___float128(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16___float128___float128: ; CHECK-LABEL: ld_not_disjoint16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_disjoint_unalign16___float128___float128(i64 %ptr) { define dso_local fp128 @ld_disjoint_unalign16___float128___float128(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_unalign16___float128___float128: ; CHECK-LABEL: ld_disjoint_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: li r4, 6
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_disjoint_align16___float128___float128(i64 %ptr) { define dso_local fp128 @ld_disjoint_align16___float128___float128(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16___float128___float128: ; CHECK-LABEL: ld_disjoint_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 24 ; CHECK-NEXT: li r4, 24
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_not_disjoint32___float128___float128(i64 %ptr) { define dso_local fp128 @ld_not_disjoint32___float128___float128(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint32___float128___float128: ; CHECK-LABEL: ld_not_disjoint32___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
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; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_not_disjoint64___float128___float128(i64 %ptr) { define dso_local fp128 @ld_not_disjoint64___float128___float128(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint64___float128___float128: ; CHECK-P10-LABEL: ld_not_disjoint64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: ld_not_disjoint64___float128___float128: ; CHECK-PREP10-LABEL: ld_not_disjoint64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-PREP10-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lxvx v2, 0, r3 ; CHECK-PREP10-NEXT: lxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
%1 = load fp128, fp128* %0, align 16 %1 = load fp128, fp128* %0, align 16
ret fp128 %1 ret fp128 %1
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesentry:
ret fp128 %1 ret fp128 %1
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_unalign16___float128___float128() { define dso_local fp128 @ld_cst_unalign16___float128___float128() {
; CHECK-LABEL: ld_cst_unalign16___float128___float128: ; CHECK-LABEL: ld_cst_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 255 to fp128*), align 16 %0 = load fp128, fp128* inttoptr (i64 255 to fp128*), align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_align16___float128___float128() { define dso_local fp128 @ld_cst_align16___float128___float128() {
; CHECK-LABEL: ld_cst_align16___float128___float128: ; CHECK-LABEL: ld_cst_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 4080(0) ; CHECK-NEXT: lxv v2, 4080(0)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 4080 to fp128*), align 16 %0 = load fp128, fp128* inttoptr (i64 4080 to fp128*), align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_unalign32___float128___float128() { define dso_local fp128 @ld_cst_unalign32___float128___float128() {
; CHECK-P10-LABEL: ld_cst_unalign32___float128___float128: ; CHECK-P10-LABEL: ld_cst_unalign32___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 99999 ; CHECK-P10-NEXT: pli r3, 99999
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: ld_cst_unalign32___float128___float128: ; CHECK-PREP10-LABEL: ld_cst_unalign32___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 1 ; CHECK-PREP10-NEXT: lis r3, 1
; CHECK-PREP10-NEXT: ori r3, r3, 34463 ; CHECK-PREP10-NEXT: ori r3, r3, 34463
; CHECK-PREP10-NEXT: lxvx v2, 0, r3 ; CHECK-PREP10-NEXT: lxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 99999 to fp128*), align 16 %0 = load fp128, fp128* inttoptr (i64 99999 to fp128*), align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_align32___float128___float128() { define dso_local fp128 @ld_cst_align32___float128___float128() {
; CHECK-P10-LABEL: ld_cst_align32___float128___float128: ; CHECK-P10-LABEL: ld_cst_align32___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 9999900 ; CHECK-P10-NEXT: pli r3, 9999900
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: ld_cst_align32___float128___float128: ; CHECK-PREP10-LABEL: ld_cst_align32___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 152 ; CHECK-PREP10-NEXT: lis r3, 152
; CHECK-PREP10-NEXT: ori r3, r3, 38428 ; CHECK-PREP10-NEXT: ori r3, r3, 38428
; CHECK-PREP10-NEXT: lxvx v2, 0, r3 ; CHECK-PREP10-NEXT: lxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 9999900 to fp128*), align 16 %0 = load fp128, fp128* inttoptr (i64 9999900 to fp128*), align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_unalign64___float128___float128() { define dso_local fp128 @ld_cst_unalign64___float128___float128() {
; CHECK-P10-LABEL: ld_cst_unalign64___float128___float128: ; CHECK-P10-LABEL: ld_cst_unalign64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lxvx v2, 0, r4 ; CHECK-P10-NEXT: lxv v2, 0(r4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: ld_cst_unalign64___float128___float128: ; CHECK-PREP10-LABEL: ld_cst_unalign64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-PREP10-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-PREP10-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-PREP10-NEXT: lxvx v2, 0, r3 ; CHECK-PREP10-NEXT: lxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 1000000000001 to fp128*), align 16 %0 = load fp128, fp128* inttoptr (i64 1000000000001 to fp128*), align 16
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define dso_local fp128 @ld_cst_align64___float128___float128() { define dso_local fp128 @ld_cst_align64___float128___float128() {
; CHECK-P10-LABEL: ld_cst_align64___float128___float128: ; CHECK-P10-LABEL: ld_cst_align64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: ld_cst_align64___float128___float128: ; CHECK-PREP10-LABEL: ld_cst_align64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lxvx v2, 0, r3 ; CHECK-PREP10-NEXT: lxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load fp128, fp128* inttoptr (i64 1000000000000 to fp128*), align 4096 %0 = load fp128, fp128* inttoptr (i64 1000000000000 to fp128*), align 4096
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_0___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_0___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-LABEL: st_0___float128___float128: ; CHECK-LABEL: st_0___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to fp128* %0 = inttoptr i64 %ptr to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_unalign16___float128___float128(i8* nocapture %ptr, fp128 %str) { define dso_local void @st_unalign16___float128___float128(i8* nocapture %ptr, fp128 %str) {
; CHECK-LABEL: st_unalign16___float128___float128: ; CHECK-LABEL: st_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1
%0 = bitcast i8* %add.ptr to fp128* %0 = bitcast i8* %add.ptr to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_align16___float128___float128(i8* nocapture %ptr, fp128 %str) { define dso_local void @st_align16___float128___float128(i8* nocapture %ptr, fp128 %str) {
; CHECK-LABEL: st_align16___float128___float128: ; CHECK-LABEL: st_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: li r4, 8
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
%0 = bitcast i8* %add.ptr to fp128* %0 = bitcast i8* %add.ptr to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_or1___float128___float128(i64 %ptr, i8 zeroext %off, fp128 %str) { define dso_local void @st_or1___float128___float128(i64 %ptr, i8 zeroext %off, fp128 %str) {
; CHECK-LABEL: st_or1___float128___float128: ; CHECK-LABEL: st_or1___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
Show All 14 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_not_disjoint16___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_not_disjoint16___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-LABEL: st_not_disjoint16___float128___float128: ; CHECK-LABEL: st_not_disjoint16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_disjoint_unalign16___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_disjoint_unalign16___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-LABEL: st_disjoint_unalign16___float128___float128: ; CHECK-LABEL: st_disjoint_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: li r4, 6
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_disjoint_align16___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_disjoint_align16___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-LABEL: st_disjoint_align16___float128___float128: ; CHECK-LABEL: st_disjoint_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 24 ; CHECK-NEXT: li r4, 24
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_not_disjoint32___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_not_disjoint32___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-LABEL: st_not_disjoint32___float128___float128: ; CHECK-LABEL: st_not_disjoint32___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_not_disjoint64___float128___float128(i64 %ptr, fp128 %str) { define dso_local void @st_not_disjoint64___float128___float128(i64 %ptr, fp128 %str) {
; CHECK-P10-LABEL: st_not_disjoint64___float128___float128: ; CHECK-P10-LABEL: st_not_disjoint64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: st_not_disjoint64___float128___float128: ; CHECK-PREP10-LABEL: st_not_disjoint64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-PREP10-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: stxvx v2, 0, r3 ; CHECK-PREP10-NEXT: stxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to fp128* %0 = inttoptr i64 %or to fp128*
store fp128 %str, fp128* %0, align 16 store fp128 %str, fp128* %0, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_unalign16___float128___float128(fp128 %str) { define dso_local void @st_cst_unalign16___float128___float128(fp128 %str) {
; CHECK-LABEL: st_cst_unalign16___float128___float128: ; CHECK-LABEL: st_cst_unalign16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 255 to fp128*), align 16 store fp128 %str, fp128* inttoptr (i64 255 to fp128*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_align16___float128___float128(fp128 %str) { define dso_local void @st_cst_align16___float128___float128(fp128 %str) {
; CHECK-LABEL: st_cst_align16___float128___float128: ; CHECK-LABEL: st_cst_align16___float128___float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxv v2, 4080(0) ; CHECK-NEXT: stxv v2, 4080(0)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 4080 to fp128*), align 16 store fp128 %str, fp128* inttoptr (i64 4080 to fp128*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_unalign32___float128___float128(fp128 %str) { define dso_local void @st_cst_unalign32___float128___float128(fp128 %str) {
; CHECK-P10-LABEL: st_cst_unalign32___float128___float128: ; CHECK-P10-LABEL: st_cst_unalign32___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 99999 ; CHECK-P10-NEXT: pli r3, 99999
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: st_cst_unalign32___float128___float128: ; CHECK-PREP10-LABEL: st_cst_unalign32___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 1 ; CHECK-PREP10-NEXT: lis r3, 1
; CHECK-PREP10-NEXT: ori r3, r3, 34463 ; CHECK-PREP10-NEXT: ori r3, r3, 34463
; CHECK-PREP10-NEXT: stxvx v2, 0, r3 ; CHECK-PREP10-NEXT: stxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 99999 to fp128*), align 16 store fp128 %str, fp128* inttoptr (i64 99999 to fp128*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_align32___float128___float128(fp128 %str) { define dso_local void @st_cst_align32___float128___float128(fp128 %str) {
; CHECK-P10-LABEL: st_cst_align32___float128___float128: ; CHECK-P10-LABEL: st_cst_align32___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 9999900 ; CHECK-P10-NEXT: pli r3, 9999900
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: st_cst_align32___float128___float128: ; CHECK-PREP10-LABEL: st_cst_align32___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 152 ; CHECK-PREP10-NEXT: lis r3, 152
; CHECK-PREP10-NEXT: ori r3, r3, 38428 ; CHECK-PREP10-NEXT: ori r3, r3, 38428
; CHECK-PREP10-NEXT: stxvx v2, 0, r3 ; CHECK-PREP10-NEXT: stxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 9999900 to fp128*), align 16 store fp128 %str, fp128* inttoptr (i64 9999900 to fp128*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_unalign64___float128___float128(fp128 %str) { define dso_local void @st_cst_unalign64___float128___float128(fp128 %str) {
; CHECK-P10-LABEL: st_cst_unalign64___float128___float128: ; CHECK-P10-LABEL: st_cst_unalign64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: stxvx v2, 0, r4 ; CHECK-P10-NEXT: stxv v2, 0(r4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: st_cst_unalign64___float128___float128: ; CHECK-PREP10-LABEL: st_cst_unalign64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-PREP10-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-PREP10-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-PREP10-NEXT: stxvx v2, 0, r3 ; CHECK-PREP10-NEXT: stxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 1000000000001 to fp128*), align 16 store fp128 %str, fp128* inttoptr (i64 1000000000001 to fp128*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define dso_local void @st_cst_align64___float128___float128(fp128 %str) { define dso_local void @st_cst_align64___float128___float128(fp128 %str) {
; CHECK-P10-LABEL: st_cst_align64___float128___float128: ; CHECK-P10-LABEL: st_cst_align64___float128___float128:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-PREP10-LABEL: st_cst_align64___float128___float128: ; CHECK-PREP10-LABEL: st_cst_align64___float128___float128:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: stxvx v2, 0, r3 ; CHECK-PREP10-NEXT: stxv v2, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
store fp128 %str, fp128* inttoptr (i64 1000000000000 to fp128*), align 4096 store fp128 %str, fp128* inttoptr (i64 1000000000000 to fp128*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn ; Function Attrs: nofree norecurse nounwind willreturn
define dso_local void @testGlob128PtrPlus0() { define dso_local void @testGlob128PtrPlus0() {
; CHECK-P10-LE-LABEL: testGlob128PtrPlus0: ; CHECK-P10-LE-LABEL: testGlob128PtrPlus0:
; CHECK-P10-LE: # %bb.0: # %entry ; CHECK-P10-LE: # %bb.0: # %entry
; CHECK-P10-LE-NEXT: plxv vs0, GlobLd128@PCREL(0), 1 ; CHECK-P10-LE-NEXT: plxv vs0, GlobLd128@PCREL(0), 1
; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt128@PCREL(0), 1 ; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt128@PCREL(0), 1
; CHECK-P10-LE-NEXT: blr ; CHECK-P10-LE-NEXT: blr
; ;
; CHECK-P10-BE-LABEL: testGlob128PtrPlus0: ; CHECK-P10-BE-LABEL: testGlob128PtrPlus0:
; CHECK-P10-BE: # %bb.0: # %entry ; CHECK-P10-BE: # %bb.0: # %entry
; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd128@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd128@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd128@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd128@toc@l
; CHECK-P10-BE-NEXT: lxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: lxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt128@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt128@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt128@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt128@toc@l
; CHECK-P10-BE-NEXT: stxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: stxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: blr ; CHECK-P10-BE-NEXT: blr
; ;
; CHECK-PREP10-LABEL: testGlob128PtrPlus0: ; CHECK-PREP10-LABEL: testGlob128PtrPlus0:
; CHECK-PREP10: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: addis r3, r2, GlobLd128@toc@ha ; CHECK-PREP10-NEXT: addis r3, r2, GlobLd128@toc@ha
; CHECK-PREP10-NEXT: addi r3, r3, GlobLd128@toc@l ; CHECK-PREP10-NEXT: addi r3, r3, GlobLd128@toc@l
; CHECK-PREP10-NEXT: lxvx vs0, 0, r3 ; CHECK-PREP10-NEXT: lxv vs0, 0(r3)
; CHECK-PREP10-NEXT: addis r3, r2, GlobSt128@toc@ha ; CHECK-PREP10-NEXT: addis r3, r2, GlobSt128@toc@ha
; CHECK-PREP10-NEXT: addi r3, r3, GlobSt128@toc@l ; CHECK-PREP10-NEXT: addi r3, r3, GlobSt128@toc@l
; CHECK-PREP10-NEXT: stxvx vs0, 0, r3 ; CHECK-PREP10-NEXT: stxv vs0, 0(r3)
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load fp128, fp128* getelementptr inbounds ([20 x fp128], [20 x fp128]* @GlobLd128, i64 0, i64 0), align 16 %0 = load fp128, fp128* getelementptr inbounds ([20 x fp128], [20 x fp128]* @GlobLd128, i64 0, i64 0), align 16
store fp128 %0, fp128* getelementptr inbounds ([20 x fp128], [20 x fp128]* @GlobSt128, i64 0, i64 0), align 16 store fp128 %0, fp128* getelementptr inbounds ([20 x fp128], [20 x fp128]* @GlobSt128, i64 0, i64 0), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn ; Function Attrs: nofree norecurse nounwind willreturn
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll

Show All 11 Lines
%SomeStruct = type { double } %SomeStruct = type { double }
; ELF64VSX-LABEL: SomeStructCtor ; ELF64VSX-LABEL: SomeStructCtor
define linkonce_odr void @SomeStructCtor(%SomeStruct* %this, double %V) unnamed_addr align 2 { define linkonce_odr void @SomeStructCtor(%SomeStruct* %this, double %V) unnamed_addr align 2 {
entry: entry:
%this.addr = alloca %SomeStruct*, align 8 %this.addr = alloca %SomeStruct*, align 8
%V.addr = alloca double, align 8 %V.addr = alloca double, align 8
store %SomeStruct* %this, %SomeStruct** %this.addr, align 8 store %SomeStruct* %this, %SomeStruct** %this.addr, align 8
; ELF64VSX: stfdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}} ; ELF64VSX: stfd {{[0-9][0-9]?}}, -{{[1-9][0-9]?}}({{[1-9][0-9]?}})
store double %V, double* %V.addr, align 8 store double %V, double* %V.addr, align 8
%this1 = load %SomeStruct*, %SomeStruct** %this.addr %this1 = load %SomeStruct*, %SomeStruct** %this.addr
%Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0 %Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0
; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}} ; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
%0 = load double, double* %V.addr, align 8 %0 = load double, double* %V.addr, align 8
store double %0, double* %Val, align 8 store double %0, double* %Val, align 8
ret void ret void
} }

llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

Show All 36 Lines
; CHECK-NEXT: addis 4, 2, a15@toc@ha ; CHECK-NEXT: addis 4, 2, a15@toc@ha
; CHECK-NEXT: lfd 1, a1@toc@l(3) ; CHECK-NEXT: lfd 1, a1@toc@l(3)
; CHECK-NEXT: addis 3, 2, a2@toc@ha ; CHECK-NEXT: addis 3, 2, a2@toc@ha
; CHECK-NEXT: addi 5, 5, a16@toc@l ; CHECK-NEXT: addi 5, 5, a16@toc@l
; CHECK-NEXT: addi 6, 6, a17@toc@l ; CHECK-NEXT: addi 6, 6, a17@toc@l
; CHECK-NEXT: ld 4, a15@toc@l(4) ; CHECK-NEXT: ld 4, a15@toc@l(4)
; CHECK-NEXT: lfd 2, a2@toc@l(3) ; CHECK-NEXT: lfd 2, a2@toc@l(3)
; CHECK-NEXT: addis 3, 2, a3@toc@ha ; CHECK-NEXT: addis 3, 2, a3@toc@ha
; CHECK-NEXT: lxvx 34, 0, 6 ; CHECK-NEXT: lxv 34, 0(6)
; CHECK-NEXT: lxvx 0, 0, 5 ; CHECK-NEXT: lxv 0, 0(5)
; CHECK-NEXT: li 5, 152 ; CHECK-NEXT: li 5, 152
; CHECK-NEXT: lfd 3, a3@toc@l(3) ; CHECK-NEXT: lfd 3, a3@toc@l(3)
; CHECK-NEXT: addis 3, 2, a4@toc@ha ; CHECK-NEXT: addis 3, 2, a4@toc@ha
; CHECK-NEXT: lfd 4, a4@toc@l(3) ; CHECK-NEXT: lfd 4, a4@toc@l(3)
; CHECK-NEXT: addis 3, 2, a5@toc@ha ; CHECK-NEXT: addis 3, 2, a5@toc@ha
; CHECK-NEXT: lfd 5, a5@toc@l(3) ; CHECK-NEXT: lfd 5, a5@toc@l(3)
; CHECK-NEXT: addis 3, 2, a6@toc@ha ; CHECK-NEXT: addis 3, 2, a6@toc@ha
; CHECK-NEXT: lfd 6, a6@toc@l(3) ; CHECK-NEXT: lfd 6, a6@toc@l(3)
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fma-combine.ll

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Linesentry:
%add = fsub double %mul, %a %add = fsub double %mul, %a
ret double %add ret double %add
} }
define dso_local float @fma_combine_no_ice() { define dso_local float @fma_combine_no_ice() {
; CHECK-FAST-LABEL: fma_combine_no_ice: ; CHECK-FAST-LABEL: fma_combine_no_ice:
; CHECK-FAST: # %bb.0: ; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-FAST-NEXT: addis 4, 2, .LCPI4_1@toc@ha
; CHECK-FAST-NEXT: lfs 0, .LCPI4_0@toc@l(3) ; CHECK-FAST-NEXT: lfs 0, .LCPI4_0@toc@l(3)
; CHECK-FAST-NEXT: lfsx 2, 0, 3 ; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_1@toc@ha
; CHECK-FAST-NEXT: lfs 2, 0(3)
; CHECK-FAST-NEXT: lfs 3, .LCPI4_1@toc@l(3)
; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_2@toc@ha
; CHECK-FAST-NEXT: lfs 3, .LCPI4_1@toc@l(4)
; CHECK-FAST-NEXT: lfs 1, .LCPI4_2@toc@l(3) ; CHECK-FAST-NEXT: lfs 1, .LCPI4_2@toc@l(3)
; CHECK-FAST-NEXT: xsmaddasp 3, 2, 0 ; CHECK-FAST-NEXT: xsmaddasp 3, 2, 0
; CHECK-FAST-NEXT: xsmaddasp 1, 2, 3 ; CHECK-FAST-NEXT: xsmaddasp 1, 2, 3
; CHECK-FAST-NEXT: xsnmsubasp 1, 3, 2 ; CHECK-FAST-NEXT: xsnmsubasp 1, 3, 2
; CHECK-FAST-NEXT: blr ; CHECK-FAST-NEXT: blr
; ;
; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice: ; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice:
; CHECK-FAST-NOVSX: # %bb.0: ; CHECK-FAST-NOVSX: # %bb.0:
; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI4_0@toc@l(3) ; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI4_0@toc@l(3)
; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_1@toc@ha
; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3) ; CHECK-FAST-NOVSX-NEXT: lfs 1, 0(3)
; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_1@toc@l(3) ; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_1@toc@l(3)
; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI4_2@toc@ha
; CHECK-FAST-NOVSX-NEXT: fmadds 0, 1, 2, 0 ; CHECK-FAST-NOVSX-NEXT: fmadds 0, 1, 2, 0
; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_2@toc@l(3) ; CHECK-FAST-NOVSX-NEXT: lfs 2, .LCPI4_2@toc@l(3)
; CHECK-FAST-NOVSX-NEXT: fmadds 2, 1, 0, 2 ; CHECK-FAST-NOVSX-NEXT: fmadds 2, 1, 0, 2
; CHECK-FAST-NOVSX-NEXT: fnmsubs 1, 0, 1, 2 ; CHECK-FAST-NOVSX-NEXT: fnmsubs 1, 0, 1, 2
; CHECK-FAST-NOVSX-NEXT: blr ; CHECK-FAST-NOVSX-NEXT: blr
; ;
; CHECK-LABEL: fma_combine_no_ice: ; CHECK-LABEL: fma_combine_no_ice:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI4_1@toc@ha
; CHECK-NEXT: lfs 0, .LCPI4_0@toc@l(3) ; CHECK-NEXT: lfs 0, .LCPI4_0@toc@l(3)
; CHECK-NEXT: lfsx 2, 0, 3 ; CHECK-NEXT: addis 3, 2, .LCPI4_1@toc@ha
; CHECK-NEXT: lfs 2, 0(3)
; CHECK-NEXT: lfs 3, .LCPI4_1@toc@l(3)
; CHECK-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI4_2@toc@ha
; CHECK-NEXT: lfs 3, .LCPI4_1@toc@l(4)
; CHECK-NEXT: lfs 1, .LCPI4_2@toc@l(3) ; CHECK-NEXT: lfs 1, .LCPI4_2@toc@l(3)
; CHECK-NEXT: fmr 4, 3 ; CHECK-NEXT: fmr 4, 3
; CHECK-NEXT: xsmaddasp 3, 2, 0 ; CHECK-NEXT: xsmaddasp 3, 2, 0
; CHECK-NEXT: xsnmaddasp 4, 2, 0 ; CHECK-NEXT: xsnmaddasp 4, 2, 0
; CHECK-NEXT: xsmaddasp 1, 2, 3 ; CHECK-NEXT: xsmaddasp 1, 2, 3
; CHECK-NEXT: xsmaddasp 1, 4, 2 ; CHECK-NEXT: xsmaddasp 1, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%tmp = load float, float* undef, align 4 %tmp = load float, float* undef, align 4
Show All 11 Lines; CHECK-NEXT: blr
ret float %tmp12 ret float %tmp12
} }
; This would crash while trying getNegatedExpression(). ; This would crash while trying getNegatedExpression().
define dso_local double @getNegatedExpression_crash(double %x, double %y) { define dso_local double @getNegatedExpression_crash(double %x, double %y) {
; CHECK-FAST-LABEL: getNegatedExpression_crash: ; CHECK-FAST-LABEL: getNegatedExpression_crash:
; CHECK-FAST: # %bb.0: ; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_1@toc@ha ; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_1@toc@ha
; CHECK-FAST-NEXT: addis 4, 2, .LCPI5_0@toc@ha
; CHECK-FAST-NEXT: lfs 3, .LCPI5_1@toc@l(3) ; CHECK-FAST-NEXT: lfs 3, .LCPI5_1@toc@l(3)
; CHECK-FAST-NEXT: lfs 4, .LCPI5_0@toc@l(4) ; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-FAST-NEXT: lfs 4, .LCPI5_0@toc@l(3)
; CHECK-FAST-NEXT: xssubdp 0, 1, 3 ; CHECK-FAST-NEXT: xssubdp 0, 1, 3
; CHECK-FAST-NEXT: xsmaddadp 3, 1, 4 ; CHECK-FAST-NEXT: xsmaddadp 3, 1, 4
; CHECK-FAST-NEXT: xsmaddadp 0, 3, 2 ; CHECK-FAST-NEXT: xsmaddadp 0, 3, 2
; CHECK-FAST-NEXT: fmr 1, 0 ; CHECK-FAST-NEXT: fmr 1, 0
; CHECK-FAST-NEXT: blr ; CHECK-FAST-NEXT: blr
; ;
; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash: ; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash:
; CHECK-FAST-NOVSX: # %bb.0: ; CHECK-FAST-NOVSX: # %bb.0:
; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-FAST-NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-FAST-NOVSX-NEXT: addis 4, 2, .LCPI5_1@toc@ha ; CHECK-FAST-NOVSX-NEXT: addis 4, 2, .LCPI5_1@toc@ha
; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI5_0@toc@l(3) ; CHECK-FAST-NOVSX-NEXT: lfs 0, .LCPI5_0@toc@l(3)
; CHECK-FAST-NOVSX-NEXT: lfs 3, .LCPI5_1@toc@l(4) ; CHECK-FAST-NOVSX-NEXT: lfs 3, .LCPI5_1@toc@l(4)
; CHECK-FAST-NOVSX-NEXT: fmadd 3, 1, 3, 0 ; CHECK-FAST-NOVSX-NEXT: fmadd 3, 1, 3, 0
; CHECK-FAST-NOVSX-NEXT: fsub 0, 1, 0 ; CHECK-FAST-NOVSX-NEXT: fsub 0, 1, 0
; CHECK-FAST-NOVSX-NEXT: fmadd 1, 3, 2, 0 ; CHECK-FAST-NOVSX-NEXT: fmadd 1, 3, 2, 0
; CHECK-FAST-NOVSX-NEXT: blr ; CHECK-FAST-NOVSX-NEXT: blr
; ;
; CHECK-LABEL: getNegatedExpression_crash: ; CHECK-LABEL: getNegatedExpression_crash:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI5_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI5_1@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI5_0@toc@ha
; CHECK-NEXT: lfs 3, .LCPI5_1@toc@l(3) ; CHECK-NEXT: lfs 3, .LCPI5_1@toc@l(3)
; CHECK-NEXT: lfs 4, .LCPI5_0@toc@l(4) ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-NEXT: lfs 4, .LCPI5_0@toc@l(3)
; CHECK-NEXT: xssubdp 0, 1, 3 ; CHECK-NEXT: xssubdp 0, 1, 3
; CHECK-NEXT: xsmaddadp 3, 1, 4 ; CHECK-NEXT: xsmaddadp 3, 1, 4
; CHECK-NEXT: xsmaddadp 0, 3, 2 ; CHECK-NEXT: xsmaddadp 0, 3, 2
; CHECK-NEXT: fmr 1, 0 ; CHECK-NEXT: fmr 1, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%neg = fneg reassoc double %x %neg = fneg reassoc double %x
%fma = call reassoc nsz double @llvm.fma.f64(double %neg, double 42.0, double -1.0) %fma = call reassoc nsz double @llvm.fma.f64(double %neg, double 42.0, double -1.0)
%add = fadd reassoc nsz double %x, 1.0 %add = fadd reassoc nsz double %x, 1.0
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llvm/test/CodeGen/PowerPC/fmf-propagation.ll

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines
; FMF-NEXT: addis 3, 2, .LCPI10_2@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI10_2@toc@ha
; FMF-NEXT: lfs 2, .LCPI10_2@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI10_2@toc@l(3)
; FMF-NEXT: fcmpu 0, 0, 2 ; FMF-NEXT: fcmpu 0, 0, 2
; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: xxlxor 0, 0, 0
; FMF-NEXT: blt 0, .LBB10_2 ; FMF-NEXT: blt 0, .LBB10_2
; FMF-NEXT: # %bb.1: ; FMF-NEXT: # %bb.1:
; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: xsrsqrtesp 0, 1
; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha
; FMF-NEXT: addis 4, 2, .LCPI10_1@toc@ha
; FMF-NEXT: lfs 2, .LCPI10_0@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI10_0@toc@l(3)
; FMF-NEXT: lfs 3, .LCPI10_1@toc@l(4) ; FMF-NEXT: addis 3, 2, .LCPI10_1@toc@ha
; FMF-NEXT: lfs 3, .LCPI10_1@toc@l(3)
; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 0
; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0
; FMF-NEXT: xsmulsp 1, 1, 2 ; FMF-NEXT: xsmulsp 1, 1, 2
; FMF-NEXT: xsaddsp 0, 0, 3 ; FMF-NEXT: xsaddsp 0, 0, 3
; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0
; FMF-NEXT: .LBB10_2: ; FMF-NEXT: .LBB10_2:
; FMF-NEXT: fmr 1, 0 ; FMF-NEXT: fmr 1, 0
; FMF-NEXT: blr ; FMF-NEXT: blr
; ;
; GLOBAL-LABEL: sqrt_afn_ieee: ; GLOBAL-LABEL: sqrt_afn_ieee:
; GLOBAL: # %bb.0: ; GLOBAL: # %bb.0:
; GLOBAL-NEXT: xsabsdp 0, 1 ; GLOBAL-NEXT: xsabsdp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI10_2@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI10_2@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI10_2@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI10_2@toc@l(3)
; GLOBAL-NEXT: fcmpu 0, 0, 2 ; GLOBAL-NEXT: fcmpu 0, 0, 2
; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: xxlxor 0, 0, 0
; GLOBAL-NEXT: blt 0, .LBB10_2 ; GLOBAL-NEXT: blt 0, .LBB10_2
; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: xsrsqrtesp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha
; GLOBAL-NEXT: addis 4, 2, .LCPI10_1@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI10_0@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI10_0@toc@l(3)
; GLOBAL-NEXT: lfs 3, .LCPI10_1@toc@l(4) ; GLOBAL-NEXT: addis 3, 2, .LCPI10_1@toc@ha
; GLOBAL-NEXT: lfs 3, .LCPI10_1@toc@l(3)
; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmulsp 1, 1, 0
; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0
; GLOBAL-NEXT: xsmulsp 0, 1, 3 ; GLOBAL-NEXT: xsmulsp 0, 1, 3
; GLOBAL-NEXT: xsmulsp 0, 0, 2 ; GLOBAL-NEXT: xsmulsp 0, 0, 2
; GLOBAL-NEXT: .LBB10_2: ; GLOBAL-NEXT: .LBB10_2:
; GLOBAL-NEXT: fmr 1, 0 ; GLOBAL-NEXT: fmr 1, 0
; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%rt = call afn ninf float @llvm.sqrt.f32(float %x) %rt = call afn ninf float @llvm.sqrt.f32(float %x)
Show All 26 Lines
; FMF-LABEL: sqrt_afn_preserve_sign: ; FMF-LABEL: sqrt_afn_preserve_sign:
; FMF: # %bb.0: ; FMF: # %bb.0:
; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: xxlxor 0, 0, 0
; FMF-NEXT: fcmpu 0, 1, 0 ; FMF-NEXT: fcmpu 0, 1, 0
; FMF-NEXT: beq 0, .LBB12_2 ; FMF-NEXT: beq 0, .LBB12_2
; FMF-NEXT: # %bb.1: ; FMF-NEXT: # %bb.1:
; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: xsrsqrtesp 0, 1
; FMF-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; FMF-NEXT: addis 4, 2, .LCPI12_1@toc@ha
; FMF-NEXT: lfs 2, .LCPI12_0@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI12_0@toc@l(3)
; FMF-NEXT: lfs 3, .LCPI12_1@toc@l(4) ; FMF-NEXT: addis 3, 2, .LCPI12_1@toc@ha
; FMF-NEXT: lfs 3, .LCPI12_1@toc@l(3)
; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 0
; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0
; FMF-NEXT: xsmulsp 1, 1, 2 ; FMF-NEXT: xsmulsp 1, 1, 2
; FMF-NEXT: xsaddsp 0, 0, 3 ; FMF-NEXT: xsaddsp 0, 0, 3
; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0
; FMF-NEXT: .LBB12_2: ; FMF-NEXT: .LBB12_2:
; FMF-NEXT: fmr 1, 0 ; FMF-NEXT: fmr 1, 0
; FMF-NEXT: blr ; FMF-NEXT: blr
; ;
; GLOBAL-LABEL: sqrt_afn_preserve_sign: ; GLOBAL-LABEL: sqrt_afn_preserve_sign:
; GLOBAL: # %bb.0: ; GLOBAL: # %bb.0:
; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: xxlxor 0, 0, 0
; GLOBAL-NEXT: fcmpu 0, 1, 0 ; GLOBAL-NEXT: fcmpu 0, 1, 0
; GLOBAL-NEXT: beq 0, .LBB12_2 ; GLOBAL-NEXT: beq 0, .LBB12_2
; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: xsrsqrtesp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; GLOBAL-NEXT: addis 4, 2, .LCPI12_1@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI12_0@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI12_0@toc@l(3)
; GLOBAL-NEXT: lfs 3, .LCPI12_1@toc@l(4) ; GLOBAL-NEXT: addis 3, 2, .LCPI12_1@toc@ha
; GLOBAL-NEXT: lfs 3, .LCPI12_1@toc@l(3)
; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmulsp 1, 1, 0
; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0
; GLOBAL-NEXT: xsmulsp 0, 1, 3 ; GLOBAL-NEXT: xsmulsp 0, 1, 3
; GLOBAL-NEXT: xsmulsp 0, 0, 2 ; GLOBAL-NEXT: xsmulsp 0, 0, 2
; GLOBAL-NEXT: .LBB12_2: ; GLOBAL-NEXT: .LBB12_2:
; GLOBAL-NEXT: fmr 1, 0 ; GLOBAL-NEXT: fmr 1, 0
; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%rt = call afn ninf float @llvm.sqrt.f32(float %x) %rt = call afn ninf float @llvm.sqrt.f32(float %x)
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; FMF-NEXT: addis 3, 2, .LCPI14_2@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI14_2@toc@ha
; FMF-NEXT: lfs 2, .LCPI14_2@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI14_2@toc@l(3)
; FMF-NEXT: fcmpu 0, 0, 2 ; FMF-NEXT: fcmpu 0, 0, 2
; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: xxlxor 0, 0, 0
; FMF-NEXT: blt 0, .LBB14_2 ; FMF-NEXT: blt 0, .LBB14_2
; FMF-NEXT: # %bb.1: ; FMF-NEXT: # %bb.1:
; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: xsrsqrtesp 0, 1
; FMF-NEXT: addis 3, 2, .LCPI14_0@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI14_0@toc@ha
; FMF-NEXT: addis 4, 2, .LCPI14_1@toc@ha
; FMF-NEXT: lfs 2, .LCPI14_0@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI14_0@toc@l(3)
; FMF-NEXT: lfs 3, .LCPI14_1@toc@l(4) ; FMF-NEXT: addis 3, 2, .LCPI14_1@toc@ha
; FMF-NEXT: lfs 3, .LCPI14_1@toc@l(3)
; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 0
; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0
; FMF-NEXT: xsmulsp 0, 1, 3 ; FMF-NEXT: xsmulsp 0, 1, 3
; FMF-NEXT: xsmulsp 0, 0, 2 ; FMF-NEXT: xsmulsp 0, 0, 2
; FMF-NEXT: .LBB14_2: ; FMF-NEXT: .LBB14_2:
; FMF-NEXT: fmr 1, 0 ; FMF-NEXT: fmr 1, 0
; FMF-NEXT: blr ; FMF-NEXT: blr
; ;
; GLOBAL-LABEL: sqrt_fast_ieee: ; GLOBAL-LABEL: sqrt_fast_ieee:
; GLOBAL: # %bb.0: ; GLOBAL: # %bb.0:
; GLOBAL-NEXT: xsabsdp 0, 1 ; GLOBAL-NEXT: xsabsdp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI14_2@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI14_2@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI14_2@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI14_2@toc@l(3)
; GLOBAL-NEXT: fcmpu 0, 0, 2 ; GLOBAL-NEXT: fcmpu 0, 0, 2
; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: xxlxor 0, 0, 0
; GLOBAL-NEXT: blt 0, .LBB14_2 ; GLOBAL-NEXT: blt 0, .LBB14_2
; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: xsrsqrtesp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI14_0@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI14_0@toc@ha
; GLOBAL-NEXT: addis 4, 2, .LCPI14_1@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI14_0@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI14_0@toc@l(3)
; GLOBAL-NEXT: lfs 3, .LCPI14_1@toc@l(4) ; GLOBAL-NEXT: addis 3, 2, .LCPI14_1@toc@ha
; GLOBAL-NEXT: lfs 3, .LCPI14_1@toc@l(3)
; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmulsp 1, 1, 0
; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0
; GLOBAL-NEXT: xsmulsp 0, 1, 3 ; GLOBAL-NEXT: xsmulsp 0, 1, 3
; GLOBAL-NEXT: xsmulsp 0, 0, 2 ; GLOBAL-NEXT: xsmulsp 0, 0, 2
; GLOBAL-NEXT: .LBB14_2: ; GLOBAL-NEXT: .LBB14_2:
; GLOBAL-NEXT: fmr 1, 0 ; GLOBAL-NEXT: fmr 1, 0
; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%rt = call reassoc afn ninf float @llvm.sqrt.f32(float %x) %rt = call reassoc afn ninf float @llvm.sqrt.f32(float %x)
Show All 14 Lines
; FMF-LABEL: sqrt_fast_preserve_sign: ; FMF-LABEL: sqrt_fast_preserve_sign:
; FMF: # %bb.0: ; FMF: # %bb.0:
; FMF-NEXT: xxlxor 0, 0, 0 ; FMF-NEXT: xxlxor 0, 0, 0
; FMF-NEXT: fcmpu 0, 1, 0 ; FMF-NEXT: fcmpu 0, 1, 0
; FMF-NEXT: beq 0, .LBB15_2 ; FMF-NEXT: beq 0, .LBB15_2
; FMF-NEXT: # %bb.1: ; FMF-NEXT: # %bb.1:
; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: xsrsqrtesp 0, 1
; FMF-NEXT: addis 3, 2, .LCPI15_0@toc@ha ; FMF-NEXT: addis 3, 2, .LCPI15_0@toc@ha
; FMF-NEXT: addis 4, 2, .LCPI15_1@toc@ha
; FMF-NEXT: lfs 2, .LCPI15_0@toc@l(3) ; FMF-NEXT: lfs 2, .LCPI15_0@toc@l(3)
; FMF-NEXT: lfs 3, .LCPI15_1@toc@l(4) ; FMF-NEXT: addis 3, 2, .LCPI15_1@toc@ha
; FMF-NEXT: lfs 3, .LCPI15_1@toc@l(3)
; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 0
; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0
; FMF-NEXT: xsmulsp 0, 1, 3 ; FMF-NEXT: xsmulsp 0, 1, 3
; FMF-NEXT: xsmulsp 0, 0, 2 ; FMF-NEXT: xsmulsp 0, 0, 2
; FMF-NEXT: .LBB15_2: ; FMF-NEXT: .LBB15_2:
; FMF-NEXT: fmr 1, 0 ; FMF-NEXT: fmr 1, 0
; FMF-NEXT: blr ; FMF-NEXT: blr
; ;
; GLOBAL-LABEL: sqrt_fast_preserve_sign: ; GLOBAL-LABEL: sqrt_fast_preserve_sign:
; GLOBAL: # %bb.0: ; GLOBAL: # %bb.0:
; GLOBAL-NEXT: xxlxor 0, 0, 0 ; GLOBAL-NEXT: xxlxor 0, 0, 0
; GLOBAL-NEXT: fcmpu 0, 1, 0 ; GLOBAL-NEXT: fcmpu 0, 1, 0
; GLOBAL-NEXT: beq 0, .LBB15_2 ; GLOBAL-NEXT: beq 0, .LBB15_2
; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: # %bb.1:
; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: xsrsqrtesp 0, 1
; GLOBAL-NEXT: addis 3, 2, .LCPI15_0@toc@ha ; GLOBAL-NEXT: addis 3, 2, .LCPI15_0@toc@ha
; GLOBAL-NEXT: addis 4, 2, .LCPI15_1@toc@ha
; GLOBAL-NEXT: lfs 2, .LCPI15_0@toc@l(3) ; GLOBAL-NEXT: lfs 2, .LCPI15_0@toc@l(3)
; GLOBAL-NEXT: lfs 3, .LCPI15_1@toc@l(4) ; GLOBAL-NEXT: addis 3, 2, .LCPI15_1@toc@ha
; GLOBAL-NEXT: lfs 3, .LCPI15_1@toc@l(3)
; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmulsp 1, 1, 0
; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0
; GLOBAL-NEXT: xsmulsp 0, 1, 3 ; GLOBAL-NEXT: xsmulsp 0, 1, 3
; GLOBAL-NEXT: xsmulsp 0, 0, 2 ; GLOBAL-NEXT: xsmulsp 0, 0, 2
; GLOBAL-NEXT: .LBB15_2: ; GLOBAL-NEXT: .LBB15_2:
; GLOBAL-NEXT: fmr 1, 0 ; GLOBAL-NEXT: fmr 1, 0
; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%rt = call reassoc ninf afn float @llvm.sqrt.f32(float %x) %rt = call reassoc ninf afn float @llvm.sqrt.f32(float %x)
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llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

Show First 20 Lines • Show All 611 Lines • ▼ Show 20 Lines
; P8-NEXT: stdu r1, -128(r1) ; P8-NEXT: stdu r1, -128(r1)
; P8-NEXT: .cfi_def_cfa_offset 128 ; P8-NEXT: .cfi_def_cfa_offset 128
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: .cfi_offset r30, -16 ; P8-NEXT: .cfi_offset r30, -16
; P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: xxlxor f3, f3, f3
; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3) ; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3)
; P8-NEXT: fcmpo cr0, f2, f3
; P8-NEXT: lis r3, -32768 ; P8-NEXT: lis r3, -32768
; P8-NEXT: fcmpo cr0, f2, f3
; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: xxlxor f3, f3, f3
; P8-NEXT: fcmpo cr1, f1, f0 ; P8-NEXT: fcmpo cr1, f1, f0
; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt ; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt
; P8-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq ; P8-NEXT: crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
; P8-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt ; P8-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P8-NEXT: isel r30, 0, r3, 4*cr5+lt ; P8-NEXT: isel r30, 0, r3, 4*cr5+lt
; P8-NEXT: bc 12, 4*cr5+lt, .LBB13_2 ; P8-NEXT: bc 12, 4*cr5+lt, .LBB13_2
; P8-NEXT: # %bb.1: # %entry ; P8-NEXT: # %bb.1: # %entry
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llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

Show All 39 Lines
} }
define i128 @test_neg(ppc_fp128 %x) nounwind { define i128 @test_neg(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_neg: ; PPC64-LABEL: test_neg:
; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]]) ; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]])
; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]]) ; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]])
; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1 ; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
; PPC64-DAG: rldic [[FLIP_BIT]], [[FLIP_BIT]], 63, 0 ; PPC64-DAG: rldic [[RES:[0-9]+]], [[FLIP_BIT]], 63, 0
; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
; PPC64-NOT: BARRIER ; PPC64-NOT: BARRIER
; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] ; PPC64-DAG: xor 3, [[HI]], [[RES]]
; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] ; PPC64-DAG: xor 4, [[LO]], [[RES]]
; PPC64: blr ; PPC64: blr
; PPC64-P8-LABEL: test_neg: ; PPC64-P8-LABEL: test_neg:
; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2 ; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1 ; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
; PPC64-P8-DAG: rldic [[FLIP_BIT:[0-9]+]], [[IMM1]], 63, 0 ; PPC64-P8-DAG: rldic [[FLIP_BIT:[0-9]+]], [[IMM1]], 63, 0
; PPC64-P8-NOT: BARRIER ; PPC64-P8-NOT: BARRIER
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llvm/test/CodeGen/PowerPC/instr-properties.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -stop-after=machine-scheduler -o - | FileCheck %s --check-prefix=CHECK-P8 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-misched -stop-after=machine-scheduler -o - | FileCheck %s --check-prefix=CHECK-P8
; Verify XFLOADf64 didn't implict def 'rm'. ; Verify XFLOADf64 didn't implict def 'rm'.
define double @rm() { define double @rm() {
; CHECK-P8-LABEL: bb.0.entry ; CHECK-P8-LABEL: bb.0.entry
; CHECK-P8: %{{[0-9]+}}:vsfrc = XFLOADf64 $zero8, %{{[0-9]+}} :: ; CHECK-P8: %{{[0-9]+}}:f8rc = LFD target-flags(ppc-toc-lo) %const.0, %{{[0-9]+}}, implicit $x2 ::
entry: entry:
ret double 2.300000e+00 ret double 2.300000e+00
} }

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap10: ; CHECK-P9-BE-LABEL: load_swap10:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x i32>, <4 x i32>* %vp1 %v1 = load <4 x i32>, <4 x i32>* %vp1
%v2 = load <4 x i32>, <4 x i32>* %vp2 %v2 = load <4 x i32>, <4 x i32>* %vp2
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i32> %v3 ret <4 x i32> %v3
} }
Show All 21 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap11: ; CHECK-P9-BE-LABEL: load_swap11:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x i32>, <4 x i32>* %vp1 %v1 = load <4 x i32>, <4 x i32>* %vp1
%v2 = load <4 x i32>, <4 x i32>* %vp2 %v2 = load <4 x i32>, <4 x i32>* %vp2
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
ret <4 x i32> %v3 ret <4 x i32> %v3
} }
Show All 21 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap20: ; CHECK-P9-BE-LABEL: load_swap20:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <8 x i16>, <8 x i16>* %vp1 %v1 = load <8 x i16>, <8 x i16>* %vp1
%v2 = load <8 x i16>, <8 x i16>* %vp2 %v2 = load <8 x i16>, <8 x i16>* %vp2
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %v3 ret <8 x i16> %v3
} }
Show All 21 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap21: ; CHECK-P9-BE-LABEL: load_swap21:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <8 x i16>, <8 x i16>* %vp1 %v1 = load <8 x i16>, <8 x i16>* %vp1
%v2 = load <8 x i16>, <8 x i16>* %vp2 %v2 = load <8 x i16>, <8 x i16>* %vp2
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <8 x i16> %v3 ret <8 x i16> %v3
} }
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; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap50: ; CHECK-P9-BE-LABEL: load_swap50:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x float>, <4 x float>* %vp1 %v1 = load <4 x float>, <4 x float>* %vp1
%v2 = load <4 x float>, <4 x float>* %vp2 %v2 = load <4 x float>, <4 x float>* %vp2
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %v3 ret <4 x float> %v3
} }
Show All 21 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: load_swap51: ; CHECK-P9-BE-LABEL: load_swap51:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha
; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: lxv v2, 0(r4)
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v1 = load <4 x float>, <4 x float>* %vp1 %v1 = load <4 x float>, <4 x float>* %vp1
%v2 = load <4 x float>, <4 x float>* %vp2 %v2 = load <4 x float>, <4 x float>* %vp2
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
ret <4 x float> %v3 ret <4 x float> %v3
} }
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; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store10: ; CHECK-P9-BE-LABEL: swap_store10:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
store <4 x i32> %v3, <4 x i32>* %vp store <4 x i32> %v3, <4 x i32>* %vp
ret void ret void
} }
Show All 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store11: ; CHECK-P9-BE-LABEL: swap_store11:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
store <4 x i32> %v3, <4 x i32>* %vp store <4 x i32> %v3, <4 x i32>* %vp
ret void ret void
} }
Show All 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store20: ; CHECK-P9-BE-LABEL: swap_store20:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
store <8 x i16> %v3, <8 x i16>* %vp store <8 x i16> %v3, <8 x i16>* %vp
ret void ret void
} }
Show All 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store21: ; CHECK-P9-BE-LABEL: swap_store21:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
store <8 x i16> %v3, <8 x i16>* %vp store <8 x i16> %v3, <8 x i16>* %vp
ret void ret void
} }
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store50: ; CHECK-P9-BE-LABEL: swap_store50:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 ; CHECK-P9-BE-NEXT: lxv v3, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
store <4 x float> %v3, <4 x float>* %vp store <4 x float> %v3, <4 x float>* %vp
ret void ret void
} }
Show All 20 Lines
; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r7
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
; ;
; CHECK-P9-BE-LABEL: swap_store51: ; CHECK-P9-BE-LABEL: swap_store51:
; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE: # %bb.0:
; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha
; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l
; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 ; CHECK-P9-BE-NEXT: lxv v2, 0(r3)
; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2
; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: stxv v2, 0(r7)
; CHECK-P9-BE-NEXT: blr ; CHECK-P9-BE-NEXT: blr
%v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4> %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
store <4 x float> %v3, <4 x float>* %vp store <4 x float> %v3, <4 x float>* %vp
ret void ret void
} }

llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll

; RUN: llc -O3 -ppc-late-peephole=false -o - %s | FileCheck %s ; RUN: llc -O3 -ppc-late-peephole=false -ppc-convert-rr-to-ri=false -o - %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%class1 = type { %union1 } %class1 = type { %union1 }
%union1 = type { i64, [24 x i8] } %union1 = type { i64, [24 x i8] }
%class2 = type { %class3 } %class2 = type { %class3 }
%class3 = type { %class4 } %class3 = type { %class4 }
%class4 = type { %class5, i64, %union.anon } %class4 = type { %class5, i64, %union.anon }
Show All 37 Lines

llvm/test/CodeGen/PowerPC/mcm-4.ll

Show All 27 Lines
; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0 ; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0
; MEDIUM-VSX-LABEL: test_double_const: ; MEDIUM-VSX-LABEL: test_double_const:
; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; MEDIUM-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})
; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE: .quad 0x3f4fd4920b498cf0 ; LARGE: .quad 0x3f4fd4920b498cf0
; LARGE-LABEL: test_double_const: ; LARGE-LABEL: test_double_const:
; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE-VSX: .quad 0x3f4fd4920b498cf0 ; LARGE-VSX: .quad 0x3f4fd4920b498cf0
; LARGE-VSX-LABEL: test_double_const: ; LARGE-VSX-LABEL: test_double_const:
; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] ; LARGE-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})
; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
; MEDIUM-P9: .quad 0x3f4fd4920b498cf0 ; MEDIUM-P9: .quad 0x3f4fd4920b498cf0
; MEDIUM-P9-LABEL: test_double_const: ; MEDIUM-P9-LABEL: test_double_const:
; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])
; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:
; LARGE-P9: .quad 0x3f4fd4920b498cf0 ; LARGE-P9: .quad 0x3f4fd4920b498cf0
; LARGE-P9-LABEL: test_double_const: ; LARGE-P9-LABEL: test_double_const:
; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])

llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-NEXT: li r3, 96 ; CHECK-NEXT: li r3, 96
; CHECK-NEXT: lxvp vsp36, r1(r3) # 32-byte Folded Reload ; CHECK-NEXT: lxvp vsp36, r1(r3) # 32-byte Folded Reload
; CHECK-NEXT: xxmtacc acc0 ; CHECK-NEXT: xxmtacc acc0
; CHECK-NEXT: xvf16ger2pp acc0, v2, v4 ; CHECK-NEXT: xvf16ger2pp acc0, v2, v4
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r30) ; CHECK-NEXT: stxv vs0, 48(r30)
; CHECK-NEXT: stxv vs1, 32(r30) ; CHECK-NEXT: stxv vs1, 32(r30)
; CHECK-NEXT: stxv vs2, 16(r30) ; CHECK-NEXT: stxv vs2, 16(r30)
; CHECK-NEXT: stxvx vs3, 0, r30 ; CHECK-NEXT: stxv vs3, 0(r30)
; CHECK-NEXT: addi r1, r1, 176 ; CHECK-NEXT: addi r1, r1, 176
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: intrinsics1: ; CHECK-BE-LABEL: intrinsics1:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
Show All 33 Lines
; CHECK-BE-NEXT: li r3, 208 ; CHECK-BE-NEXT: li r3, 208
; CHECK-BE-NEXT: lxvp vsp34, r1(r3) # 32-byte Folded Reload ; CHECK-BE-NEXT: lxvp vsp34, r1(r3) # 32-byte Folded Reload
; CHECK-BE-NEXT: li r3, 176 ; CHECK-BE-NEXT: li r3, 176
; CHECK-BE-NEXT: lxvp vsp36, r1(r3) # 32-byte Folded Reload ; CHECK-BE-NEXT: lxvp vsp36, r1(r3) # 32-byte Folded Reload
; CHECK-BE-NEXT: xxmtacc acc0 ; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4 ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r30) ; CHECK-BE-NEXT: stxv vs1, 16(r30)
; CHECK-BE-NEXT: stxvx vs0, 0, r30 ; CHECK-BE-NEXT: stxv vs0, 0(r30)
; CHECK-BE-NEXT: stxv vs3, 48(r30) ; CHECK-BE-NEXT: stxv vs3, 48(r30)
; CHECK-BE-NEXT: stxv vs2, 32(r30) ; CHECK-BE-NEXT: stxv vs2, 32(r30)
; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload ; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload
; CHECK-BE-NEXT: addi r1, r1, 256 ; CHECK-BE-NEXT: addi r1, r1, 256
; CHECK-BE-NEXT: ld r0, 16(r1) ; CHECK-BE-NEXT: ld r0, 16(r1)
; CHECK-BE-NEXT: mtlr r0 ; CHECK-BE-NEXT: mtlr r0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4) %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3) %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
tail call void @foo() tail call void @foo()
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = bitcast i8* %ptr to <512 x i1>* %4 = bitcast i8* %ptr to <512 x i1>*
store <512 x i1> %3, <512 x i1>* %4, align 64 store <512 x i1> %3, <512 x i1>* %4, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

Show All 25 Lines
; CHECK-NEXT: xvi4ger8pp acc0, v2, v3 ; CHECK-NEXT: xvi4ger8pp acc0, v2, v3
; CHECK-NEXT: xvf16ger2pp acc0, v2, v1 ; CHECK-NEXT: xvf16ger2pp acc0, v2, v1
; CHECK-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0 ; CHECK-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
; CHECK-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0 ; CHECK-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0
; CHECK-NEXT: xxmfacc acc0 ; CHECK-NEXT: xxmfacc acc0
; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs0, 48(r3)
; CHECK-NEXT: stxv vs1, 32(r3) ; CHECK-NEXT: stxv vs1, 32(r3)
; CHECK-NEXT: stxv vs2, 16(r3) ; CHECK-NEXT: stxv vs2, 16(r3)
; CHECK-NEXT: stxvx vs3, 0, r3 ; CHECK-NEXT: stxv vs3, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: intrinsics1: ; CHECK-BE-LABEL: intrinsics1:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18 ; CHECK-BE-NEXT: # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
; CHECK-BE-NEXT: vmr v1, v4 ; CHECK-BE-NEXT: vmr v1, v4
; CHECK-BE-NEXT: vmr v4, v3 ; CHECK-BE-NEXT: vmr v4, v3
; CHECK-BE-NEXT: ld r3, 112(r1) ; CHECK-BE-NEXT: ld r3, 112(r1)
; CHECK-BE-NEXT: vmr v0, v2 ; CHECK-BE-NEXT: vmr v0, v2
; CHECK-BE-NEXT: xxlor vs5, v2, v2 ; CHECK-BE-NEXT: xxlor vs5, v2, v2
; CHECK-BE-NEXT: xxlor vs4, v5, v5 ; CHECK-BE-NEXT: xxlor vs4, v5, v5
; CHECK-BE-NEXT: xxlor vs0, v0, v0 ; CHECK-BE-NEXT: xxlor vs0, v0, v0
; CHECK-BE-NEXT: xxlor vs1, v1, v1 ; CHECK-BE-NEXT: xxlor vs1, v1, v1
; CHECK-BE-NEXT: xxlor vs2, v4, v4 ; CHECK-BE-NEXT: xxlor vs2, v4, v4
; CHECK-BE-NEXT: xxlor vs3, v5, v5 ; CHECK-BE-NEXT: xxlor vs3, v5, v5
; CHECK-BE-NEXT: xxmtacc acc0 ; CHECK-BE-NEXT: xxmtacc acc0
; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v3 ; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v3
; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v1 ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v1
; CHECK-BE-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0 ; CHECK-BE-NEXT: pmxvf32gerpn acc0, v3, v5, 0, 0
; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0 ; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0
; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: xxmfacc acc0
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: stxvx vs0, 0, r3 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4) %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2) %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3) %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0) %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
%5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1) %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
▲ Show 20 Lines • Show All 1,757 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/mul-const-vector.ll

Show First 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
define <2 x i64> @test1_v2i64(<2 x i64> %a) { define <2 x i64> @test1_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test1_v2i64: ; CHECK-LABEL: test1_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]] ; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]
define <2 x i64> @test2_v2i64(<2 x i64> %a) { define <2 x i64> @test2_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test2_v2i64: ; CHECK-LABEL: test2_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]] ; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]]
define <2 x i64> @test3_v2i64(<2 x i64> %a) { define <2 x i64> @test3_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test3_v2i64: ; CHECK-LABEL: test3_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
; negtive constant ; negtive constant
define <2 x i64> @test4_v2i64(<2 x i64> %a) { define <2 x i64> @test4_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test4_v2i64: ; CHECK-LABEL: test4_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]], ; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]] ; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]] ; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]
define <2 x i64> @test5_v2i64(<2 x i64> %a) { define <2 x i64> @test5_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test5_v2i64: ; CHECK-LABEL: test5_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]] ; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]]
; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]], ; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]],
; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]] ; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]]
; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]] ; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]
define <2 x i64> @test6_v2i64(<2 x i64> %a) { define <2 x i64> @test6_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test6_v2i64: ; CHECK-LABEL: test6_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]]
; boundary case ; boundary case
define <2 x i64> @test7_v2i64(<2 x i64> %a) { define <2 x i64> @test7_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test7_v2i64: ; CHECK-LABEL: test7_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
define <2 x i64> @test8_v2i64(<2 x i64> %a) { define <2 x i64> @test8_v2i64(<2 x i64> %a) {
%tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1] %tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp.1 ret <2 x i64> %tmp.1
} }
; CHECK-LABEL: test8_v2i64: ; CHECK-LABEL: test8_v2i64:
; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}}
; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]]
; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}})
; CHECK-NOT: vmul ; CHECK-NOT: vmul
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2

llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local void @test(float* nocapture readonly %Fptr, <4 x float>* nocapture %Vptr) local_unnamed_addr #0 !dbg !10 { define dso_local void @test(float* nocapture readonly %Fptr, <4 x float>* nocapture %Vptr) local_unnamed_addr #0 !dbg !10 {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3 ; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3
; CHECK-NEXT: #DEBUG_VALUE: test:Vptr <- $x4 ; CHECK-NEXT: #DEBUG_VALUE: test:Vptr <- $x4
; CHECK-NEXT: addis 5, 2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis 5, 2, .LCPI0_0@toc@ha
; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: .loc 1 2 38 prologue_end ; CHECK-NEXT: .loc 1 2 38 prologue_end
; CHECK-NEXT: lfsx 0, 0, 3 ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3
; CHECK-NEXT: .loc 1 0 38 is_stmt 0 ; CHECK-NEXT: .loc 1 0 38 is_stmt 0
; CHECK-NEXT: lfs 1, .LCPI0_0@toc@l(5) ; CHECK-NEXT: lfs 1, .LCPI0_0@toc@l(5)
; CHECK-NEXT: lfd 2, .LCPI0_1@toc@l(3) ; CHECK-NEXT: lfd 2, .LCPI0_1@toc@l(3)
; CHECK-NEXT: .loc 1 2 27 ; CHECK-NEXT: .loc 1 2 27
; CHECK-NEXT: xssubdp 1, 1, 0 ; CHECK-NEXT: xssubdp 1, 1, 0
; CHECK-NEXT: .loc 1 2 45 ; CHECK-NEXT: .loc 1 2 45
; CHECK-NEXT: xsadddp 1, 1, 2 ; CHECK-NEXT: xsadddp 1, 1, 2
; CHECK-NEXT: .Ltmp2: ; CHECK-NEXT: .Ltmp2:
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llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll

Show All 31 Lines
; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, 1081435463 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, 1081435463
; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -1374389535 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -1374389535
; CHECK-NOPCREL-LE-NEXT: blr ; CHECK-NOPCREL-LE-NEXT: blr
; ;
; CHECK-NOPREFIX-LABEL: testDoubleToDoubleFail: ; CHECK-NOPREFIX-LABEL: testDoubleToDoubleFail:
; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX: # %bb.0: # %entry
; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3)
; CHECK-NOPREFIX-NEXT: blr ; CHECK-NOPREFIX-NEXT: blr
; ;
; CHECK-BE-LABEL: testDoubleToDoubleFail: ; CHECK-BE-LABEL: testDoubleToDoubleFail:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 1081435463 ; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 1081435463
; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -1374389535 ; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -1374389535
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
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; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, 940259579 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, 940259579
; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -2147483648 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -2147483648
; CHECK-NOPCREL-LE-NEXT: blr ; CHECK-NOPCREL-LE-NEXT: blr
; ;
; CHECK-NOPREFIX-LABEL: testFloatDenormToDouble: ; CHECK-NOPREFIX-LABEL: testFloatDenormToDouble:
; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX: # %bb.0: # %entry
; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3)
; CHECK-NOPREFIX-NEXT: blr ; CHECK-NOPREFIX-NEXT: blr
; ;
; CHECK-BE-LABEL: testFloatDenormToDouble: ; CHECK-BE-LABEL: testFloatDenormToDouble:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 940259579 ; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 940259579
; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -2147483648 ; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -2147483648
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 18 Lines
; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, -1 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 0, -1
; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -16 ; CHECK-NOPCREL-LE-NEXT: xxsplti32dx vs34, 1, -16
; CHECK-NOPCREL-LE-NEXT: blr ; CHECK-NOPCREL-LE-NEXT: blr
; ;
; CHECK-NOPREFIX-LABEL: testDoubleToDoubleNaNFail: ; CHECK-NOPREFIX-LABEL: testDoubleToDoubleNaNFail:
; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX: # %bb.0: # %entry
; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 ; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3)
; CHECK-NOPREFIX-NEXT: blr ; CHECK-NOPREFIX-NEXT: blr
; ;
; CHECK-BE-LABEL: testDoubleToDoubleNaNFail: ; CHECK-BE-LABEL: testDoubleToDoubleNaNFail:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsplti32dx vs34, 0, -1 ; CHECK-BE-NEXT: xxsplti32dx vs34, 0, -1
; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -16 ; CHECK-BE-NEXT: xxsplti32dx vs34, 1, -16
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
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llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll

Show All 28 Lines
; CHECK-LE-NEXT: plxv v3, .LCPI1_0@PCREL(0), 1 ; CHECK-LE-NEXT: plxv v3, .LCPI1_0@PCREL(0), 1
; CHECK-LE-NEXT: vrlq v2, v3, v2 ; CHECK-LE-NEXT: vrlq v2, v3, v2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: test_vrlq_cost_mult8: ; CHECK-BE-LABEL: test_vrlq_cost_mult8:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: vrlq v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%shl.i = shl <1 x i128> <i128 16>, %x %shl.i = shl <1 x i128> <i128 16>, %x
%sub.i = sub <1 x i128> <i128 128>, %x %sub.i = sub <1 x i128> <i128 128>, %x
%lshr.i = lshr <1 x i128> <i128 16>, %sub.i %lshr.i = lshr <1 x i128> <i128 16>, %sub.i
%tmp = or <1 x i128> %shl.i, %lshr.i %tmp = or <1 x i128> %shl.i, %lshr.i
ret <1 x i128> %tmp ret <1 x i128> %tmp
} }
define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) { define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) {
; CHECK-LE-LABEL: test_vrlq_cost_non_mult8: ; CHECK-LE-LABEL: test_vrlq_cost_non_mult8:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: plxv v3, .LCPI2_0@PCREL(0), 1 ; CHECK-LE-NEXT: plxv v3, .LCPI2_0@PCREL(0), 1
; CHECK-LE-NEXT: vrlq v2, v3, v2 ; CHECK-LE-NEXT: vrlq v2, v3, v2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: test_vrlq_cost_non_mult8: ; CHECK-BE-LABEL: test_vrlq_cost_non_mult8:
; CHECK-BE: # %bb.0: ; CHECK-BE: # %bb.0:
; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: vrlq v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
%shl.i = shl <1 x i128> <i128 4>, %x %shl.i = shl <1 x i128> <i128 4>, %x
%sub.i = sub <1 x i128> <i128 128>, %x %sub.i = sub <1 x i128> <i128 128>, %x
%lshr.i = lshr <1 x i128> <i128 4>, %sub.i %lshr.i = lshr <1 x i128> <i128 4>, %sub.i
%tmp = or <1 x i128> %shl.i, %lshr.i %tmp = or <1 x i128> %shl.i, %lshr.i
ret <1 x i128> %tmp ret <1 x i128> %tmp
} }
Show All 18 Lines
; CHECK-LE-NEXT: vperm v3, v4, v3, v5 ; CHECK-LE-NEXT: vperm v3, v4, v3, v5
; CHECK-LE-NEXT: vrlqnm v2, v2, v3 ; CHECK-LE-NEXT: vrlqnm v2, v2, v3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: test_vrlqnm: ; CHECK-BE-LABEL: test_vrlqnm:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v5, 0, r3 ; CHECK-BE-NEXT: lxv v5, 0(r3)
; CHECK-BE-NEXT: vperm v3, v3, v4, v5 ; CHECK-BE-NEXT: vperm v3, v3, v4, v5
; CHECK-BE-NEXT: vrlqnm v2, v2, v3 ; CHECK-BE-NEXT: vrlqnm v2, v2, v3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast <1 x i128> %b to <16 x i8> %0 = bitcast <1 x i128> %b to <16 x i8>
%1 = bitcast <1 x i128> %c to <16 x i8> %1 = bitcast <1 x i128> %c to <16 x i8>
%shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%d = bitcast <16 x i8> %shuffle.i to <1 x i128> %d = bitcast <16 x i8> %shuffle.i to <1 x i128>
Show All 9 Lines

llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll

Show First 20 Lines • Show All 445 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinserth 2, 2, 14 ; CHECK-NEXT: vinserth 2, 2, 14
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_0_4: ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_1_3: ; CHECK-LABEL: shuffle_vector_halfword_1_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_1_3: ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinserth 2, 2, 2 ; CHECK-BE-NEXT: vinserth 2, 2, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_2_3: ; CHECK-LABEL: shuffle_vector_halfword_2_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_2_3: ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinserth 2, 2, 4 ; CHECK-BE-NEXT: vinserth 2, 2, 4
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_3_4: ; CHECK-LABEL: shuffle_vector_halfword_3_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinserth 2, 2, 8 ; CHECK-NEXT: vinserth 2, 2, 8
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_3_4: ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_4_3: ; CHECK-LABEL: shuffle_vector_halfword_4_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_4_3: ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinserth 2, 2, 8 ; CHECK-BE-NEXT: vinserth 2, 2, 8
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_5_3: ; CHECK-LABEL: shuffle_vector_halfword_5_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_5_3: ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinserth 2, 2, 10 ; CHECK-BE-NEXT: vinserth 2, 2, 10
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_6_4: ; CHECK-LABEL: shuffle_vector_halfword_6_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinserth 2, 2, 2 ; CHECK-NEXT: vinserth 2, 2, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_6_4: ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
; CHECK-LABEL: shuffle_vector_halfword_7_4: ; CHECK-LABEL: shuffle_vector_halfword_7_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinserth 2, 2, 0 ; CHECK-NEXT: vinserth 2, 2, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_halfword_7_4: ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4> %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
ret <8 x i16> %vecins ret <8 x i16> %vecins
} }
; The following testcases take one byte element from the second vector and ; The following testcases take one byte element from the second vector and
▲ Show 20 Lines • Show All 861 Lines • ▼ Show 20 Lines
; The following testcases use the same vector in both arguments of the ; The following testcases use the same vector in both arguments of the
; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one ; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one
; we're attempting to insert, then we can use the vector insert instruction ; we're attempting to insert, then we can use the vector insert instruction
define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_0_7: ; CHECK-LABEL: shuffle_vector_byte_0_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_0_7: ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 0 ; CHECK-BE-NEXT: vinsertb 2, 2, 0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_1_8: ; CHECK-LABEL: shuffle_vector_byte_1_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 14 ; CHECK-NEXT: vinsertb 2, 2, 14
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_1_8: ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_2_8: ; CHECK-LABEL: shuffle_vector_byte_2_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 13 ; CHECK-NEXT: vinsertb 2, 2, 13
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_2_8: ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_3_7: ; CHECK-LABEL: shuffle_vector_byte_3_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_3_7: ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 3 ; CHECK-BE-NEXT: vinsertb 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_4_7: ; CHECK-LABEL: shuffle_vector_byte_4_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_4_7: ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 4 ; CHECK-BE-NEXT: vinsertb 2, 2, 4
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_5_8: ; CHECK-LABEL: shuffle_vector_byte_5_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 10 ; CHECK-NEXT: vinsertb 2, 2, 10
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_5_8: ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_6_8: ; CHECK-LABEL: shuffle_vector_byte_6_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 9 ; CHECK-NEXT: vinsertb 2, 2, 9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_6_8: ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_7_8: ; CHECK-LABEL: shuffle_vector_byte_7_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 8 ; CHECK-NEXT: vinsertb 2, 2, 8
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_7_8: ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_8_7: ; CHECK-LABEL: shuffle_vector_byte_8_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_8_7: ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 8 ; CHECK-BE-NEXT: vinsertb 2, 2, 8
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_9_7: ; CHECK-LABEL: shuffle_vector_byte_9_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_9_7: ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 9 ; CHECK-BE-NEXT: vinsertb 2, 2, 9
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_10_7: ; CHECK-LABEL: shuffle_vector_byte_10_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_10_7: ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 10 ; CHECK-BE-NEXT: vinsertb 2, 2, 10
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_11_8: ; CHECK-LABEL: shuffle_vector_byte_11_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 4 ; CHECK-NEXT: vinsertb 2, 2, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_11_8: ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_12_8: ; CHECK-LABEL: shuffle_vector_byte_12_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 3 ; CHECK-NEXT: vinsertb 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_12_8: ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_13_7: ; CHECK-LABEL: shuffle_vector_byte_13_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_13_7: ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 13 ; CHECK-BE-NEXT: vinsertb 2, 2, 13
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_14_7: ; CHECK-LABEL: shuffle_vector_byte_14_7:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l
; CHECK-NEXT: lxvx 35, 0, 3 ; CHECK-NEXT: lxv 35, 0(3)
; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_14_7: ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vinsertb 2, 2, 14 ; CHECK-BE-NEXT: vinsertb 2, 2, 14
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
; CHECK-LABEL: shuffle_vector_byte_15_8: ; CHECK-LABEL: shuffle_vector_byte_15_8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertb 2, 2, 0 ; CHECK-NEXT: vinsertb 2, 2, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: shuffle_vector_byte_15_8: ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8> %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
; The following tests try to insert one halfword element into the vector. We ; The following tests try to insert one halfword element into the vector. We
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llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll

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} }
; FIXME: we should always convert X-Form instructions that use ; FIXME: we should always convert X-Form instructions that use
; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt. ; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
define dso_local void @ReadWrite128() local_unnamed_addr #0 { define dso_local void @ReadWrite128() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWrite128: ; CHECK-LABEL: ReadWrite128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, input128@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, input128@got@pcrel(0), 1
; CHECK-NEXT: lxvx vs0, 0, r3 ; CHECK-NEXT: .Lpcrel4:
; CHECK-NEXT: .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: pld r3, output128@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, output128@got@pcrel(0), 1
; CHECK-NEXT: stxvx vs0, 0, r3 ; CHECK-NEXT: .Lpcrel5:
; CHECK-NEXT: .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i128, i128* @input128, align 16 %0 = load i128, i128* @input128, align 16
store i128 %0, i128* @output128, align 16 store i128 %0, i128* @output128, align 16
ret void ret void
} }
define dso_local void @ReadWritef32() local_unnamed_addr #0 { define dso_local void @ReadWritef32() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWritef32: ; CHECK-LABEL: ReadWritef32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, inputf32@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, inputf32@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel4: ; CHECK-NEXT: .Lpcrel6:
; CHECK-NEXT: xxspltidp vs1, 1078103900 ; CHECK-NEXT: xxspltidp vs1, 1078103900
; CHECK-NEXT: .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8) ; CHECK-NEXT: .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
; CHECK-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: pld r3, outputf32@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, outputf32@got@pcrel(0), 1
; CHECK-NEXT: xsaddsp f0, f0, f1 ; CHECK-NEXT: xsaddsp f0, f0, f1
; CHECK-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load float, float* @inputf32, align 4 %0 = load float, float* @inputf32, align 4
%add = fadd float %0, 0x400851EB80000000 %add = fadd float %0, 0x400851EB80000000
store float %add, float* @outputf32, align 4 store float %add, float* @outputf32, align 4
ret void ret void
} }
define dso_local void @ReadWritef64() local_unnamed_addr #0 { define dso_local void @ReadWritef64() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWritef64: ; CHECK-LABEL: ReadWritef64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, inputf64@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, inputf64@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel5: ; CHECK-NEXT: .Lpcrel7:
; CHECK-NEXT: plfd f1, .LCPI6_0@PCREL(0), 1 ; CHECK-NEXT: plfd f1, .LCPI6_0@PCREL(0), 1
; CHECK-NEXT: .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8) ; CHECK-NEXT: .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
; CHECK-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: pld r3, outputf64@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, outputf64@got@pcrel(0), 1
; CHECK-NEXT: xsadddp f0, f0, f1 ; CHECK-NEXT: xsadddp f0, f0, f1
; CHECK-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load double, double* @inputf64, align 8 %0 = load double, double* @inputf64, align 8
%add = fadd double %0, 6.800000e+00 %add = fadd double %0, 6.800000e+00
store double %add, double* @outputf64, align 8 store double %add, double* @outputf64, align 8
ret void ret void
} }
; FIXME: we should always convert X-Form instructions that use ; FIXME: we should always convert X-Form instructions that use
; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt. ; PPC::ZERO[8] to the corresponding D-Form so we can perform this opt.
define dso_local void @ReadWriteVi32() local_unnamed_addr #0 { define dso_local void @ReadWriteVi32() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWriteVi32: ; CHECK-LABEL: ReadWriteVi32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel8:
; CHECK-NEXT: li r4, 45 ; CHECK-NEXT: li r4, 45
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: pld r3, outputVi32@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, outputVi32@got@pcrel(0), 1
; CHECK-NEXT: vinsw v2, r4, 8 ; CHECK-NEXT: vinsw v2, r4, 8
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16 %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
%vecins = insertelement <4 x i32> %0, i32 45, i32 1 %vecins = insertelement <4 x i32> %0, i32 45, i32 1
store <4 x i32> %vecins, <4 x i32>* @outputVi32, align 16 store <4 x i32> %vecins, <4 x i32>* @outputVi32, align 16
ret void ret void
} }
define dso_local void @ReadWriteVi64() local_unnamed_addr #0 { define dso_local void @ReadWriteVi64() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWriteVi64: ; CHECK-LABEL: ReadWriteVi64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, inputVi64@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, inputVi64@got@pcrel(0), 1
; CHECK-NEXT: lxvx vs0, 0, r3 ; CHECK-NEXT: .Lpcrel9:
; CHECK-NEXT: .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
; CHECK-NEXT: lxv vs0, 0(r3)
; CHECK-NEXT: pld r3, outputVi64@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, outputVi64@got@pcrel(0), 1
; CHECK-NEXT: stxvx vs0, 0, r3 ; CHECK-NEXT: .Lpcrel10:
; CHECK-NEXT: .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8)
; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load <2 x i64>, <2 x i64>* @inputVi64, align 16 %0 = load <2 x i64>, <2 x i64>* @inputVi64, align 16
store <2 x i64> %0, <2 x i64>* @outputVi64, align 16 store <2 x i64> %0, <2 x i64>* @outputVi64, align 16
ret void ret void
} }
define dso_local void @ReadWriteArray() local_unnamed_addr #0 { define dso_local void @ReadWriteArray() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWriteArray: ; CHECK-LABEL: ReadWriteArray:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, ArrayIn@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, ArrayIn@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel6: ; CHECK-NEXT: .Lpcrel11:
; CHECK-NEXT: pld r4, ArrayOut@got@pcrel(0), 1 ; CHECK-NEXT: pld r4, ArrayOut@got@pcrel(0), 1
; CHECK-NEXT: .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8) ; CHECK-NEXT: .reloc .Lpcrel11-8,R_PPC64_PCREL_OPT,.-(.Lpcrel11-8)
; CHECK-NEXT: lwz r3, 28(r3) ; CHECK-NEXT: lwz r3, 28(r3)
; CHECK-NEXT: addi r3, r3, 42 ; CHECK-NEXT: addi r3, r3, 42
; CHECK-NEXT: stw r3, 8(r4) ; CHECK-NEXT: stw r3, 8(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 7), align 4 %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 7), align 4
%add = add nsw i32 %0, 42 %add = add nsw i32 %0, 42
store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayOut, i64 0, i64 2), align 4 store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayOut, i64 0, i64 2), align 4
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store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 6), align 4 store i32 %add, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ArrayIn, i64 0, i64 6), align 4
ret void ret void
} }
define dso_local void @ReadWriteIntPtr() local_unnamed_addr #0 { define dso_local void @ReadWriteIntPtr() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWriteIntPtr: ; CHECK-LABEL: ReadWriteIntPtr:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, IntPtrIn@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, IntPtrIn@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel7: ; CHECK-NEXT: .Lpcrel12:
; CHECK-NEXT: pld r4, IntPtrOut@got@pcrel(0), 1 ; CHECK-NEXT: pld r4, IntPtrOut@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel8: ; CHECK-NEXT: .Lpcrel13:
; CHECK-NEXT: .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8) ; CHECK-NEXT: .reloc .Lpcrel12-8,R_PPC64_PCREL_OPT,.-(.Lpcrel12-8)
; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8) ; CHECK-NEXT: .reloc .Lpcrel13-8,R_PPC64_PCREL_OPT,.-(.Lpcrel13-8)
; CHECK-NEXT: ld r4, 0(r4) ; CHECK-NEXT: ld r4, 0(r4)
; CHECK-NEXT: lwz r5, 216(r3) ; CHECK-NEXT: lwz r5, 216(r3)
; CHECK-NEXT: lwz r3, 48(r3) ; CHECK-NEXT: lwz r3, 48(r3)
; CHECK-NEXT: add r3, r3, r5 ; CHECK-NEXT: add r3, r3, r5
; CHECK-NEXT: stw r3, 136(r4) ; CHECK-NEXT: stw r3, 136(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i32*, i32** @IntPtrIn, align 8 %0 = load i32*, i32** @IntPtrIn, align 8
%arrayidx = getelementptr inbounds i32, i32* %0, i64 54 %arrayidx = getelementptr inbounds i32, i32* %0, i64 54
%1 = load i32, i32* %arrayidx, align 4 %1 = load i32, i32* %arrayidx, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %0, i64 12 %arrayidx1 = getelementptr inbounds i32, i32* %0, i64 12
%2 = load i32, i32* %arrayidx1, align 4 %2 = load i32, i32* %arrayidx1, align 4
%add = add nsw i32 %2, %1 %add = add nsw i32 %2, %1
%3 = load i32*, i32** @IntPtrOut, align 8 %3 = load i32*, i32** @IntPtrOut, align 8
%arrayidx2 = getelementptr inbounds i32, i32* %3, i64 34 %arrayidx2 = getelementptr inbounds i32, i32* %3, i64 34
store i32 %add, i32* %arrayidx2, align 4 store i32 %add, i32* %arrayidx2, align 4
ret void ret void
} }
define dso_local void @ReadWriteFuncPtr() local_unnamed_addr #0 { define dso_local void @ReadWriteFuncPtr() local_unnamed_addr #0 {
; CHECK-LABEL: ReadWriteFuncPtr: ; CHECK-LABEL: ReadWriteFuncPtr:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel9: ; CHECK-NEXT: .Lpcrel14:
; CHECK-NEXT: pld r4, FuncPtrOut@got@pcrel(0), 1 ; CHECK-NEXT: pld r4, FuncPtrOut@got@pcrel(0), 1
; CHECK-NEXT: .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8) ; CHECK-NEXT: .reloc .Lpcrel14-8,R_PPC64_PCREL_OPT,.-(.Lpcrel14-8)
; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load i64, i64* bitcast (void (...)** @FuncPtrIn to i64*), align 8 %0 = load i64, i64* bitcast (void (...)** @FuncPtrIn to i64*), align 8
store i64 %0, i64* bitcast (void (...)** @FuncPtrOut to i64*), align 8 store i64 %0, i64* bitcast (void (...)** @FuncPtrOut to i64*), align 8
ret void ret void
} }
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} }
declare void @Callee(...) declare void @Callee(...)
define dso_local void @FuncPtrCall() local_unnamed_addr #0 { define dso_local void @FuncPtrCall() local_unnamed_addr #0 {
; CHECK-LABEL: FuncPtrCall: ; CHECK-LABEL: FuncPtrCall:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel10: ; CHECK-NEXT: .Lpcrel15:
; CHECK-NEXT: .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8) ; CHECK-NEXT: .reloc .Lpcrel15-8,R_PPC64_PCREL_OPT,.-(.Lpcrel15-8)
; CHECK-NEXT: ld r12, 0(r3) ; CHECK-NEXT: ld r12, 0(r3)
; CHECK-NEXT: mtctr r12 ; CHECK-NEXT: mtctr r12
; CHECK-NEXT: bctr ; CHECK-NEXT: bctr
; CHECK-NEXT: #TC_RETURNr8 ctr 0 ; CHECK-NEXT: #TC_RETURNr8 ctr 0
entry: entry:
%0 = load void ()*, void ()** bitcast (void (...)** @FuncPtrIn to void ()**), align 8 %0 = load void ()*, void ()** bitcast (void (...)** @FuncPtrIn to void ()**), align 8
tail call void %0() tail call void %0()
ret void ret void
} }
define dso_local signext i32 @ReadVecElement() local_unnamed_addr #0 { define dso_local signext i32 @ReadVecElement() local_unnamed_addr #0 {
; CHECK-LABEL: ReadVecElement: ; CHECK-LABEL: ReadVecElement:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1 ; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1
; CHECK-NEXT: .Lpcrel11: ; CHECK-NEXT: .Lpcrel16:
; CHECK-NEXT: .reloc .Lpcrel11-8,R_PPC64_PCREL_OPT,.-(.Lpcrel11-8) ; CHECK-NEXT: .reloc .Lpcrel16-8,R_PPC64_PCREL_OPT,.-(.Lpcrel16-8)
; CHECK-NEXT: lwa r3, 4(r3) ; CHECK-NEXT: lwa r3, 4(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16 %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16
%vecext = extractelement <4 x i32> %0, i32 1 %vecext = extractelement <4 x i32> %0, i32 1
ret i32 %vecext ret i32 %vecext
} }
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llvm/test/CodeGen/PowerPC/pcrel_ldst.ll

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; CHECK-P10-LE-NEXT: plxv vs0, GlobLd11@PCREL(0), 1 ; CHECK-P10-LE-NEXT: plxv vs0, GlobLd11@PCREL(0), 1
; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt11@PCREL(0), 1 ; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt11@PCREL(0), 1
; CHECK-P10-LE-NEXT: blr ; CHECK-P10-LE-NEXT: blr
; ;
; CHECK-P10-BE-LABEL: testGlob11PtrPlus0: ; CHECK-P10-BE-LABEL: testGlob11PtrPlus0:
; CHECK-P10-BE: # %bb.0: # %entry ; CHECK-P10-BE: # %bb.0: # %entry
; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P10-BE-NEXT: lxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: lxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P10-BE-NEXT: stxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: stxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: blr ; CHECK-P10-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: testGlob11PtrPlus0: ; CHECK-P9-LABEL: testGlob11PtrPlus0:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P9-NEXT: lxvx vs0, 0, r3 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
; CHECK-P9-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobSt11@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobSt11@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobSt11@toc@l
; CHECK-P9-NEXT: stxvx vs0, 0, r3 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob11PtrPlus0: ; CHECK-P8-LE-LABEL: testGlob11PtrPlus0:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd11@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd11@toc@l
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt11@toc@ha
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; CHECK-P10-LE-NEXT: plxv vs0, GlobLd12@PCREL(0), 1 ; CHECK-P10-LE-NEXT: plxv vs0, GlobLd12@PCREL(0), 1
; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt12@PCREL(0), 1 ; CHECK-P10-LE-NEXT: pstxv vs0, GlobSt12@PCREL(0), 1
; CHECK-P10-LE-NEXT: blr ; CHECK-P10-LE-NEXT: blr
; ;
; CHECK-P10-BE-LABEL: testGlob12PtrPlus0: ; CHECK-P10-BE-LABEL: testGlob12PtrPlus0:
; CHECK-P10-BE: # %bb.0: # %entry ; CHECK-P10-BE: # %bb.0: # %entry
; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P10-BE-NEXT: lxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: lxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P10-BE-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P10-BE-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P10-BE-NEXT: stxvx vs0, 0, r3 ; CHECK-P10-BE-NEXT: stxv vs0, 0(r3)
; CHECK-P10-BE-NEXT: blr ; CHECK-P10-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: testGlob12PtrPlus0: ; CHECK-P9-LABEL: testGlob12PtrPlus0:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P9-NEXT: lxvx vs0, 0, r3 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
; CHECK-P9-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobSt12@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobSt12@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobSt12@toc@l
; CHECK-P9-NEXT: stxvx vs0, 0, r3 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: testGlob12PtrPlus0: ; CHECK-P8-LE-LABEL: testGlob12PtrPlus0:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobLd12@toc@ha
; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l ; CHECK-P8-LE-NEXT: addi r3, r3, GlobLd12@toc@l
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha ; CHECK-P8-LE-NEXT: addis r3, r2, GlobSt12@toc@ha
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llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll

Show All 27 Lines
; CHECK-NEXT: std 6, 72(1) ; CHECK-NEXT: std 6, 72(1)
; CHECK-NEXT: std 5, 64(1) ; CHECK-NEXT: std 5, 64(1)
; CHECK-NEXT: std 3, 48(1) ; CHECK-NEXT: std 3, 48(1)
; CHECK-NEXT: std 4, 56(1) ; CHECK-NEXT: std 4, 56(1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-VSX-LABEL: test: ; CHECK-VSX-LABEL: test:
; CHECK-VSX: # %bb.0: # %entry ; CHECK-VSX: # %bb.0: # %entry
; CHECK-VSX-NEXT: std 3, 48(1)
; CHECK-VSX-NEXT: std 6, 72(1)
; CHECK-VSX-NEXT: std 5, 64(1)
; CHECK-VSX-NEXT: std 4, 56(1)
; CHECK-VSX-NEXT: std 5, -16(1) ; CHECK-VSX-NEXT: std 5, -16(1)
; CHECK-VSX-NEXT: std 6, -8(1) ; CHECK-VSX-NEXT: std 6, -8(1)
; CHECK-VSX-NEXT: lfd 1, -16(1) ; CHECK-VSX-NEXT: lfd 1, -16(1)
; CHECK-VSX-NEXT: lfd 2, -8(1) ; CHECK-VSX-NEXT: lfd 2, -8(1)
; CHECK-VSX-NEXT: std 6, 72(1)
; CHECK-VSX-NEXT: std 5, 64(1)
; CHECK-VSX-NEXT: std 3, 48(1)
; CHECK-VSX-NEXT: std 4, 56(1)
; CHECK-VSX-NEXT: blr ; CHECK-VSX-NEXT: blr
; ;
; CHECK-P9-LABEL: test: ; CHECK-P9-LABEL: test:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd 1, 5 ; CHECK-P9-NEXT: mtfprd 1, 5
; CHECK-P9-NEXT: mtfprd 2, 6 ; CHECK-P9-NEXT: mtfprd 2, 6
; CHECK-P9-NEXT: std 6, 72(1) ; CHECK-P9-NEXT: std 6, 72(1)
; CHECK-P9-NEXT: std 5, 64(1) ; CHECK-P9-NEXT: std 5, 64(1)
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llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll

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; CHECK-LE: blr ; CHECK-LE: blr
; CHECK-P9-LABEL: @v1i128_increment_by_one ; CHECK-P9-LABEL: @v1i128_increment_by_one
; The below FIXME is due to the lowering for BUILD_VECTOR that will be fixed ; The below FIXME is due to the lowering for BUILD_VECTOR that will be fixed
; in a subsequent patch. ; in a subsequent patch.
; FIXME: li [[R1:r[0-9]+]], 1 ; FIXME: li [[R1:r[0-9]+]], 1
; FIXME: li [[R2:r[0-9]+]], 0 ; FIXME: li [[R2:r[0-9]+]], 0
; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]] ; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
; CHECK-P9: lxvx [[V1:v[0-9]+]] ; CHECK-P9: lxv [[V1:v[0-9]+]]
; CHECK-P9: vadduqm v2, v2, [[V1]] ; CHECK-P9: vadduqm v2, v2, [[V1]]
; CHECK-P9: blr ; CHECK-P9: blr
; CHECK-BE-LABEL: @v1i128_increment_by_one ; CHECK-BE-LABEL: @v1i128_increment_by_one
; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}} ; CHECK-BE: lxvd2x 35, {{[0-9]+}}, {{[0-9]+}}
; CHECK-BE-NOT: xxswapd ; CHECK-BE-NOT: xxswapd
; CHECK-BE: vadduqm 2, 2, 3 ; CHECK-BE: vadduqm 2, 2, 3
; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}} ; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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; CHECK-LE-LABEL: @call_v1i128_increment_by_val ; CHECK-LE-LABEL: @call_v1i128_increment_by_val
; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}}
; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}}
; CHECK-LE: bl v1i128_increment_by_val ; CHECK-LE: bl v1i128_increment_by_val
; CHECK-LE: blr ; CHECK-LE: blr
; CHECK-P9-LABEL: @call_v1i128_increment_by_val ; CHECK-P9-LABEL: @call_v1i128_increment_by_val
; CHECK-P9-DAG: lxvx v2 ; CHECK-P9-DAG: lxv v2
; CHECK-P9-DAG: lxvx v3 ; CHECK-P9-DAG: lxv v3
; CHECK-P9: bl v1i128_increment_by_val ; CHECK-P9: bl v1i128_increment_by_val
; CHECK-P9: blr ; CHECK-P9: blr
; CHECK-BE-LABEL: @call_v1i128_increment_by_val ; CHECK-BE-LABEL: @call_v1i128_increment_by_val
; CHECK-BE-DAG: lxvw4x 35, {{[0-9]+}}, {{[0-9]+}} ; CHECK-BE-DAG: lxvw4x 35, {{[0-9]+}}, {{[0-9]+}}
; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}} ; CHECK-BE-NOT: xxswapd 34, {{[0-9]+}}
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llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

Show First 20 Lines • Show All 1,287 Lines • ▼ Show 20 Lines
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -48(1) ; PC64LE-NEXT: stdu 1, -48(1)
; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3)
; PC64LE-NEXT: fcmpo 0, 2, 3
; PC64LE-NEXT: lis 3, -32768 ; PC64LE-NEXT: lis 3, -32768
; PC64LE-NEXT: fcmpo 0, 2, 3
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: fcmpo 1, 1, 0 ; PC64LE-NEXT: fcmpo 1, 1, 0
; PC64LE-NEXT: crand 20, 6, 0 ; PC64LE-NEXT: crand 20, 6, 0
; PC64LE-NEXT: crandc 21, 4, 6 ; PC64LE-NEXT: crandc 21, 4, 6
; PC64LE-NEXT: cror 20, 21, 20 ; PC64LE-NEXT: cror 20, 21, 20
; PC64LE-NEXT: isel 30, 0, 3, 20 ; PC64LE-NEXT: isel 30, 0, 3, 20
; PC64LE-NEXT: bc 12, 20, .LBB31_2 ; PC64LE-NEXT: bc 12, 20, .LBB31_2
; PC64LE-NEXT: # %bb.1: # %entry ; PC64LE-NEXT: # %bb.1: # %entry
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; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: mr 29, 3 ; PC64LE-NEXT: mr 29, 3
; PC64LE-NEXT: xxlxor 2, 2, 2 ; PC64LE-NEXT: xxlxor 2, 2, 2
; PC64LE-NEXT: li 3, 0 ; PC64LE-NEXT: li 3, 0
; PC64LE-NEXT: mr 30, 4 ; PC64LE-NEXT: mr 30, 4
; PC64LE-NEXT: lfsx 31, 0, 29 ; PC64LE-NEXT: lfs 31, 0(29)
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: std 3, 8(4) ; PC64LE-NEXT: std 3, 8(4)
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
; PC64LE-NEXT: fmr 3, 31 ; PC64LE-NEXT: fmr 3, 31
; PC64LE-NEXT: stfdx 31, 0, 4 ; PC64LE-NEXT: stfd 31, 0(4)
; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: bl __gcc_qadd
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 3, 1
; PC64LE-NEXT: fmr 4, 2 ; PC64LE-NEXT: fmr 4, 2
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: fmr 29, 2 ; PC64LE-NEXT: fmr 29, 2
; PC64LE-NEXT: stfd 2, 24(30) ; PC64LE-NEXT: stfd 2, 24(30)
; PC64LE-NEXT: stfd 1, 16(30) ; PC64LE-NEXT: stfd 1, 16(30)
; PC64LE-NEXT: bl __gcc_qmul ; PC64LE-NEXT: bl __gcc_qmul
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
; PC64LE-NEXT: xxlxor 2, 2, 2 ; PC64LE-NEXT: xxlxor 2, 2, 2
; PC64LE-NEXT: li 5, 2 ; PC64LE-NEXT: li 5, 2
; PC64LE-NEXT: stfd 29, 40(30) ; PC64LE-NEXT: stfd 29, 40(30)
; PC64LE-NEXT: stfd 30, 32(30) ; PC64LE-NEXT: stfd 30, 32(30)
; PC64LE-NEXT: bl __powitf2 ; PC64LE-NEXT: bl __powitf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xsrsp 0, 1 ; PC64LE-NEXT: xsrsp 0, 1
; PC64LE-NEXT: stfsx 0, 0, 29 ; PC64LE-NEXT: stfs 0, 0(29)
; PC64LE-NEXT: stfd 1, -16(30) ; PC64LE-NEXT: stfd 1, -16(30)
; PC64LE-NEXT: stfd 2, -8(30) ; PC64LE-NEXT: stfd 2, -8(30)
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
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; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: mr 30, 3 ; PC64LE-NEXT: mr 30, 3
; PC64LE-NEXT: bl __floatditf ; PC64LE-NEXT: bl __floatditf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: fmr 31, 2
; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3) ; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3)
; PC64LE-NEXT: fmr 31, 2
; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: bl __gcc_qadd
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: cmpdi 30, 0 ; PC64LE-NEXT: cmpdi 30, 0
; PC64LE-NEXT: blt 0, .LBB36_2 ; PC64LE-NEXT: blt 0, .LBB36_2
; PC64LE-NEXT: # %bb.1: # %entry ; PC64LE-NEXT: # %bb.1: # %entry
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: .LBB36_2: # %entry ; PC64LE-NEXT: .LBB36_2: # %entry
; PC64LE-NEXT: blt 0, .LBB36_4 ; PC64LE-NEXT: blt 0, .LBB36_4
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; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: mr 30, 4 ; PC64LE-NEXT: mr 30, 4
; PC64LE-NEXT: bl __floattitf ; PC64LE-NEXT: bl __floattitf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: fmr 31, 2
; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3) ; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3)
; PC64LE-NEXT: fmr 31, 2
; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: bl __gcc_qadd
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: cmpdi 30, 0 ; PC64LE-NEXT: cmpdi 30, 0
; PC64LE-NEXT: blt 0, .LBB38_2 ; PC64LE-NEXT: blt 0, .LBB38_2
; PC64LE-NEXT: # %bb.1: # %entry ; PC64LE-NEXT: # %bb.1: # %entry
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: .LBB38_2: # %entry ; PC64LE-NEXT: .LBB38_2: # %entry
; PC64LE-NEXT: blt 0, .LBB38_4 ; PC64LE-NEXT: blt 0, .LBB38_4
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llvm/test/CodeGen/PowerPC/pr30715.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%11 = load float, float* %arrayidx.i, align 4 %11 = load float, float* %arrayidx.i, align 4
%conv = fpext float %11 to ppc_fp128 %conv = fpext float %11 to ppc_fp128
%add = fadd ppc_fp128 %conv, %conv %add = fadd ppc_fp128 %conv, %conv
%conv4 = fptrunc ppc_fp128 %add to float %conv4 = fptrunc ppc_fp128 %add to float
store float %conv4, float* %arrayidx.i, align 4 store float %conv4, float* %arrayidx.i, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
; CHECK: stfdx ; CHECK: stfd
; CHECK: lxvd2x ; CHECK: lxvd2x
} }
declare signext i32 @fn1(%class.FullMatrix*) local_unnamed_addr #1 declare signext i32 @fn1(%class.FullMatrix*) local_unnamed_addr #1

llvm/test/CodeGen/PowerPC/pr36292.ll

Show All 13 Lines
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: ld 29, 0(3) ; CHECK-NEXT: ld 29, 0(3)
; CHECK-NEXT: ld 30, 32(1) ; CHECK-NEXT: ld 30, 32(1)
; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: cmpld 30, 29
; CHECK-NEXT: bge- 0, .LBB0_2 ; CHECK-NEXT: bge- 0, .LBB0_2
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %bounds.ok ; CHECK-NEXT: .LBB0_1: # %bounds.ok
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfsx 2, 0, 3 ; CHECK-NEXT: lfs 2, 0(3)
; CHECK-NEXT: xxlxor 1, 1, 1 ; CHECK-NEXT: xxlxor 1, 1, 1
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 30, 30, 1 ; CHECK-NEXT: addi 30, 30, 1
; CHECK-NEXT: stfsx 1, 0, 3 ; CHECK-NEXT: stfs 1, 0(3)
; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: cmpld 30, 29
; CHECK-NEXT: blt+ 0, .LBB0_1 ; CHECK-NEXT: blt+ 0, .LBB0_1
; CHECK-NEXT: .LBB0_2: # %bounds.fail ; CHECK-NEXT: .LBB0_2: # %bounds.fail
; CHECK-NEXT: std 30, 32(1) ; CHECK-NEXT: std 30, 32(1)
%pos = alloca i64, align 8 %pos = alloca i64, align 8
br label %forcond br label %forcond
forcond: ; preds = %bounds.ok, %0 forcond: ; preds = %bounds.ok, %0
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llvm/test/CodeGen/PowerPC/pr38087.ll

Show All 11 Lines
; CHECK-LABEL: draw_llvm_vs_variant0: ; CHECK-LABEL: draw_llvm_vs_variant0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v3, 0(r3) ; CHECK-NEXT: lxsd v3, 0(r3)
; CHECK-NEXT: vmrghh v3, v3, v3 ; CHECK-NEXT: vmrghh v3, v3, v3
; CHECK-NEXT: vextsh2w v3, v3 ; CHECK-NEXT: vextsh2w v3, v3
; CHECK-NEXT: xvcvsxwsp vs0, v3 ; CHECK-NEXT: xvcvsxwsp vs0, v3
; CHECK-NEXT: xxspltw vs0, vs0, 2 ; CHECK-NEXT: xxspltw vs0, vs0, 2
; CHECK-NEXT: xvmaddasp vs0, v2, v2 ; CHECK-NEXT: xvmaddasp vs0, v2, v2
; CHECK-NEXT: stxvx vs0, 0, r3 ; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%.size = load i32, i32* undef %.size = load i32, i32* undef
%0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7) %0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7)
%1 = extractvalue { i32, i1 } %0, 0 %1 = extractvalue { i32, i1 } %0, 0
%2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0) %2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0)
%3 = extractvalue { i32, i1 } %2, 0 %3 = extractvalue { i32, i1 } %2, 0
%4 = select i1 false, i32 0, i32 %3 %4 = select i1 false, i32 0, i32 %3
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llvm/test/CodeGen/PowerPC/pr45628.ll

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Linesentry:
ret <1 x i128> %or ret <1 x i128> %or
} }
define <1 x i128> @NO_rotl(<1 x i128> %num) { define <1 x i128> @NO_rotl(<1 x i128> %num) {
; P9-VSX-LABEL: NO_rotl: ; P9-VSX-LABEL: NO_rotl:
; P9-VSX: # %bb.0: # %entry ; P9-VSX: # %bb.0: # %entry
; P9-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; P9-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha
; P9-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l ; P9-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l
; P9-VSX-NEXT: lxvx v3, 0, r3 ; P9-VSX-NEXT: lxv v3, 0(r3)
; P9-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha ; P9-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha
; P9-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l ; P9-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l
; P9-VSX-NEXT: vslo v4, v2, v3 ; P9-VSX-NEXT: vslo v4, v2, v3
; P9-VSX-NEXT: vspltb v3, v3, 15 ; P9-VSX-NEXT: vspltb v3, v3, 15
; P9-VSX-NEXT: vsl v3, v4, v3 ; P9-VSX-NEXT: vsl v3, v4, v3
; P9-VSX-NEXT: lxvx v4, 0, r3 ; P9-VSX-NEXT: lxv v4, 0(r3)
; P9-VSX-NEXT: vsro v2, v2, v4 ; P9-VSX-NEXT: vsro v2, v2, v4
; P9-VSX-NEXT: vspltb v4, v4, 15 ; P9-VSX-NEXT: vspltb v4, v4, 15
; P9-VSX-NEXT: vsr v2, v2, v4 ; P9-VSX-NEXT: vsr v2, v2, v4
; P9-VSX-NEXT: xxlor v2, v3, v2 ; P9-VSX-NEXT: xxlor v2, v3, v2
; P9-VSX-NEXT: blr ; P9-VSX-NEXT: blr
; ;
; P9-NOVSX-LABEL: NO_rotl: ; P9-NOVSX-LABEL: NO_rotl:
; P9-NOVSX: # %bb.0: # %entry ; P9-NOVSX: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

Show All 10 Lines
define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_1: ; CHECK-LABEL: test_pre_inc_disable_1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v5, 0(r5) ; CHECK-NEXT: lxsd v5, 0(r5)
; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: li r6, 0
; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l
; CHECK-NEXT: lxvx v2, 0, r5 ; CHECK-NEXT: lxv v2, 0(r5)
; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha
; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l
; CHECK-NEXT: lxvx v4, 0, r5 ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: li r5, 4 ; CHECK-NEXT: li r5, 4
; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: vperm v0, v3, v5, v2
; CHECK-NEXT: mtctr r5 ; CHECK-NEXT: mtctr r5
; CHECK-NEXT: li r5, 0 ; CHECK-NEXT: li r5, 0
; CHECK-NEXT: vperm v1, v3, v5, v4 ; CHECK-NEXT: vperm v1, v3, v5, v4
; CHECK-NEXT: xvnegsp v5, v0 ; CHECK-NEXT: xvnegsp v5, v0
; CHECK-NEXT: xvnegsp v0, v1 ; CHECK-NEXT: xvnegsp v0, v1
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
Show All 36 Lines
; ;
; P9BE-LABEL: test_pre_inc_disable_1: ; P9BE-LABEL: test_pre_inc_disable_1:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfd f0, 0(r5) ; P9BE-NEXT: lfd f0, 0(r5)
; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha ; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: li r6, 0 ; P9BE-NEXT: li r6, 0
; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l
; P9BE-NEXT: lxvx v2, 0, r5 ; P9BE-NEXT: lxv v2, 0(r5)
; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha
; P9BE-NEXT: xxlor v5, vs0, vs0 ; P9BE-NEXT: xxlor v5, vs0, vs0
; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l
; P9BE-NEXT: lxvx v4, 0, r5 ; P9BE-NEXT: lxv v4, 0(r5)
; P9BE-NEXT: li r5, 4 ; P9BE-NEXT: li r5, 4
; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: vperm v0, v3, v5, v2
; P9BE-NEXT: mtctr r5 ; P9BE-NEXT: mtctr r5
; P9BE-NEXT: li r5, 0 ; P9BE-NEXT: li r5, 0
; P9BE-NEXT: vperm v1, v3, v5, v4 ; P9BE-NEXT: vperm v1, v3, v5, v4
; P9BE-NEXT: xvnegsp v5, v0 ; P9BE-NEXT: xvnegsp v5, v0
; P9BE-NEXT: xvnegsp v0, v1 ; P9BE-NEXT: xvnegsp v0, v1
; P9BE-NEXT: .p2align 4 ; P9BE-NEXT: .p2align 4
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define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) { define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
; CHECK-LABEL: test_pre_inc_disable_2: ; CHECK-LABEL: test_pre_inc_disable_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxsd v2, 0(r3) ; CHECK-NEXT: lxsd v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-NEXT: lxsd v1, 0(r4) ; CHECK-NEXT: lxsd v1, 0(r4)
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxv v4, 0(r3)
; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
; CHECK-NEXT: lxvx v0, 0, r3 ; CHECK-NEXT: lxv v0, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v5, v3, v2, v4 ; CHECK-NEXT: vperm v5, v3, v2, v4
; CHECK-NEXT: vperm v2, v3, v2, v0 ; CHECK-NEXT: vperm v2, v3, v2, v0
; CHECK-NEXT: vperm v0, v3, v1, v0 ; CHECK-NEXT: vperm v0, v3, v1, v0
; CHECK-NEXT: vperm v3, v3, v1, v4 ; CHECK-NEXT: vperm v3, v3, v1, v4
; CHECK-NEXT: vabsduw v2, v2, v0 ; CHECK-NEXT: vabsduw v2, v2, v0
; CHECK-NEXT: vabsduw v3, v5, v3 ; CHECK-NEXT: vabsduw v3, v5, v3
; CHECK-NEXT: vadduwm v2, v3, v2 ; CHECK-NEXT: vadduwm v2, v3, v2
; CHECK-NEXT: xxswapd v3, v2 ; CHECK-NEXT: xxswapd v3, v2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; P9BE-LABEL: test_pre_inc_disable_2: ; P9BE-LABEL: test_pre_inc_disable_2:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfd f0, 0(r3) ; P9BE-NEXT: lfd f0, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxv v4, 0(r3)
; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha
; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l
; P9BE-NEXT: xxlor v2, vs0, vs0 ; P9BE-NEXT: xxlor v2, vs0, vs0
; P9BE-NEXT: lfd f0, 0(r4) ; P9BE-NEXT: lfd f0, 0(r4)
; P9BE-NEXT: lxvx v0, 0, r3 ; P9BE-NEXT: lxv v0, 0(r3)
; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: xxlor v1, vs0, vs0
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v5, v3, v2, v4 ; P9BE-NEXT: vperm v5, v3, v2, v4
; P9BE-NEXT: vperm v2, v3, v2, v0 ; P9BE-NEXT: vperm v2, v3, v2, v0
; P9BE-NEXT: vperm v0, v3, v1, v0 ; P9BE-NEXT: vperm v0, v3, v1, v0
; P9BE-NEXT: vperm v3, v3, v1, v4 ; P9BE-NEXT: vperm v3, v3, v1, v4
; P9BE-NEXT: vabsduw v2, v2, v0 ; P9BE-NEXT: vabsduw v2, v2, v0
; P9BE-NEXT: vabsduw v3, v5, v3 ; P9BE-NEXT: vabsduw v3, v5, v3
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define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) { define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
; CHECK-LABEL: test32: ; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r5, r3, r4 ; CHECK-NEXT: add r5, r3, r4
; CHECK-NEXT: lxsiwzx v2, r3, r4 ; CHECK-NEXT: lxsiwzx v2, r3, r4
; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: xxlxor v3, v3, v3
; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxv v4, 0(r3)
; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: li r3, 4
; CHECK-NEXT: lxsiwzx v5, r5, r3 ; CHECK-NEXT: lxsiwzx v5, r5, r3
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: vperm v3, v5, v3, v4 ; CHECK-NEXT: vperm v3, v5, v3, v4
; CHECK-NEXT: vspltisw v4, 8 ; CHECK-NEXT: vspltisw v4, 8
; CHECK-NEXT: vnegw v3, v3 ; CHECK-NEXT: vnegw v3, v3
; CHECK-NEXT: vadduwm v4, v4, v4 ; CHECK-NEXT: vadduwm v4, v4, v4
; CHECK-NEXT: vslw v3, v3, v4 ; CHECK-NEXT: vslw v3, v3, v4
; CHECK-NEXT: vsubuwm v2, v3, v2 ; CHECK-NEXT: vsubuwm v2, v3, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: stxvx vs0, 0, r3 ; CHECK-NEXT: stxv vs0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; P9BE-LABEL: test32: ; P9BE-LABEL: test32:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: add r5, r3, r4 ; P9BE-NEXT: add r5, r3, r4
; P9BE-NEXT: lfiwzx f0, r3, r4 ; P9BE-NEXT: lfiwzx f0, r3, r4
; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: xxlxor v3, v3, v3
; P9BE-NEXT: xxsldwi v2, f0, f0, 1 ; P9BE-NEXT: xxsldwi v2, f0, f0, 1
; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxv v4, 0(r3)
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: lfiwzx f0, r5, r3 ; P9BE-NEXT: lfiwzx f0, r5, r3
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxsldwi v5, f0, f0, 1 ; P9BE-NEXT: xxsldwi v5, f0, f0, 1
; P9BE-NEXT: vperm v3, v3, v5, v4 ; P9BE-NEXT: vperm v3, v3, v5, v4
; P9BE-NEXT: vspltisw v4, 8 ; P9BE-NEXT: vspltisw v4, 8
; P9BE-NEXT: vnegw v3, v3 ; P9BE-NEXT: vnegw v3, v3
; P9BE-NEXT: vadduwm v4, v4, v4 ; P9BE-NEXT: vadduwm v4, v4, v4
; P9BE-NEXT: vslw v3, v3, v4 ; P9BE-NEXT: vslw v3, v3, v4
; P9BE-NEXT: vsubuwm v2, v3, v2 ; P9BE-NEXT: vsubuwm v2, v3, v2
; P9BE-NEXT: xxswapd vs0, v2 ; P9BE-NEXT: xxswapd vs0, v2
; P9BE-NEXT: stxvx vs0, 0, r3 ; P9BE-NEXT: stxv vs0, 0(r3)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
entry: entry:
%idx.ext63 = sext i32 %i_pix2 to i64 %idx.ext63 = sext i32 %i_pix2 to i64
%add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63 %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
%arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4 %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
%0 = bitcast i8* %add.ptr64 to <4 x i8>* %0 = bitcast i8* %add.ptr64 to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 1 %1 = load <4 x i8>, <4 x i8>* %0, align 1
%reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
Show All 27 Lines
; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT: mtvsrd v3, r6 ; CHECK-NEXT: mtvsrd v3, r6
; CHECK-NEXT: vsplth v4, v4, 3 ; CHECK-NEXT: vsplth v4, v4, 3
; CHECK-NEXT: vsplth v2, v2, 3 ; CHECK-NEXT: vsplth v2, v2, 3
; CHECK-NEXT: vmrghh v4, v3, v4 ; CHECK-NEXT: vmrghh v4, v3, v4
; CHECK-NEXT: vmrghh v2, v3, v2 ; CHECK-NEXT: vmrghh v2, v3, v2
; CHECK-NEXT: vsplth v3, v3, 3 ; CHECK-NEXT: vsplth v3, v3, 3
; CHECK-NEXT: vmrglw v3, v4, v3 ; CHECK-NEXT: vmrglw v3, v4, v3
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxv v4, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
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; P9BE-NEXT: sldi r6, r6, 48 ; P9BE-NEXT: sldi r6, r6, 48
; P9BE-NEXT: vsplth v4, v4, 3 ; P9BE-NEXT: vsplth v4, v4, 3
; P9BE-NEXT: mtvsrd v3, r6 ; P9BE-NEXT: mtvsrd v3, r6
; P9BE-NEXT: vsplth v2, v2, 3 ; P9BE-NEXT: vsplth v2, v2, 3
; P9BE-NEXT: vmrghh v4, v3, v4 ; P9BE-NEXT: vmrghh v4, v3, v4
; P9BE-NEXT: vmrghh v2, v3, v2 ; P9BE-NEXT: vmrghh v2, v3, v2
; P9BE-NEXT: vsplth v3, v3, 0 ; P9BE-NEXT: vsplth v3, v3, 0
; P9BE-NEXT: vmrghw v3, v3, v4 ; P9BE-NEXT: vmrghw v3, v3, v4
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxv v4, 0(r3)
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2 ; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw r3, r5 ; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0 ; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then ; P9BE-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT: vmrghb v2, v3, v2 ; CHECK-NEXT: vmrghb v2, v3, v2
; CHECK-NEXT: vspltb v5, v5, 7 ; CHECK-NEXT: vspltb v5, v5, 7
; CHECK-NEXT: vmrglh v2, v2, v4 ; CHECK-NEXT: vmrglh v2, v2, v4
; CHECK-NEXT: vmrghb v3, v3, v5 ; CHECK-NEXT: vmrghb v3, v3, v5
; CHECK-NEXT: vmrglw v2, v2, v4 ; CHECK-NEXT: vmrglw v2, v2, v4
; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglh v3, v3, v4
; CHECK-NEXT: vmrglw v3, v4, v3 ; CHECK-NEXT: vmrglw v3, v4, v3
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxv v4, 0(r3)
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
Show All 12 Lines
; P9BE-NEXT: mtvsrd v3, r6 ; P9BE-NEXT: mtvsrd v3, r6
; P9BE-NEXT: vspltb v2, v2, 7 ; P9BE-NEXT: vspltb v2, v2, 7
; P9BE-NEXT: vmrghb v4, v3, v4 ; P9BE-NEXT: vmrghb v4, v3, v4
; P9BE-NEXT: vmrghb v2, v3, v2 ; P9BE-NEXT: vmrghb v2, v3, v2
; P9BE-NEXT: vspltb v3, v3, 0 ; P9BE-NEXT: vspltb v3, v3, 0
; P9BE-NEXT: vmrghh v4, v4, v3 ; P9BE-NEXT: vmrghh v4, v4, v3
; P9BE-NEXT: xxspltw v3, v3, 0 ; P9BE-NEXT: xxspltw v3, v3, 0
; P9BE-NEXT: vmrghw v2, v4, v2 ; P9BE-NEXT: vmrghw v2, v4, v2
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxv v4, 0(r3)
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2 ; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw r3, r5 ; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0 ; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then ; P9BE-NEXT: # %bb.1: # %if.then
Show All 31 Lines

llvm/test/CodeGen/PowerPC/recipest.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; CHECK-P7-NEXT: fmuls 0, 0, 4 ; CHECK-P7-NEXT: fmuls 0, 0, 4
; CHECK-P7-NEXT: fmuls 0, 0, 2 ; CHECK-P7-NEXT: fmuls 0, 0, 2
; CHECK-P7-NEXT: fmul 1, 1, 0 ; CHECK-P7-NEXT: fmul 1, 1, 0
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: foof_fmf: ; CHECK-P8-LABEL: foof_fmf:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xsrsqrtesp 0, 2 ; CHECK-P8-NEXT: xsrsqrtesp 0, 2
; CHECK-P8-NEXT: addis 3, 2, .LCPI3_1@toc@ha
; CHECK-P8-NEXT: lfs 3, .LCPI3_1@toc@l(3)
; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI3_1@toc@ha ; CHECK-P8-NEXT: lfs 4, .LCPI3_0@toc@l(3)
; CHECK-P8-NEXT: lfs 3, .LCPI3_0@toc@l(3)
; CHECK-P8-NEXT: lfs 4, .LCPI3_1@toc@l(4)
; CHECK-P8-NEXT: xsmulsp 2, 2, 0 ; CHECK-P8-NEXT: xsmulsp 2, 2, 0
; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 ; CHECK-P8-NEXT: xsmulsp 3, 0, 3
; CHECK-P8-NEXT: xsmulsp 0, 0, 4 ; CHECK-P8-NEXT: xsmaddasp 4, 2, 0
; CHECK-P8-NEXT: xsmulsp 0, 0, 3 ; CHECK-P8-NEXT: xsmulsp 0, 3, 4
; CHECK-P8-NEXT: xsmuldp 1, 1, 0 ; CHECK-P8-NEXT: xsmuldp 1, 1, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: foof_fmf: ; CHECK-P9-LABEL: foof_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xsrsqrtesp 0, 2 ; CHECK-P9-NEXT: xsrsqrtesp 0, 2
; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: lfs 3, .LCPI3_0@toc@l(3) ; CHECK-P9-NEXT: lfs 3, .LCPI3_0@toc@l(3)
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; CHECK-P7-NEXT: fmuls 0, 0, 4 ; CHECK-P7-NEXT: fmuls 0, 0, 4
; CHECK-P7-NEXT: fmuls 0, 0, 2 ; CHECK-P7-NEXT: fmuls 0, 0, 2
; CHECK-P7-NEXT: fmuls 1, 1, 0 ; CHECK-P7-NEXT: fmuls 1, 1, 0
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: goo_fmf: ; CHECK-P8-LABEL: goo_fmf:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xsrsqrtesp 0, 2 ; CHECK-P8-NEXT: xsrsqrtesp 0, 2
; CHECK-P8-NEXT: addis 3, 2, .LCPI7_1@toc@ha
; CHECK-P8-NEXT: lfs 3, .LCPI7_1@toc@l(3)
; CHECK-P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI7_1@toc@ha ; CHECK-P8-NEXT: lfs 4, .LCPI7_0@toc@l(3)
; CHECK-P8-NEXT: lfs 3, .LCPI7_0@toc@l(3)
; CHECK-P8-NEXT: lfs 4, .LCPI7_1@toc@l(4)
; CHECK-P8-NEXT: xsmulsp 2, 2, 0 ; CHECK-P8-NEXT: xsmulsp 2, 2, 0
; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 ; CHECK-P8-NEXT: xsmulsp 3, 0, 3
; CHECK-P8-NEXT: xsmulsp 0, 0, 4 ; CHECK-P8-NEXT: xsmaddasp 4, 2, 0
; CHECK-P8-NEXT: xsmulsp 0, 0, 3 ; CHECK-P8-NEXT: xsmulsp 0, 3, 4
; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmulsp 1, 1, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: goo_fmf: ; CHECK-P9-LABEL: goo_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xsrsqrtesp 0, 2 ; CHECK-P9-NEXT: xsrsqrtesp 0, 2
; CHECK-P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: lfs 3, .LCPI7_0@toc@l(3) ; CHECK-P9-NEXT: lfs 3, .LCPI7_0@toc@l(3)
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; CHECK-P7-NEXT: fmadds 0, 1, 0, 4 ; CHECK-P7-NEXT: fmadds 0, 1, 0, 4
; CHECK-P7-NEXT: fmuls 1, 3, 0 ; CHECK-P7-NEXT: fmuls 1, 3, 0
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: rsqrt_fmul_fmf: ; CHECK-P8-LABEL: rsqrt_fmul_fmf:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xsrsqrtesp 0, 1 ; CHECK-P8-NEXT: xsrsqrtesp 0, 1
; CHECK-P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI10_1@toc@ha
; CHECK-P8-NEXT: lfs 4, .LCPI10_0@toc@l(3) ; CHECK-P8-NEXT: lfs 4, .LCPI10_0@toc@l(3)
; CHECK-P8-NEXT: lfs 5, .LCPI10_1@toc@l(4) ; CHECK-P8-NEXT: addis 3, 2, .LCPI10_1@toc@ha
; CHECK-P8-NEXT: lfs 5, .LCPI10_1@toc@l(3)
; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmulsp 1, 1, 0
; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 4, 1, 0
; CHECK-P8-NEXT: xsmulsp 0, 0, 5 ; CHECK-P8-NEXT: xsmulsp 0, 0, 5
; CHECK-P8-NEXT: xsresp 1, 2 ; CHECK-P8-NEXT: xsresp 1, 2
; CHECK-P8-NEXT: xsmulsp 0, 0, 4 ; CHECK-P8-NEXT: xsmulsp 0, 0, 4
; CHECK-P8-NEXT: xsmulsp 4, 0, 1 ; CHECK-P8-NEXT: xsmulsp 4, 0, 1
; CHECK-P8-NEXT: xsnmsubasp 0, 2, 4 ; CHECK-P8-NEXT: xsnmsubasp 0, 2, 4
; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 4, 1, 0
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xvmulsp 34, 34, 0 ; CHECK-P8-NEXT: xvmulsp 34, 34, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: hoo_fmf: ; CHECK-P9-LABEL: hoo_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xvrsqrtesp 0, 35 ; CHECK-P9-NEXT: xvrsqrtesp 0, 35
; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l
; CHECK-P9-NEXT: lxvx 2, 0, 3 ; CHECK-P9-NEXT: lxv 2, 0(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l
; CHECK-P9-NEXT: xvmulsp 1, 35, 0 ; CHECK-P9-NEXT: xvmulsp 1, 35, 0
; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0
; CHECK-P9-NEXT: lxvx 1, 0, 3 ; CHECK-P9-NEXT: lxv 1, 0(3)
; CHECK-P9-NEXT: xvmulsp 0, 0, 1 ; CHECK-P9-NEXT: xvmulsp 0, 0, 1
; CHECK-P9-NEXT: xvmulsp 0, 0, 2 ; CHECK-P9-NEXT: xvmulsp 0, 0, 2
; CHECK-P9-NEXT: xvmulsp 34, 34, 0 ; CHECK-P9-NEXT: xvmulsp 34, 34, 0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%x = call reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b) %x = call reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
%r = fdiv reassoc arcp <4 x float> %a, %x %r = fdiv reassoc arcp <4 x float> %a, %x
ret <4 x float> %r ret <4 x float> %r
} }
▲ Show 20 Lines • Show All 435 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI23_2@toc@ha
; CHECK-P8-NEXT: lfs 2, .LCPI23_2@toc@l(3) ; CHECK-P8-NEXT: lfs 2, .LCPI23_2@toc@l(3)
; CHECK-P8-NEXT: fcmpu 0, 0, 2 ; CHECK-P8-NEXT: fcmpu 0, 0, 2
; CHECK-P8-NEXT: xxlxor 0, 0, 0 ; CHECK-P8-NEXT: xxlxor 0, 0, 0
; CHECK-P8-NEXT: blt 0, .LBB23_2 ; CHECK-P8-NEXT: blt 0, .LBB23_2
; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: # %bb.1:
; CHECK-P8-NEXT: xsrsqrtesp 0, 1 ; CHECK-P8-NEXT: xsrsqrtesp 0, 1
; CHECK-P8-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; CHECK-P8-NEXT: addis 4, 2, .LCPI23_1@toc@ha
; CHECK-P8-NEXT: lfs 2, .LCPI23_0@toc@l(3) ; CHECK-P8-NEXT: lfs 2, .LCPI23_0@toc@l(3)
; CHECK-P8-NEXT: lfs 3, .LCPI23_1@toc@l(4) ; CHECK-P8-NEXT: addis 3, 2, .LCPI23_1@toc@ha
; CHECK-P8-NEXT: lfs 3, .LCPI23_1@toc@l(3)
; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmulsp 1, 1, 0
; CHECK-P8-NEXT: xsmaddasp 2, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 2, 1, 0
; CHECK-P8-NEXT: xsmulsp 0, 1, 3 ; CHECK-P8-NEXT: xsmulsp 0, 1, 3
; CHECK-P8-NEXT: xsmulsp 0, 0, 2 ; CHECK-P8-NEXT: xsmulsp 0, 0, 2
; CHECK-P8-NEXT: .LBB23_2: ; CHECK-P8-NEXT: .LBB23_2:
; CHECK-P8-NEXT: fmr 1, 0 ; CHECK-P8-NEXT: fmr 1, 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-P9-LABEL: hoo3_fmf: ; CHECK-P9-LABEL: hoo3_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xvtsqrtsp 0, 34 ; CHECK-P9-NEXT: xvtsqrtsp 0, 34
; CHECK-P9-NEXT: bc 12, 2, .LBB25_2 ; CHECK-P9-NEXT: bc 12, 2, .LBB25_2
; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: # %bb.1:
; CHECK-P9-NEXT: xvrsqrtesp 0, 34 ; CHECK-P9-NEXT: xvrsqrtesp 0, 34
; CHECK-P9-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI25_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI25_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI25_0@toc@l
; CHECK-P9-NEXT: lxvx 2, 0, 3 ; CHECK-P9-NEXT: lxv 2, 0(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI25_1@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI25_1@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI25_1@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI25_1@toc@l
; CHECK-P9-NEXT: xvmulsp 1, 34, 0 ; CHECK-P9-NEXT: xvmulsp 1, 34, 0
; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0
; CHECK-P9-NEXT: lxvx 0, 0, 3 ; CHECK-P9-NEXT: lxv 0, 0(3)
; CHECK-P9-NEXT: xvmulsp 0, 1, 0 ; CHECK-P9-NEXT: xvmulsp 0, 1, 0
; CHECK-P9-NEXT: xvmulsp 34, 0, 2 ; CHECK-P9-NEXT: xvmulsp 34, 0, 2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB25_2: ; CHECK-P9-NEXT: .LBB25_2:
; CHECK-P9-NEXT: xvsqrtsp 34, 34 ; CHECK-P9-NEXT: xvsqrtsp 34, 34
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%r = call reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) %r = call reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
ret <4 x float> %r ret <4 x float> %r
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; CHECK-P9-LABEL: hoo4_fmf: ; CHECK-P9-LABEL: hoo4_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xvtsqrtdp 0, 34 ; CHECK-P9-NEXT: xvtsqrtdp 0, 34
; CHECK-P9-NEXT: bc 12, 2, .LBB27_2 ; CHECK-P9-NEXT: bc 12, 2, .LBB27_2
; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: # %bb.1:
; CHECK-P9-NEXT: xvrsqrtedp 0, 34 ; CHECK-P9-NEXT: xvrsqrtedp 0, 34
; CHECK-P9-NEXT: addis 3, 2, .LCPI27_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI27_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI27_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI27_0@toc@l
; CHECK-P9-NEXT: lxvx 2, 0, 3 ; CHECK-P9-NEXT: lxv 2, 0(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI27_1@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI27_1@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI27_1@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI27_1@toc@l
; CHECK-P9-NEXT: xvmuldp 1, 34, 0 ; CHECK-P9-NEXT: xvmuldp 1, 34, 0
; CHECK-P9-NEXT: xxlor 3, 2, 2 ; CHECK-P9-NEXT: xxlor 3, 2, 2
; CHECK-P9-NEXT: xvmaddadp 3, 1, 0 ; CHECK-P9-NEXT: xvmaddadp 3, 1, 0
; CHECK-P9-NEXT: lxvx 1, 0, 3 ; CHECK-P9-NEXT: lxv 1, 0(3)
; CHECK-P9-NEXT: xvmuldp 0, 0, 1 ; CHECK-P9-NEXT: xvmuldp 0, 0, 1
; CHECK-P9-NEXT: xvmuldp 0, 0, 3 ; CHECK-P9-NEXT: xvmuldp 0, 0, 3
; CHECK-P9-NEXT: xvmuldp 3, 34, 0 ; CHECK-P9-NEXT: xvmuldp 3, 34, 0
; CHECK-P9-NEXT: xvmaddadp 2, 3, 0 ; CHECK-P9-NEXT: xvmaddadp 2, 3, 0
; CHECK-P9-NEXT: xvmuldp 0, 3, 1 ; CHECK-P9-NEXT: xvmuldp 0, 3, 1
; CHECK-P9-NEXT: xvmuldp 34, 0, 2 ; CHECK-P9-NEXT: xvmuldp 34, 0, 2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB27_2: ; CHECK-P9-NEXT: .LBB27_2:
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-NEXT: xsmulsp f0, f2, f0 ; CHECK-NEXT: xsmulsp f0, f2, f0
; CHECK-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: foo_float_reuse_const: ; CHECK-P8-LABEL: foo_float_reuse_const:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: xsmulsp f1, f2, f1 ; CHECK-P8-NEXT: xsmulsp f1, f2, f1
; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: xssubsp f0, f3, f4 ; CHECK-P8-NEXT: xssubsp f0, f3, f4
; CHECK-P8-NEXT: lfs f3, .LCPI2_0@toc@l(r3) ; CHECK-P8-NEXT: lfs f3, .LCPI2_0@toc@l(r3)
; CHECK-P8-NEXT: lfs f4, .LCPI2_1@toc@l(r4) ; CHECK-P8-NEXT: addis r3, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: lfs f4, .LCPI2_1@toc@l(r3)
; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-P8-NEXT: xsmaddasp f1, f0, f3 ; CHECK-P8-NEXT: xsmaddasp f1, f0, f3
; CHECK-P8-NEXT: xsmulsp f0, f2, f4 ; CHECK-P8-NEXT: xsmulsp f0, f2, f4
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-FMA-LABEL: foo_float_reuse_const: ; CHECK-FMA-LABEL: foo_float_reuse_const:
; CHECK-FMA: # %bb.0: ; CHECK-FMA: # %bb.0:
; CHECK-FMA-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-FMA-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-FMA-NEXT: xsmulsp f1, f2, f1 ; CHECK-FMA-NEXT: xsmulsp f1, f2, f1
; CHECK-FMA-NEXT: lfs f0, .LCPI2_0@toc@l(r3) ; CHECK-FMA-NEXT: lfs f0, .LCPI2_0@toc@l(r3)
; CHECK-FMA-NEXT: addis r3, r2, .LCPI2_1@toc@ha ; CHECK-FMA-NEXT: addis r3, r2, .LCPI2_1@toc@ha
Show All 16 Lines

llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,479 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load i32, i32* inttoptr (i64 1000000000000 to i32*), align 4096 %0 = load i32, i32* inttoptr (i64 1000000000000 to i32*), align 4096
%conv = sitofp i32 %0 to double %conv = sitofp i32 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_0_double_uint64_t(i64 %ptr) { define dso_local double @ld_0_double_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_double_uint64_t: ; CHECK-LABEL: ld_0_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to i64* %0 = inttoptr i64 %ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to i64* %0 = bitcast i8* %add.ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_or_double_uint64_t(i64 %ptr, i8 zeroext %off) { define dso_local double @ld_or_double_uint64_t(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_double_uint64_t: ; CHECK-LABEL: ld_or_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv1 = uitofp i64 %1 to double %conv1 = uitofp i64 %1 to double
ret double %conv1 ret double %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint16_double_uint64_t(i64 %ptr) { define dso_local double @ld_not_disjoint16_double_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_double_uint64_t: ; CHECK-LABEL: ld_not_disjoint16_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_disjoint_align16_double_uint64_t(i64 %ptr) { define dso_local double @ld_disjoint_align16_double_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_double_uint64_t: ; CHECK-LABEL: ld_disjoint_align16_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint32_double_uint64_t(i64 %ptr) { define dso_local double @ld_not_disjoint32_double_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_double_uint64_t: ; CHECK-LABEL: ld_not_disjoint32_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvuxddp f1, f0 ; CHECK-P10-NEXT: xscvuxddp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_double_uint64_t: ; CHECK-PREP10-LABEL: ld_not_disjoint64_double_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvuxddp f1, f0 ; CHECK-PREP10-NEXT: xscvuxddp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to double %conv = uitofp i64 %1 to double
ret double %conv ret double %conv
} }
Show All 36 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16 %0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16
%conv = uitofp i64 %0 to double %conv = uitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align32_double_uint64_t() { define dso_local double @ld_cst_align32_double_uint64_t() {
; CHECK-POSTP8-LABEL: ld_cst_align32_double_uint64_t: ; CHECK-LABEL: ld_cst_align32_double_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-POSTP8-NEXT: xscvuxddp f1, f0 ; CHECK-NEXT: xscvuxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8 %0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8
%conv = uitofp i64 %0 to double %conv = uitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align64_double_uint64_t() { define dso_local double @ld_cst_align64_double_uint64_t() {
; CHECK-P10-LABEL: ld_cst_align64_double_uint64_t: ; CHECK-P10-LABEL: ld_cst_align64_double_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvuxddp f1, f0 ; CHECK-P10-NEXT: xscvuxddp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_double_uint64_t: ; CHECK-PREP10-LABEL: ld_cst_align64_double_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvuxddp f1, f0 ; CHECK-PREP10-NEXT: xscvuxddp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_double_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = uitofp i64 %0 to double %conv = uitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_0_double_int64_t(i64 %ptr) { define dso_local double @ld_0_double_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_double_int64_t: ; CHECK-LABEL: ld_0_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to i64* %0 = inttoptr i64 %ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to i64* %0 = bitcast i8* %add.ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_or_double_int64_t(i64 %ptr, i8 zeroext %off) { define dso_local double @ld_or_double_int64_t(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_double_int64_t: ; CHECK-LABEL: ld_or_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv1 = sitofp i64 %1 to double %conv1 = sitofp i64 %1 to double
ret double %conv1 ret double %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint16_double_int64_t(i64 %ptr) { define dso_local double @ld_not_disjoint16_double_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_double_int64_t: ; CHECK-LABEL: ld_not_disjoint16_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_disjoint_align16_double_int64_t(i64 %ptr) { define dso_local double @ld_disjoint_align16_double_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_double_int64_t: ; CHECK-LABEL: ld_disjoint_align16_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint32_double_int64_t(i64 %ptr) { define dso_local double @ld_not_disjoint32_double_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_double_int64_t: ; CHECK-LABEL: ld_not_disjoint32_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvsxddp f1, f0 ; CHECK-P10-NEXT: xscvsxddp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_double_int64_t: ; CHECK-PREP10-LABEL: ld_not_disjoint64_double_int64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvsxddp f1, f0 ; CHECK-PREP10-NEXT: xscvsxddp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to double %conv = sitofp i64 %1 to double
ret double %conv ret double %conv
} }
Show All 36 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16 %0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16
%conv = sitofp i64 %0 to double %conv = sitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align32_double_int64_t() { define dso_local double @ld_cst_align32_double_int64_t() {
; CHECK-POSTP8-LABEL: ld_cst_align32_double_int64_t: ; CHECK-LABEL: ld_cst_align32_double_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-POSTP8-NEXT: xscvsxddp f1, f0 ; CHECK-NEXT: xscvsxddp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8 %0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8
%conv = sitofp i64 %0 to double %conv = sitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align64_double_int64_t() { define dso_local double @ld_cst_align64_double_int64_t() {
; CHECK-P10-LABEL: ld_cst_align64_double_int64_t: ; CHECK-P10-LABEL: ld_cst_align64_double_int64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvsxddp f1, f0 ; CHECK-P10-NEXT: xscvsxddp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_double_int64_t: ; CHECK-PREP10-LABEL: ld_cst_align64_double_int64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvsxddp f1, f0 ; CHECK-PREP10-NEXT: xscvsxddp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_double_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxddp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = sitofp i64 %0 to double %conv = sitofp i64 %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_0_double_float(i64 %ptr) { define dso_local double @ld_0_double_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_double_float: ; CHECK-LABEL: ld_0_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_or_double_float(i64 %ptr, i8 zeroext %off) { define dso_local double @ld_or_double_float(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_double_float: ; CHECK-LABEL: ld_or_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fpext float %1 to double %conv1 = fpext float %1 to double
ret double %conv1 ret double %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint16_double_float(i64 %ptr) { define dso_local double @ld_not_disjoint16_double_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_double_float: ; CHECK-LABEL: ld_not_disjoint16_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_disjoint_align16_double_float(i64 %ptr) { define dso_local double @ld_disjoint_align16_double_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_double_float: ; CHECK-LABEL: ld_disjoint_align16_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfs f1, 24(r3) ; CHECK-NEXT: lfs f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint32_double_float(i64 %ptr) { define dso_local double @ld_not_disjoint32_double_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_double_float: ; CHECK-LABEL: ld_not_disjoint32_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
Show All 39 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f1, 0(r3) ; CHECK-P10-NEXT: lfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_double_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_double_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-PREP10-NEXT: lfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fpext float %1 to double %conv = fpext float %1 to double
ret double %conv ret double %conv
} }
Show All 33 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fpext float %0 to double %conv = fpext float %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align32_double_float() { define dso_local double @ld_cst_align32_double_float() {
; CHECK-POSTP8-LABEL: ld_cst_align32_double_float: ; CHECK-LABEL: ld_cst_align32_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfs f1, -27108(r3) ; CHECK-NEXT: lfs f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fpext float %0 to double %conv = fpext float %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align64_double_float() { define dso_local double @ld_cst_align64_double_float() {
; CHECK-P10-LABEL: ld_cst_align64_double_float: ; CHECK-P10-LABEL: ld_cst_align64_double_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f1, 0(r3) ; CHECK-P10-NEXT: lfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_double_float: ; CHECK-PREP10-LABEL: ld_cst_align64_double_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-PREP10-NEXT: lfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fpext float %0 to double %conv = fpext float %0 to double
ret double %conv ret double %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_0_double_double(i64 %ptr) { define dso_local double @ld_0_double_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_double_double: ; CHECK-LABEL: ld_0_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f1, 0(r3) ; CHECK-NEXT: lfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_align16_double_double(i8* nocapture readonly %ptr) { define dso_local double @ld_align16_double_double(i8* nocapture readonly %ptr) {
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_or_double_double(i64 %ptr, i8 zeroext %off) { define dso_local double @ld_or_double_double(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_double_double: ; CHECK-LABEL: ld_or_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f1, 0(r3) ; CHECK-NEXT: lfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint16_double_double(i64 %ptr) { define dso_local double @ld_not_disjoint16_double_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_double_double: ; CHECK-LABEL: ld_not_disjoint16_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f1, 0(r3) ; CHECK-NEXT: lfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_disjoint_align16_double_double(i64 %ptr) { define dso_local double @ld_disjoint_align16_double_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_double_double: ; CHECK-LABEL: ld_disjoint_align16_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f1, 24(r3) ; CHECK-NEXT: lfd f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_not_disjoint32_double_double(i64 %ptr) { define dso_local double @ld_not_disjoint32_double_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_double_double: ; CHECK-LABEL: ld_not_disjoint32_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f1, 0(r3) ; CHECK-NEXT: lfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
Show All 37 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f1, 0(r3) ; CHECK-P10-NEXT: lfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_double_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_double_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-PREP10-NEXT: lfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
ret double %1 ret double %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
Show All 30 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
ret double %0 ret double %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align32_double_double() { define dso_local double @ld_cst_align32_double_double() {
; CHECK-POSTP8-LABEL: ld_cst_align32_double_double: ; CHECK-LABEL: ld_cst_align32_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f1, -27108(r3) ; CHECK-NEXT: lfd f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
ret double %0 ret double %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local double @ld_cst_align64_double_double() { define dso_local double @ld_cst_align64_double_double() {
; CHECK-P10-LABEL: ld_cst_align64_double_double: ; CHECK-P10-LABEL: ld_cst_align64_double_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f1, 0(r3) ; CHECK-P10-NEXT: lfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_double_double: ; CHECK-PREP10-LABEL: ld_cst_align64_double_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f1, 0(r3) ; CHECK-PREP10-NEXT: lfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
ret double %0 ret double %0
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_double_uint8_t(i64 %ptr, double %str) { define dso_local void @st_0_double_uint8_t(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_0_double_uint8_t: ; CHECK-POSTP8-LABEL: st_0_double_uint8_t:
▲ Show 20 Lines • Show All 3,195 Lines • ▼ Show 20 Lines
entry: entry:
%conv = fptosi double %str to i64 %conv = fptosi double %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_double_float(i64 %ptr, double %str) { define dso_local void @st_0_double_float(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_0_double_float: ; CHECK-LABEL: st_0_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_0_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_double_float(i64 %ptr, i8 zeroext %off, double %str) { define dso_local void @st_or1_double_float(i64 %ptr, i8 zeroext %off, double %str) {
; CHECK-POSTP8-LABEL: st_or1_double_float: ; CHECK-LABEL: st_or1_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_double_float(i64 %ptr, double %str) { define dso_local void @st_not_disjoint16_double_float(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint16_double_float: ; CHECK-LABEL: st_not_disjoint16_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_double_float(i64 %ptr, double %str) { define dso_local void @st_disjoint_align16_double_float(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_disjoint_align16_double_float: ; CHECK-LABEL: st_disjoint_align16_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint32_double_float(i64 %ptr, double %str) { define dso_local void @st_not_disjoint32_double_float(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint32_double_float: ; CHECK-LABEL: st_not_disjoint32_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint32_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-P8-LABEL: st_not_disjoint64_double_float: ; CHECK-P8-LABEL: st_not_disjoint64_double_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1 ; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: li r4, 29 ; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437 ; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097 ; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4 ; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
Show All 37 Lines
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_double_float(double %str) { define dso_local void @st_cst_align32_double_float(double %str) {
; CHECK-POSTP8-LABEL: st_cst_align32_double_float: ; CHECK-LABEL: st_cst_align32_double_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: xsrsp f0, f1 ; CHECK-NEXT: xsrsp f0, f1
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_double_float(double %str) { define dso_local void @st_cst_align64_double_float(double %str) {
; CHECK-P10-LABEL: st_cst_align64_double_float: ; CHECK-P10-LABEL: st_cst_align64_double_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: xsrsp f0, f1 ; CHECK-P10-NEXT: xsrsp f0, f1
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64_double_float: ; CHECK-PREP10-LABEL: st_cst_align64_double_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: xsrsp f0, f1 ; CHECK-PREP10-NEXT: xsrsp f0, f1
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align64_double_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xsrsp f0, f1
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptrunc double %str to float %conv = fptrunc double %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_double_double(i64 %ptr, double %str) { define dso_local void @st_0_double_double(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_0_double_double: ; CHECK-LABEL: st_0_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_0_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_align16_double_double(i8* nocapture %ptr, double %str) { define dso_local void @st_align16_double_double(i8* nocapture %ptr, double %str) {
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_double_double(i64 %ptr, i8 zeroext %off, double %str) { define dso_local void @st_or1_double_double(i64 %ptr, i8 zeroext %off, double %str) {
; CHECK-POSTP8-LABEL: st_or1_double_double: ; CHECK-LABEL: st_or1_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_double_double(i64 %ptr, double %str) { define dso_local void @st_not_disjoint16_double_double(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint16_double_double: ; CHECK-LABEL: st_not_disjoint16_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_double_double(i64 %ptr, double %str) { define dso_local void @st_disjoint_align16_double_double(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_disjoint_align16_double_double: ; CHECK-LABEL: st_disjoint_align16_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: stfd f1, 24(r3) ; CHECK-NEXT: stfd f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint32_double_double(i64 %ptr, double %str) { define dso_local void @st_not_disjoint32_double_double(i64 %ptr, double %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint32_double_double: ; CHECK-LABEL: st_not_disjoint32_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint32_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
Show All 37 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f1, 0(r3) ; CHECK-P10-NEXT: stfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_double_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_double_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f1, 0(r3) ; CHECK-PREP10-NEXT: stfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %str, double* %0, align 8 store double %str, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
Show All 30 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
store double %str, double* inttoptr (i64 4080 to double*), align 16 store double %str, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_double_double(double %str) { define dso_local void @st_cst_align32_double_double(double %str) {
; CHECK-POSTP8-LABEL: st_cst_align32_double_double: ; CHECK-LABEL: st_cst_align32_double_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: stfd f1, -27108(r3) ; CHECK-NEXT: stfd f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
store double %str, double* inttoptr (i64 9999900 to double*), align 8 store double %str, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_double_double(double %str) { define dso_local void @st_cst_align64_double_double(double %str) {
; CHECK-P10-LABEL: st_cst_align64_double_double: ; CHECK-P10-LABEL: st_cst_align64_double_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stfd f1, 0(r3) ; CHECK-P10-NEXT: stfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64_double_double: ; CHECK-PREP10-LABEL: st_cst_align64_double_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stfd f1, 0(r3) ; CHECK-PREP10-NEXT: stfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align64_double_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
store double %str, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %str, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll

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entry: entry:
%0 = load i32, i32* inttoptr (i64 1000000000000 to i32*), align 4096 %0 = load i32, i32* inttoptr (i64 1000000000000 to i32*), align 4096
%conv = sitofp i32 %0 to float %conv = sitofp i32 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_0_float_uint64_t(i64 %ptr) { define dso_local float @ld_0_float_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_float_uint64_t: ; CHECK-LABEL: ld_0_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to i64* %0 = inttoptr i64 %ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to i64* %0 = bitcast i8* %add.ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_or_float_uint64_t(i64 %ptr, i8 zeroext %off) { define dso_local float @ld_or_float_uint64_t(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_float_uint64_t: ; CHECK-LABEL: ld_or_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv1 = uitofp i64 %1 to float %conv1 = uitofp i64 %1 to float
ret float %conv1 ret float %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint16_float_uint64_t(i64 %ptr) { define dso_local float @ld_not_disjoint16_float_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_float_uint64_t: ; CHECK-LABEL: ld_not_disjoint16_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_disjoint_align16_float_uint64_t(i64 %ptr) { define dso_local float @ld_disjoint_align16_float_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_float_uint64_t: ; CHECK-LABEL: ld_disjoint_align16_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint32_float_uint64_t(i64 %ptr) { define dso_local float @ld_not_disjoint32_float_uint64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_float_uint64_t: ; CHECK-LABEL: ld_not_disjoint32_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
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; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvuxdsp f1, f0 ; CHECK-P10-NEXT: xscvuxdsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_float_uint64_t: ; CHECK-PREP10-LABEL: ld_not_disjoint64_float_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvuxdsp f1, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = uitofp i64 %1 to float %conv = uitofp i64 %1 to float
ret float %conv ret float %conv
} }
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entry: entry:
%0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16 %0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16
%conv = uitofp i64 %0 to float %conv = uitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align32_float_uint64_t() { define dso_local float @ld_cst_align32_float_uint64_t() {
; CHECK-POSTP8-LABEL: ld_cst_align32_float_uint64_t: ; CHECK-LABEL: ld_cst_align32_float_uint64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-POSTP8-NEXT: xscvuxdsp f1, f0 ; CHECK-NEXT: xscvuxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8 %0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8
%conv = uitofp i64 %0 to float %conv = uitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align64_float_uint64_t() { define dso_local float @ld_cst_align64_float_uint64_t() {
; CHECK-P10-LABEL: ld_cst_align64_float_uint64_t: ; CHECK-P10-LABEL: ld_cst_align64_float_uint64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvuxdsp f1, f0 ; CHECK-P10-NEXT: xscvuxdsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_float_uint64_t: ; CHECK-PREP10-LABEL: ld_cst_align64_float_uint64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvuxdsp f1, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_float_uint64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvuxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = uitofp i64 %0 to float %conv = uitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_0_float_int64_t(i64 %ptr) { define dso_local float @ld_0_float_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_float_int64_t: ; CHECK-LABEL: ld_0_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to i64* %0 = inttoptr i64 %ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to i64* %0 = bitcast i8* %add.ptr to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_or_float_int64_t(i64 %ptr, i8 zeroext %off) { define dso_local float @ld_or_float_int64_t(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_float_int64_t: ; CHECK-LABEL: ld_or_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv1 = sitofp i64 %1 to float %conv1 = sitofp i64 %1 to float
ret float %conv1 ret float %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint16_float_int64_t(i64 %ptr) { define dso_local float @ld_not_disjoint16_float_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_float_int64_t: ; CHECK-LABEL: ld_not_disjoint16_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_disjoint_align16_float_int64_t(i64 %ptr) { define dso_local float @ld_disjoint_align16_float_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_float_int64_t: ; CHECK-LABEL: ld_disjoint_align16_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint32_float_int64_t(i64 %ptr) { define dso_local float @ld_not_disjoint32_float_int64_t(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_float_int64_t: ; CHECK-LABEL: ld_not_disjoint32_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvsxdsp f1, f0 ; CHECK-P10-NEXT: xscvsxdsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_float_int64_t: ; CHECK-PREP10-LABEL: ld_not_disjoint64_float_int64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvsxdsp f1, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to i64* %0 = inttoptr i64 %or to i64*
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
%conv = sitofp i64 %1 to float %conv = sitofp i64 %1 to float
ret float %conv ret float %conv
} }
Show All 36 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16 %0 = load i64, i64* inttoptr (i64 4080 to i64*), align 16
%conv = sitofp i64 %0 to float %conv = sitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align32_float_int64_t() { define dso_local float @ld_cst_align32_float_int64_t() {
; CHECK-POSTP8-LABEL: ld_cst_align32_float_int64_t: ; CHECK-LABEL: ld_cst_align32_float_int64_t:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-POSTP8-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8 %0 = load i64, i64* inttoptr (i64 9999900 to i64*), align 8
%conv = sitofp i64 %0 to float %conv = sitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align64_float_int64_t() { define dso_local float @ld_cst_align64_float_int64_t() {
; CHECK-P10-LABEL: ld_cst_align64_float_int64_t: ; CHECK-P10-LABEL: ld_cst_align64_float_int64_t:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvsxdsp f1, f0 ; CHECK-P10-NEXT: xscvsxdsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_float_int64_t: ; CHECK-PREP10-LABEL: ld_cst_align64_float_int64_t:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvsxdsp f1, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_float_int64_t:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvsxdsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = sitofp i64 %0 to float %conv = sitofp i64 %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_0_float_float(i64 %ptr) { define dso_local float @ld_0_float_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_float_float: ; CHECK-LABEL: ld_0_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_align16_float_float(i8* nocapture readonly %ptr) { define dso_local float @ld_align16_float_float(i8* nocapture readonly %ptr) {
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_or_float_float(i64 %ptr, i8 zeroext %off) { define dso_local float @ld_or_float_float(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_float_float: ; CHECK-LABEL: ld_or_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint16_float_float(i64 %ptr) { define dso_local float @ld_not_disjoint16_float_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_float_float: ; CHECK-LABEL: ld_not_disjoint16_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_disjoint_align16_float_float(i64 %ptr) { define dso_local float @ld_disjoint_align16_float_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_float_float: ; CHECK-LABEL: ld_disjoint_align16_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfs f1, 24(r3) ; CHECK-NEXT: lfs f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint32_float_float(i64 %ptr) { define dso_local float @ld_not_disjoint32_float_float(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_float_float: ; CHECK-LABEL: ld_not_disjoint32_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfs f1, 0(r3) ; CHECK-NEXT: lfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
Show All 37 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f1, 0(r3) ; CHECK-P10-NEXT: lfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_float_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_float_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-PREP10-NEXT: lfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
ret float %1 ret float %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
Show All 30 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
ret float %0 ret float %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align32_float_float() { define dso_local float @ld_cst_align32_float_float() {
; CHECK-POSTP8-LABEL: ld_cst_align32_float_float: ; CHECK-LABEL: ld_cst_align32_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfs f1, -27108(r3) ; CHECK-NEXT: lfs f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
ret float %0 ret float %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align64_float_float() { define dso_local float @ld_cst_align64_float_float() {
; CHECK-P10-LABEL: ld_cst_align64_float_float: ; CHECK-P10-LABEL: ld_cst_align64_float_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f1, 0(r3) ; CHECK-P10-NEXT: lfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_float_float: ; CHECK-PREP10-LABEL: ld_cst_align64_float_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f1, 0(r3) ; CHECK-PREP10-NEXT: lfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
ret float %0 ret float %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_0_float_double(i64 %ptr) { define dso_local float @ld_0_float_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_0_float_double: ; CHECK-LABEL: ld_0_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_or_float_double(i64 %ptr, i8 zeroext %off) { define dso_local float @ld_or_float_double(i64 %ptr, i8 zeroext %off) {
; CHECK-POSTP8-LABEL: ld_or_float_double: ; CHECK-LABEL: ld_or_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptrunc double %1 to float %conv1 = fptrunc double %1 to float
ret float %conv1 ret float %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint16_float_double(i64 %ptr) { define dso_local float @ld_not_disjoint16_float_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint16_float_double: ; CHECK-LABEL: ld_not_disjoint16_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_disjoint_align16_float_double(i64 %ptr) { define dso_local float @ld_disjoint_align16_float_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_disjoint_align16_float_double: ; CHECK-LABEL: ld_disjoint_align16_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_not_disjoint32_float_double(i64 %ptr) { define dso_local float @ld_not_disjoint32_float_double(i64 %ptr) {
; CHECK-POSTP8-LABEL: ld_not_disjoint32_float_double: ; CHECK-LABEL: ld_not_disjoint32_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xsrsp f1, f0 ; CHECK-P10-NEXT: xsrsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_float_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_float_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xsrsp f1, f0 ; CHECK-PREP10-NEXT: xsrsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptrunc double %1 to float %conv = fptrunc double %1 to float
ret float %conv ret float %conv
} }
Show All 36 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptrunc double %0 to float %conv = fptrunc double %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align32_float_double() { define dso_local float @ld_cst_align32_float_double() {
; CHECK-POSTP8-LABEL: ld_cst_align32_float_double: ; CHECK-LABEL: ld_cst_align32_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-POSTP8-NEXT: xsrsp f1, f0 ; CHECK-NEXT: xsrsp f1, f0
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptrunc double %0 to float %conv = fptrunc double %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local float @ld_cst_align64_float_double() { define dso_local float @ld_cst_align64_float_double() {
; CHECK-P10-LABEL: ld_cst_align64_float_double: ; CHECK-P10-LABEL: ld_cst_align64_float_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xsrsp f1, f0 ; CHECK-P10-NEXT: xsrsp f1, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_float_double: ; CHECK-PREP10-LABEL: ld_cst_align64_float_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xsrsp f1, f0 ; CHECK-PREP10-NEXT: xsrsp f1, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xsrsp f1, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptrunc double %0 to float %conv = fptrunc double %0 to float
ret float %conv ret float %conv
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_float_uint8_t(i64 %ptr, float %str) { define dso_local void @st_0_float_uint8_t(i64 %ptr, float %str) {
▲ Show 20 Lines • Show All 3,196 Lines • ▼ Show 20 Lines
entry: entry:
%conv = fptosi float %str to i64 %conv = fptosi float %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_float_float(i64 %ptr, float %str) { define dso_local void @st_0_float_float(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_0_float_float: ; CHECK-LABEL: st_0_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: stfs f1, 0(r3) ; CHECK-NEXT: stfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_0_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_align16_float_float(i8* nocapture %ptr, float %str) { define dso_local void @st_align16_float_float(i8* nocapture %ptr, float %str) {
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_float_float(i64 %ptr, i8 zeroext %off, float %str) { define dso_local void @st_or1_float_float(i64 %ptr, i8 zeroext %off, float %str) {
; CHECK-POSTP8-LABEL: st_or1_float_float: ; CHECK-LABEL: st_or1_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: stfs f1, 0(r3) ; CHECK-NEXT: stfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_float_float(i64 %ptr, float %str) { define dso_local void @st_not_disjoint16_float_float(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint16_float_float: ; CHECK-LABEL: st_not_disjoint16_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: stfs f1, 0(r3) ; CHECK-NEXT: stfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_float_float(i64 %ptr, float %str) { define dso_local void @st_disjoint_align16_float_float(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_disjoint_align16_float_float: ; CHECK-LABEL: st_disjoint_align16_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: stfs f1, 24(r3) ; CHECK-NEXT: stfs f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %str, float* %0, align 8 store float %str, float* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint32_float_float(i64 %ptr, float %str) { define dso_local void @st_not_disjoint32_float_float(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint32_float_float: ; CHECK-LABEL: st_not_disjoint32_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: stfs f1, 0(r3) ; CHECK-NEXT: stfs f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint32_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
Show All 37 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f1, 0(r3) ; CHECK-P10-NEXT: stfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_float_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_float_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f1, 0(r3) ; CHECK-PREP10-NEXT: stfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %str, float* %0, align 4 store float %str, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
Show All 30 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
store float %str, float* inttoptr (i64 4080 to float*), align 16 store float %str, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_float_float(float %str) { define dso_local void @st_cst_align32_float_float(float %str) {
; CHECK-POSTP8-LABEL: st_cst_align32_float_float: ; CHECK-LABEL: st_cst_align32_float_float:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: stfs f1, -27108(r3) ; CHECK-NEXT: stfs f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
store float %str, float* inttoptr (i64 9999900 to float*), align 4 store float %str, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_float_float(float %str) { define dso_local void @st_cst_align64_float_float(float %str) {
; CHECK-P10-LABEL: st_cst_align64_float_float: ; CHECK-P10-LABEL: st_cst_align64_float_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stfs f1, 0(r3) ; CHECK-P10-NEXT: stfs f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64_float_float: ; CHECK-PREP10-LABEL: st_cst_align64_float_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stfs f1, 0(r3) ; CHECK-PREP10-NEXT: stfs f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align64_float_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
store float %str, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %str, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_float_double(i64 %ptr, float %str) { define dso_local void @st_0_float_double(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_0_float_double: ; CHECK-LABEL: st_0_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_0_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_float_double(i64 %ptr, i8 zeroext %off, float %str) { define dso_local void @st_or1_float_double(i64 %ptr, i8 zeroext %off, float %str) {
; CHECK-POSTP8-LABEL: st_or1_float_double: ; CHECK-LABEL: st_or1_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_float_double(i64 %ptr, float %str) { define dso_local void @st_not_disjoint16_float_double(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint16_float_double: ; CHECK-LABEL: st_not_disjoint16_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_float_double(i64 %ptr, float %str) { define dso_local void @st_disjoint_align16_float_double(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_disjoint_align16_float_double: ; CHECK-LABEL: st_disjoint_align16_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-POSTP8-NEXT: stfd f1, 24(r3) ; CHECK-NEXT: stfd f1, 24(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = fpext float %str to double %conv = fpext float %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint32_float_double(i64 %ptr, float %str) { define dso_local void @st_not_disjoint32_float_double(i64 %ptr, float %str) {
; CHECK-POSTP8-LABEL: st_not_disjoint32_float_double: ; CHECK-LABEL: st_not_disjoint32_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-POSTP8-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-POSTP8-NEXT: stfd f1, 0(r3) ; CHECK-NEXT: stfd f1, 0(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint32_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 39 Lines
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f1, 0(r3) ; CHECK-P10-NEXT: stfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_float_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_float_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f1, 0(r3) ; CHECK-PREP10-NEXT: stfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 33 Lines
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_float_double(float %str) { define dso_local void @st_cst_align32_float_double(float %str) {
; CHECK-POSTP8-LABEL: st_cst_align32_float_double: ; CHECK-LABEL: st_cst_align32_float_double:
; CHECK-POSTP8: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-POSTP8-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-POSTP8-NEXT: stfd f1, -27108(r3) ; CHECK-NEXT: stfd f1, -27108(r3)
; CHECK-POSTP8-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_float_double(float %str) { define dso_local void @st_cst_align64_float_double(float %str) {
; CHECK-P10-LABEL: st_cst_align64_float_double: ; CHECK-P10-LABEL: st_cst_align64_float_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stfd f1, 0(r3) ; CHECK-P10-NEXT: stfd f1, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64_float_double: ; CHECK-PREP10-LABEL: st_cst_align64_float_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stfd f1, 0(r3) ; CHECK-PREP10-NEXT: stfd f1, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align64_float_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f1, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = fpext float %str to double %conv = fpext float %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,669 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = trunc i64 %0 to i16 %conv = trunc i64 %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_0_int16_t_float(i64 %ptr) { define dso_local signext i16 @ld_0_int16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int16_t_float: ; CHECK-LABEL: ld_0_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_or_int16_t_float(i64 %ptr, i8 zeroext %off) { define dso_local signext i16 @ld_or_int16_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int16_t_float: ; CHECK-LABEL: ld_or_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptosi float %1 to i16 %conv1 = fptosi float %1 to i16
ret i16 %conv1 ret i16 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_not_disjoint16_int16_t_float(i64 %ptr) { define dso_local signext i16 @ld_not_disjoint16_int16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int16_t_float: ; CHECK-LABEL: ld_not_disjoint16_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_disjoint_align16_int16_t_float(i64 %ptr) { define dso_local signext i16 @ld_disjoint_align16_int16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int16_t_float: ; CHECK-LABEL: ld_disjoint_align16_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_not_disjoint32_int16_t_float(i64 %ptr) { define dso_local signext i16 @ld_not_disjoint32_int16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int16_t_float: ; CHECK-LABEL: ld_not_disjoint32_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int16_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i16 %conv = fptosi float %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptosi float %0 to i16 %conv = fptosi float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_cst_align32_int16_t_float() { define dso_local signext i16 @ld_cst_align32_int16_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_int16_t_float: ; CHECK-LABEL: ld_cst_align32_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptosi float %0 to i16 %conv = fptosi float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_cst_align64_int16_t_float() { define dso_local signext i16 @ld_cst_align64_int16_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_int16_t_float: ; CHECK-P10-LABEL: ld_cst_align64_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int16_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptosi float %0 to i16 %conv = fptosi float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_0_int16_t_double(i64 %ptr) { define dso_local signext i16 @ld_0_int16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int16_t_double: ; CHECK-LABEL: ld_0_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_or_int16_t_double(i64 %ptr, i8 zeroext %off) { define dso_local signext i16 @ld_or_int16_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int16_t_double: ; CHECK-LABEL: ld_or_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptosi double %1 to i16 %conv1 = fptosi double %1 to i16
ret i16 %conv1 ret i16 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_not_disjoint16_int16_t_double(i64 %ptr) { define dso_local signext i16 @ld_not_disjoint16_int16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int16_t_double: ; CHECK-LABEL: ld_not_disjoint16_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_disjoint_align16_int16_t_double(i64 %ptr) { define dso_local signext i16 @ld_disjoint_align16_int16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int16_t_double: ; CHECK-LABEL: ld_disjoint_align16_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_not_disjoint32_int16_t_double(i64 %ptr) { define dso_local signext i16 @ld_not_disjoint32_int16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int16_t_double: ; CHECK-LABEL: ld_not_disjoint32_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int16_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i16 %conv = fptosi double %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptosi double %0 to i16 %conv = fptosi double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_cst_align32_int16_t_double() { define dso_local signext i16 @ld_cst_align32_int16_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_int16_t_double: ; CHECK-LABEL: ld_cst_align32_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptosi double %0 to i16 %conv = fptosi double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i16 @ld_cst_align64_int16_t_double() { define dso_local signext i16 @ld_cst_align64_int16_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_int16_t_double: ; CHECK-P10-LABEL: ld_cst_align64_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int16_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptosi double %0 to i16 %conv = fptosi double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) { define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) {
▲ Show 20 Lines • Show All 2,045 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i16 %conv = fptoui float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_or_uint16_t_float(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i16 @ld_or_uint16_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint16_t_float: ; CHECK-LABEL: ld_or_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptoui float %1 to i16 %conv1 = fptoui float %1 to i16
ret i16 %conv1 ret i16 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_float(i64 %ptr) { define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint16_t_float: ; CHECK-LABEL: ld_not_disjoint16_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i16 %conv = fptoui float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_float(i64 %ptr) { define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint16_t_float: ; CHECK-LABEL: ld_disjoint_align16_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptoui float %1 to i16 %conv = fptoui float %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_float(i64 %ptr) { define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint16_t_float: ; CHECK-LABEL: ld_not_disjoint32_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i16 %conv = fptoui float %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint16_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i16 %conv = fptoui float %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_cst_align32_uint16_t_float() { define dso_local zeroext i16 @ld_cst_align32_uint16_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_uint16_t_float: ; CHECK-LABEL: ld_cst_align32_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_cst_align64_uint16_t_float() { define dso_local zeroext i16 @ld_cst_align64_uint16_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_uint16_t_float: ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint16_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_0_uint16_t_double(i64 %ptr) { define dso_local zeroext i16 @ld_0_uint16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint16_t_double: ; CHECK-LABEL: ld_0_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_or_uint16_t_double(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i16 @ld_or_uint16_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint16_t_double: ; CHECK-LABEL: ld_or_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptoui double %1 to i16 %conv1 = fptoui double %1 to i16
ret i16 %conv1 ret i16 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_double(i64 %ptr) { define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint16_t_double: ; CHECK-LABEL: ld_not_disjoint16_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_double(i64 %ptr) { define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint16_t_double: ; CHECK-LABEL: ld_disjoint_align16_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_double(i64 %ptr) { define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint16_t_double: ; CHECK-LABEL: ld_not_disjoint32_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint16_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i16 %conv = fptoui double %1 to i16
ret i16 %conv ret i16 %conv
} }
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entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_cst_align32_uint16_t_double() { define dso_local zeroext i16 @ld_cst_align32_uint16_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_uint16_t_double: ; CHECK-LABEL: ld_cst_align32_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i16 @ld_cst_align64_uint16_t_double() { define dso_local zeroext i16 @ld_cst_align64_uint16_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_uint16_t_double: ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint16_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
ret i16 %conv ret i16 %conv
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint16_t_uint8_t(i64 %ptr, i16 zeroext %str) { define dso_local void @st_0_uint16_t_uint8_t(i64 %ptr, i16 zeroext %str) {
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entry: entry:
%conv = zext i16 %str to i64 %conv = zext i16 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint16_t_float(i64 %ptr, i16 zeroext %str) { define dso_local void @st_0_uint16_t_float(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint16_t_float: ; CHECK-LABEL: st_0_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint16_t_float(i64 %ptr, i8 zeroext %off, i16 zeroext %str) { define dso_local void @st_or1_uint16_t_float(i64 %ptr, i8 zeroext %off, i16 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint16_t_float: ; CHECK-LABEL: st_or1_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint16_t_float(i64 %ptr, i16 zeroext %str) { define dso_local void @st_not_disjoint16_uint16_t_float(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint16_t_float: ; CHECK-LABEL: st_not_disjoint16_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint16_t_float(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align16_uint16_t_float(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint16_t_float: ; CHECK-LABEL: st_disjoint_align16_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint16_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
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; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-P10-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint16_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
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entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint16_t_float(i16 zeroext %str) { define dso_local void @st_cst_align32_uint16_t_float(i16 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint16_t_float: ; CHECK-LABEL: st_cst_align32_uint16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint16_t_float(i16 zeroext %str) { define dso_local void @st_cst_align64_uint16_t_float(i16 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint16_t_float: ; CHECK-P8-LABEL: st_cst_align64_uint16_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to float %conv = uitofp i16 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint16_t_double(i64 %ptr, i16 zeroext %str) { define dso_local void @st_0_uint16_t_double(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint16_t_double: ; CHECK-LABEL: st_0_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint16_t_double(i64 %ptr, i8 zeroext %off, i16 zeroext %str) { define dso_local void @st_or1_uint16_t_double(i64 %ptr, i8 zeroext %off, i16 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint16_t_double: ; CHECK-LABEL: st_or1_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint16_t_double(i64 %ptr, i16 zeroext %str) { define dso_local void @st_not_disjoint16_uint16_t_double(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint16_t_double: ; CHECK-LABEL: st_not_disjoint16_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint16_t_double(i64 %ptr, i16 zeroext %str) { define dso_local void @st_disjoint_align16_uint16_t_double(i64 %ptr, i16 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint16_t_double: ; CHECK-LABEL: st_disjoint_align16_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint16_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-P10-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint16_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxddp f0, f0 ; CHECK-PREP10-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint16_t_double(i16 zeroext %str) { define dso_local void @st_cst_align32_uint16_t_double(i16 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint16_t_double: ; CHECK-LABEL: st_cst_align32_uint16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint16_t_double(i16 zeroext %str) { define dso_local void @st_cst_align64_uint16_t_double(i16 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint16_t_double: ; CHECK-P8-LABEL: st_cst_align64_uint16_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i16 %str to double %conv = uitofp i16 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 569 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sext i16 %str to i64 %conv = sext i16 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int16_t_float(i64 %ptr, i16 signext %str) { define dso_local void @st_0_int16_t_float(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_0_int16_t_float: ; CHECK-LABEL: st_0_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int16_t_float(i64 %ptr, i8 zeroext %off, i16 signext %str) { define dso_local void @st_or1_int16_t_float(i64 %ptr, i8 zeroext %off, i16 signext %str) {
; CHECK-P10-LABEL: st_or1_int16_t_float: ; CHECK-LABEL: st_or1_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int16_t_float(i64 %ptr, i16 signext %str) { define dso_local void @st_not_disjoint16_int16_t_float(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int16_t_float: ; CHECK-LABEL: st_not_disjoint16_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int16_t_float(i64 %ptr, i16 signext %str) { define dso_local void @st_disjoint_align16_int16_t_float(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int16_t_float: ; CHECK-LABEL: st_disjoint_align16_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int16_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_int16_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-P10-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int16_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_int16_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int16_t_float(i16 signext %str) { define dso_local void @st_cst_align32_int16_t_float(i16 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int16_t_float: ; CHECK-LABEL: st_cst_align32_int16_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int16_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int16_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int16_t_float(i16 signext %str) { define dso_local void @st_cst_align64_int16_t_float(i16 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int16_t_float: ; CHECK-P8-LABEL: st_cst_align64_int16_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to float %conv = sitofp i16 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int16_t_double(i64 %ptr, i16 signext %str) { define dso_local void @st_0_int16_t_double(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_0_int16_t_double: ; CHECK-LABEL: st_0_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int16_t_double(i64 %ptr, i8 zeroext %off, i16 signext %str) { define dso_local void @st_or1_int16_t_double(i64 %ptr, i8 zeroext %off, i16 signext %str) {
; CHECK-P10-LABEL: st_or1_int16_t_double: ; CHECK-LABEL: st_or1_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int16_t_double(i64 %ptr, i16 signext %str) { define dso_local void @st_not_disjoint16_int16_t_double(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int16_t_double: ; CHECK-LABEL: st_not_disjoint16_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int16_t_double(i64 %ptr, i16 signext %str) { define dso_local void @st_disjoint_align16_int16_t_double(i64 %ptr, i16 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int16_t_double: ; CHECK-LABEL: st_disjoint_align16_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int16_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_int16_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-P10-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int16_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_int16_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxddp f0, f0 ; CHECK-PREP10-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int16_t_double(i16 signext %str) { define dso_local void @st_cst_align32_int16_t_double(i16 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int16_t_double: ; CHECK-LABEL: st_cst_align32_int16_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int16_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int16_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int16_t_double(i16 signext %str) { define dso_local void @st_cst_align64_int16_t_double(i16 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int16_t_double: ; CHECK-P8-LABEL: st_cst_align64_int16_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i16 %str to double %conv = sitofp i16 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,597 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = trunc i64 %0 to i32 %conv = trunc i64 %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_0_int32_t_float(i64 %ptr) { define dso_local signext i32 @ld_0_int32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int32_t_float: ; CHECK-LABEL: ld_0_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_or_int32_t_float(i64 %ptr, i8 zeroext %off) { define dso_local signext i32 @ld_or_int32_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int32_t_float: ; CHECK-LABEL: ld_or_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptosi float %1 to i32 %conv1 = fptosi float %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
Show All 15 Linesentry:
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptosi float %1 to i32 %conv1 = fptosi float %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_not_disjoint16_int32_t_float(i64 %ptr) { define dso_local signext i32 @ld_not_disjoint16_int32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int32_t_float: ; CHECK-LABEL: ld_not_disjoint16_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_disjoint_align16_int32_t_float(i64 %ptr) { define dso_local signext i32 @ld_disjoint_align16_int32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int32_t_float: ; CHECK-LABEL: ld_disjoint_align16_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_not_disjoint32_int32_t_float(i64 %ptr) { define dso_local signext i32 @ld_not_disjoint32_int32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int32_t_float: ; CHECK-LABEL: ld_not_disjoint32_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int32_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i32 %conv = fptosi float %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_cst_align32_int32_t_float() { define dso_local signext i32 @ld_cst_align32_int32_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_int32_t_float: ; CHECK-LABEL: ld_cst_align32_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_cst_align64_int32_t_float() { define dso_local signext i32 @ld_cst_align64_int32_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_int32_t_float: ; CHECK-P10-LABEL: ld_cst_align64_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int32_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_0_int32_t_double(i64 %ptr) { define dso_local signext i32 @ld_0_int32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int32_t_double: ; CHECK-LABEL: ld_0_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_or_int32_t_double(i64 %ptr, i8 zeroext %off) { define dso_local signext i32 @ld_or_int32_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int32_t_double: ; CHECK-LABEL: ld_or_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptosi double %1 to i32 %conv1 = fptosi double %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
Show All 15 Linesentry:
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptosi double %1 to i32 %conv1 = fptosi double %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_not_disjoint16_int32_t_double(i64 %ptr) { define dso_local signext i32 @ld_not_disjoint16_int32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int32_t_double: ; CHECK-LABEL: ld_not_disjoint16_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_disjoint_align16_int32_t_double(i64 %ptr) { define dso_local signext i32 @ld_disjoint_align16_int32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int32_t_double: ; CHECK-LABEL: ld_disjoint_align16_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_not_disjoint32_int32_t_double(i64 %ptr) { define dso_local signext i32 @ld_not_disjoint32_int32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int32_t_double: ; CHECK-LABEL: ld_not_disjoint32_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int32_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i32 %conv = fptosi double %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_cst_align32_int32_t_double() { define dso_local signext i32 @ld_cst_align32_int32_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_int32_t_double: ; CHECK-LABEL: ld_cst_align32_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i32 @ld_cst_align64_int32_t_double() { define dso_local signext i32 @ld_cst_align64_int32_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_int32_t_double: ; CHECK-P10-LABEL: ld_cst_align64_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int32_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) { define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) {
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entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = trunc i64 %0 to i32 %conv = trunc i64 %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_0_uint32_t_float(i64 %ptr) { define dso_local zeroext i32 @ld_0_uint32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint32_t_float: ; CHECK-LABEL: ld_0_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_or_uint32_t_float(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i32 @ld_or_uint32_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint32_t_float: ; CHECK-LABEL: ld_or_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptoui float %1 to i32 %conv1 = fptoui float %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_float(i64 %ptr) { define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint32_t_float: ; CHECK-LABEL: ld_not_disjoint16_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_float(i64 %ptr) { define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint32_t_float: ; CHECK-LABEL: ld_disjoint_align16_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_float(i64 %ptr) { define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint32_t_float: ; CHECK-LABEL: ld_not_disjoint32_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
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; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint32_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i32 %conv = fptoui float %1 to i32
ret i32 %conv ret i32 %conv
} }
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entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_cst_align32_uint32_t_float() { define dso_local zeroext i32 @ld_cst_align32_uint32_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_uint32_t_float: ; CHECK-LABEL: ld_cst_align32_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_cst_align64_uint32_t_float() { define dso_local zeroext i32 @ld_cst_align64_uint32_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_uint32_t_float: ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint32_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_0_uint32_t_double(i64 %ptr) { define dso_local zeroext i32 @ld_0_uint32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint32_t_double: ; CHECK-LABEL: ld_0_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_or_uint32_t_double(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i32 @ld_or_uint32_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint32_t_double: ; CHECK-LABEL: ld_or_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptoui double %1 to i32 %conv1 = fptoui double %1 to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_double(i64 %ptr) { define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint32_t_double: ; CHECK-LABEL: ld_not_disjoint16_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_double(i64 %ptr) { define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint32_t_double: ; CHECK-LABEL: ld_disjoint_align16_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_double(i64 %ptr) { define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint32_t_double: ; CHECK-LABEL: ld_not_disjoint32_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint32_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i32 %conv = fptoui double %1 to i32
ret i32 %conv ret i32 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_cst_align32_uint32_t_double() { define dso_local zeroext i32 @ld_cst_align32_uint32_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_uint32_t_double: ; CHECK-LABEL: ld_cst_align32_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i32 @ld_cst_align64_uint32_t_double() { define dso_local zeroext i32 @ld_cst_align64_uint32_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_uint32_t_double: ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0 ; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint32_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint32_t_uint8_t(i64 %ptr, i32 zeroext %str) { define dso_local void @st_0_uint32_t_uint8_t(i64 %ptr, i32 zeroext %str) {
▲ Show 20 Lines • Show All 1,125 Lines • ▼ Show 20 Lines
entry: entry:
%conv = zext i32 %str to i64 %conv = zext i32 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint32_t_float(i64 %ptr, i32 zeroext %str) { define dso_local void @st_0_uint32_t_float(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint32_t_float: ; CHECK-LABEL: st_0_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint32_t_float(i64 %ptr, i8 zeroext %off, i32 zeroext %str) { define dso_local void @st_or1_uint32_t_float(i64 %ptr, i8 zeroext %off, i32 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint32_t_float: ; CHECK-LABEL: st_or1_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint32_t_float(i64 %ptr, i32 zeroext %str) { define dso_local void @st_not_disjoint16_uint32_t_float(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint32_t_float: ; CHECK-LABEL: st_not_disjoint16_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint32_t_float(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align16_uint32_t_float(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint32_t_float: ; CHECK-LABEL: st_disjoint_align16_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint32_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-P10-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint32_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint32_t_float(i32 zeroext %str) { define dso_local void @st_cst_align32_uint32_t_float(i32 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint32_t_float: ; CHECK-LABEL: st_cst_align32_uint32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint32_t_float(i32 zeroext %str) { define dso_local void @st_cst_align64_uint32_t_float(i32 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint32_t_float: ; CHECK-P8-LABEL: st_cst_align64_uint32_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to float %conv = uitofp i32 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint32_t_double(i64 %ptr, i32 zeroext %str) { define dso_local void @st_0_uint32_t_double(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint32_t_double: ; CHECK-LABEL: st_0_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint32_t_double(i64 %ptr, i8 zeroext %off, i32 zeroext %str) { define dso_local void @st_or1_uint32_t_double(i64 %ptr, i8 zeroext %off, i32 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint32_t_double: ; CHECK-LABEL: st_or1_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint32_t_double(i64 %ptr, i32 zeroext %str) { define dso_local void @st_not_disjoint16_uint32_t_double(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint32_t_double: ; CHECK-LABEL: st_not_disjoint16_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint32_t_double(i64 %ptr, i32 zeroext %str) { define dso_local void @st_disjoint_align16_uint32_t_double(i64 %ptr, i32 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint32_t_double: ; CHECK-LABEL: st_disjoint_align16_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint32_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-P10-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint32_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxddp f0, f0 ; CHECK-PREP10-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint32_t_double(i32 zeroext %str) { define dso_local void @st_cst_align32_uint32_t_double(i32 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint32_t_double: ; CHECK-LABEL: st_cst_align32_uint32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint32_t_double(i32 zeroext %str) { define dso_local void @st_cst_align64_uint32_t_double(i32 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint32_t_double: ; CHECK-P8-LABEL: st_cst_align64_uint32_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i32 %str to double %conv = uitofp i32 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
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entry: entry:
%conv = sext i32 %str to i64 %conv = sext i32 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int32_t_float(i64 %ptr, i32 signext %str) { define dso_local void @st_0_int32_t_float(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_0_int32_t_float: ; CHECK-LABEL: st_0_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int32_t_float(i64 %ptr, i8 zeroext %off, i32 signext %str) { define dso_local void @st_or1_int32_t_float(i64 %ptr, i8 zeroext %off, i32 signext %str) {
; CHECK-P10-LABEL: st_or1_int32_t_float: ; CHECK-LABEL: st_or1_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int32_t_float(i64 %ptr, i32 signext %str) { define dso_local void @st_not_disjoint16_int32_t_float(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int32_t_float: ; CHECK-LABEL: st_not_disjoint16_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int32_t_float(i64 %ptr, i32 signext %str) { define dso_local void @st_disjoint_align16_int32_t_float(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int32_t_float: ; CHECK-LABEL: st_disjoint_align16_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int32_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_int32_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-P10-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int32_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_int32_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int32_t_float(i32 signext %str) { define dso_local void @st_cst_align32_int32_t_float(i32 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int32_t_float: ; CHECK-LABEL: st_cst_align32_int32_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int32_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int32_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int32_t_float(i32 signext %str) { define dso_local void @st_cst_align64_int32_t_float(i32 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int32_t_float: ; CHECK-P8-LABEL: st_cst_align64_int32_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to float %conv = sitofp i32 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int32_t_double(i64 %ptr, i32 signext %str) { define dso_local void @st_0_int32_t_double(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_0_int32_t_double: ; CHECK-LABEL: st_0_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int32_t_double(i64 %ptr, i8 zeroext %off, i32 signext %str) { define dso_local void @st_or1_int32_t_double(i64 %ptr, i8 zeroext %off, i32 signext %str) {
; CHECK-P10-LABEL: st_or1_int32_t_double: ; CHECK-LABEL: st_or1_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int32_t_double(i64 %ptr, i32 signext %str) { define dso_local void @st_not_disjoint16_int32_t_double(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int32_t_double: ; CHECK-LABEL: st_not_disjoint16_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int32_t_double(i64 %ptr, i32 signext %str) { define dso_local void @st_disjoint_align16_int32_t_double(i64 %ptr, i32 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int32_t_double: ; CHECK-LABEL: st_disjoint_align16_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int32_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_int32_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-P10-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int32_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_int32_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxddp f0, f0 ; CHECK-PREP10-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int32_t_double(i32 signext %str) { define dso_local void @st_cst_align32_int32_t_double(i32 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int32_t_double: ; CHECK-LABEL: st_cst_align32_int32_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int32_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int32_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int32_t_double(i32 signext %str) { define dso_local void @st_cst_align64_int32_t_double(i32 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int32_t_double: ; CHECK-P8-LABEL: st_cst_align64_int32_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i32 %str to double %conv = sitofp i32 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 14 Lines
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8 ; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_0_int64_t_float(i64 %ptr) { define dso_local i64 @ld_0_int64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int64_t_float: ; CHECK-LABEL: ld_0_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_or_int64_t_float(i64 %ptr, i8 zeroext %off) { define dso_local i64 @ld_or_int64_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int64_t_float: ; CHECK-LABEL: ld_or_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptosi float %1 to i64 %conv1 = fptosi float %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint16_int64_t_float(i64 %ptr) { define dso_local i64 @ld_not_disjoint16_int64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int64_t_float: ; CHECK-LABEL: ld_not_disjoint16_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_align16_int64_t_float(i64 %ptr) { define dso_local i64 @ld_disjoint_align16_int64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int64_t_float: ; CHECK-LABEL: ld_disjoint_align16_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint32_int64_t_float(i64 %ptr) { define dso_local i64 @ld_not_disjoint32_int64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int64_t_float: ; CHECK-LABEL: ld_not_disjoint32_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-P10-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int64_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i64 %conv = fptosi float %1 to i64
ret i64 %conv ret i64 %conv
} }
Show All 39 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align32_int64_t_float() { define dso_local i64 @ld_cst_align32_int64_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_int64_t_float: ; CHECK-LABEL: ld_cst_align32_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align64_int64_t_float() { define dso_local i64 @ld_cst_align64_int64_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_int64_t_float: ; CHECK-P10-LABEL: ld_cst_align64_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-P10-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int64_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_0_int64_t_double(i64 %ptr) { define dso_local i64 @ld_0_int64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int64_t_double: ; CHECK-LABEL: ld_0_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_or_int64_t_double(i64 %ptr, i8 zeroext %off) { define dso_local i64 @ld_or_int64_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int64_t_double: ; CHECK-LABEL: ld_or_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptosi double %1 to i64 %conv1 = fptosi double %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint16_int64_t_double(i64 %ptr) { define dso_local i64 @ld_not_disjoint16_int64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int64_t_double: ; CHECK-LABEL: ld_not_disjoint16_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_align16_int64_t_double(i64 %ptr) { define dso_local i64 @ld_disjoint_align16_int64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int64_t_double: ; CHECK-LABEL: ld_disjoint_align16_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint32_int64_t_double(i64 %ptr) { define dso_local i64 @ld_not_disjoint32_int64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int64_t_double: ; CHECK-LABEL: ld_not_disjoint32_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
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; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-P10-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int64_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i64 %conv = fptosi double %1 to i64
ret i64 %conv ret i64 %conv
} }
Show All 39 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptosi double %0 to i64 %conv = fptosi double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align32_int64_t_double() { define dso_local i64 @ld_cst_align32_int64_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_int64_t_double: ; CHECK-LABEL: ld_cst_align32_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptosi double %0 to i64 %conv = fptosi double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align64_int64_t_double() { define dso_local i64 @ld_cst_align64_int64_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_int64_t_double: ; CHECK-P10-LABEL: ld_cst_align64_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxds f0, f0 ; CHECK-P10-NEXT: xscvdpsxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int64_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptosi double %0 to i64 %conv = fptosi double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) { define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) {
▲ Show 20 Lines • Show All 3,440 Lines • ▼ Show 20 Lines
; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret i64 %0 ret i64 %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_0_uint64_t_float(i64 %ptr) { define dso_local i64 @ld_0_uint64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint64_t_float: ; CHECK-LABEL: ld_0_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_or_uint64_t_float(i64 %ptr, i8 zeroext %off) { define dso_local i64 @ld_or_uint64_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint64_t_float: ; CHECK-LABEL: ld_or_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptoui float %1 to i64 %conv1 = fptoui float %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 14 Linesentry:
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptoui float %1 to i64 %conv1 = fptoui float %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint16_uint64_t_float(i64 %ptr) { define dso_local i64 @ld_not_disjoint16_uint64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint64_t_float: ; CHECK-LABEL: ld_not_disjoint16_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_unalign16_uint64_t_float(i64 %ptr) { define dso_local i64 @ld_disjoint_unalign16_uint64_t_float(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_unalign16_uint64_t_float: ; CHECK-LABEL: ld_disjoint_unalign16_uint64_t_float:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lfs f0, 6(r3)
; CHECK-NEXT: lfsx f0, 0, r3
; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_align16_uint64_t_float(i64 %ptr) { define dso_local i64 @ld_disjoint_align16_uint64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint64_t_float: ; CHECK-LABEL: ld_disjoint_align16_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint32_uint64_t_float(i64 %ptr) { define dso_local i64 @ld_not_disjoint32_uint64_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint64_t_float: ; CHECK-LABEL: ld_not_disjoint32_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint64_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i64 %conv = fptoui float %1 to i64
ret i64 %conv ret i64 %conv
} }
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: ld_cst_unalign32_uint64_t_float: ; CHECK-P8-LABEL: ld_cst_unalign32_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 1 ; CHECK-P8-NEXT: lis r3, 2
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: lfs f0, -31073(r3)
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0 ; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 99999 to float*), align 4 %0 = load float, float* inttoptr (i64 99999 to float*), align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align32_uint64_t_float() { define dso_local i64 @ld_cst_align32_uint64_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_uint64_t_float: ; CHECK-LABEL: ld_cst_align32_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_unalign64_uint64_t_float() { define dso_local i64 @ld_cst_unalign64_uint64_t_float() {
; CHECK-P10-LABEL: ld_cst_unalign64_uint64_t_float: ; CHECK-P10-LABEL: ld_cst_unalign64_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lfs f0, 0(r4) ; CHECK-P10-NEXT: lfs f0, 0(r4)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64_uint64_t_float: ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign64_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r3, 29
; CHECK-P8-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-NEXT: oris r3, r3, 54437
; CHECK-P8-NEXT: ori r3, r3, 4097
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4 %0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align64_uint64_t_float() { define dso_local i64 @ld_cst_align64_uint64_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_uint64_t_float: ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint64_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_0_uint64_t_double(i64 %ptr) { define dso_local i64 @ld_0_uint64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint64_t_double: ; CHECK-LABEL: ld_0_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_or_uint64_t_double(i64 %ptr, i8 zeroext %off) { define dso_local i64 @ld_or_uint64_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint64_t_double: ; CHECK-LABEL: ld_or_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptoui double %1 to i64 %conv1 = fptoui double %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 14 Linesentry:
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptoui double %1 to i64 %conv1 = fptoui double %1 to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint16_uint64_t_double(i64 %ptr) { define dso_local i64 @ld_not_disjoint16_uint64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint64_t_double: ; CHECK-LABEL: ld_not_disjoint16_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_unalign16_uint64_t_double(i64 %ptr) { define dso_local i64 @ld_disjoint_unalign16_uint64_t_double(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_unalign16_uint64_t_double: ; CHECK-LABEL: ld_disjoint_unalign16_uint64_t_double:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lfd f0, 6(r3)
; CHECK-NEXT: lfdx f0, 0, r3
; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 6 %or = or i64 %and, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_disjoint_align16_uint64_t_double(i64 %ptr) { define dso_local i64 @ld_disjoint_align16_uint64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint64_t_double: ; CHECK-LABEL: ld_disjoint_align16_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_not_disjoint32_uint64_t_double(i64 %ptr) { define dso_local i64 @ld_not_disjoint32_uint64_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint64_t_double: ; CHECK-LABEL: ld_not_disjoint32_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
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; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint64_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i64 %conv = fptoui double %1 to i64
ret i64 %conv ret i64 %conv
} }
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; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: ld_cst_unalign32_uint64_t_double: ; CHECK-P8-LABEL: ld_cst_unalign32_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 1 ; CHECK-P8-NEXT: lis r3, 2
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: lfd f0, -31073(r3)
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0 ; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 99999 to double*), align 8 %0 = load double, double* inttoptr (i64 99999 to double*), align 8
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align32_uint64_t_double() { define dso_local i64 @ld_cst_align32_uint64_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_uint64_t_double: ; CHECK-LABEL: ld_cst_align32_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_unalign64_uint64_t_double() { define dso_local i64 @ld_cst_unalign64_uint64_t_double() {
; CHECK-P10-LABEL: ld_cst_unalign64_uint64_t_double: ; CHECK-P10-LABEL: ld_cst_unalign64_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lfd f0, 0(r4) ; CHECK-P10-NEXT: lfd f0, 0(r4)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64_uint64_t_double: ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign64_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r3, 29
; CHECK-P8-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-NEXT: oris r3, r3, 54437
; CHECK-P8-NEXT: ori r3, r3, 4097
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8 %0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local i64 @ld_cst_align64_uint64_t_double() { define dso_local i64 @ld_cst_align64_uint64_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_uint64_t_double: ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxds f0, f0 ; CHECK-P10-NEXT: xscvdpuxds f0, f0
; CHECK-P10-NEXT: mffprd r3, f0 ; CHECK-P10-NEXT: mffprd r3, f0
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint64_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpuxds f0, f0 ; CHECK-PREP10-NEXT: xscvdpuxds f0, f0
; CHECK-P9-NEXT: mffprd r3, f0 ; CHECK-PREP10-NEXT: mffprd r3, f0
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpuxds f0, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
ret i64 %conv ret i64 %conv
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint64_t_uint8_t(i64 %ptr, i64 %str) { define dso_local void @st_0_uint64_t_uint8_t(i64 %ptr, i64 %str) {
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; CHECK-PREP10-NEXT: blr ; CHECK-PREP10-NEXT: blr
entry: entry:
store i64 %str, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %str, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_0_uint64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_0_uint64_t_float: ; CHECK-LABEL: st_0_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint64_t_float(i64 %ptr, i8 zeroext %off, i64 %str) { define dso_local void @st_or1_uint64_t_float(i64 %ptr, i8 zeroext %off, i64 %str) {
; CHECK-P10-LABEL: st_or1_uint64_t_float: ; CHECK-LABEL: st_or1_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
Show All 14 Linesentry:
%or = or i64 %and, %conv1 %or = or i64 %and, %conv1
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_not_disjoint16_uint64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint64_t_float: ; CHECK-LABEL: st_not_disjoint16_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_disjoint_align16_uint64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint64_t_float: ; CHECK-LABEL: st_disjoint_align16_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint64_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-P10-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint64_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4 ; CHECK-PREP10-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint64_t_float(i64 %str) { define dso_local void @st_cst_align32_uint64_t_float(i64 %str) {
; CHECK-P10-LABEL: st_cst_align32_uint64_t_float: ; CHECK-LABEL: st_cst_align32_uint64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint64_t_float(i64 %str) { define dso_local void @st_cst_align64_uint64_t_float(i64 %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint64_t_float: ; CHECK-P8-LABEL: st_cst_align64_uint64_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to float %conv = uitofp i64 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_0_uint64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_0_uint64_t_double: ; CHECK-LABEL: st_0_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint64_t_double(i64 %ptr, i8 zeroext %off, i64 %str) { define dso_local void @st_or1_uint64_t_double(i64 %ptr, i8 zeroext %off, i64 %str) {
; CHECK-P10-LABEL: st_or1_uint64_t_double: ; CHECK-LABEL: st_or1_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 14 Linesentry:
%or = or i64 %and, %conv1 %or = or i64 %and, %conv1
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_not_disjoint16_uint64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint64_t_double: ; CHECK-LABEL: st_not_disjoint16_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_disjoint_align16_uint64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint64_t_double: ; CHECK-LABEL: st_disjoint_align16_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint64_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-P10-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint64_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4 ; CHECK-PREP10-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxddp f0, f0 ; CHECK-PREP10-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint64_t_double(i64 %str) { define dso_local void @st_cst_align32_uint64_t_double(i64 %str) {
; CHECK-P10-LABEL: st_cst_align32_uint64_t_double: ; CHECK-LABEL: st_cst_align32_uint64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint64_t_double(i64 %str) { define dso_local void @st_cst_align64_uint64_t_double(i64 %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint64_t_double: ; CHECK-P8-LABEL: st_cst_align64_uint64_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i64 %str to double %conv = uitofp i64 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_0_int64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_0_int64_t_float: ; CHECK-LABEL: st_0_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int64_t_float(i64 %ptr, i8 zeroext %off, i64 %str) { define dso_local void @st_or1_int64_t_float(i64 %ptr, i8 zeroext %off, i64 %str) {
; CHECK-P10-LABEL: st_or1_int64_t_float: ; CHECK-LABEL: st_or1_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
Show All 14 Linesentry:
%or = or i64 %and, %conv1 %or = or i64 %and, %conv1
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_not_disjoint16_int64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int64_t_float: ; CHECK-LABEL: st_not_disjoint16_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int64_t_float(i64 %ptr, i64 %str) { define dso_local void @st_disjoint_align16_int64_t_float(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int64_t_float: ; CHECK-LABEL: st_disjoint_align16_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int64_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_int64_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-P10-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int64_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_int64_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4 ; CHECK-PREP10-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int64_t_float(i64 %str) { define dso_local void @st_cst_align32_int64_t_float(i64 %str) {
; CHECK-P10-LABEL: st_cst_align32_int64_t_float: ; CHECK-LABEL: st_cst_align32_int64_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int64_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int64_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int64_t_float(i64 %str) { define dso_local void @st_cst_align64_int64_t_float(i64 %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int64_t_float: ; CHECK-P8-LABEL: st_cst_align64_int64_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to float %conv = sitofp i64 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_0_int64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_0_int64_t_double: ; CHECK-LABEL: st_0_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int64_t_double(i64 %ptr, i8 zeroext %off, i64 %str) { define dso_local void @st_or1_int64_t_double(i64 %ptr, i8 zeroext %off, i64 %str) {
; CHECK-P10-LABEL: st_or1_int64_t_double: ; CHECK-LABEL: st_or1_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r5 ; CHECK-NEXT: mtfprd f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 14 Linesentry:
%or = or i64 %and, %conv1 %or = or i64 %and, %conv1
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_not_disjoint16_int64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int64_t_double: ; CHECK-LABEL: st_not_disjoint16_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int64_t_double(i64 %ptr, i64 %str) { define dso_local void @st_disjoint_align16_int64_t_double(i64 %ptr, i64 %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int64_t_double: ; CHECK-LABEL: st_disjoint_align16_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r4 ; CHECK-NEXT: mtfprd f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int64_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_int64_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-P10-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int64_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_int64_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r4 ; CHECK-PREP10-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxddp f0, f0 ; CHECK-PREP10-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int64_t_double(i64 %str) { define dso_local void @st_cst_align32_int64_t_double(i64 %str) {
; CHECK-P10-LABEL: st_cst_align32_int64_t_double: ; CHECK-LABEL: st_cst_align32_int64_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int64_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int64_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int64_t_double(i64 %str) { define dso_local void @st_cst_align64_int64_t_double(i64 %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int64_t_double: ; CHECK-P8-LABEL: st_cst_align64_int64_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i64 %str to double %conv = sitofp i64 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,081 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = trunc i64 %0 to i8 %conv = trunc i64 %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_0_int8_t_float(i64 %ptr) { define dso_local signext i8 @ld_0_int8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int8_t_float: ; CHECK-LABEL: ld_0_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_or_int8_t_float(i64 %ptr, i8 zeroext %off) { define dso_local signext i8 @ld_or_int8_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int8_t_float: ; CHECK-LABEL: ld_or_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptosi float %1 to i8 %conv1 = fptosi float %1 to i8
ret i8 %conv1 ret i8 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_not_disjoint16_int8_t_float(i64 %ptr) { define dso_local signext i8 @ld_not_disjoint16_int8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int8_t_float: ; CHECK-LABEL: ld_not_disjoint16_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_disjoint_align16_int8_t_float(i64 %ptr) { define dso_local signext i8 @ld_disjoint_align16_int8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int8_t_float: ; CHECK-LABEL: ld_disjoint_align16_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_not_disjoint32_int8_t_float(i64 %ptr) { define dso_local signext i8 @ld_not_disjoint32_int8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int8_t_float: ; CHECK-LABEL: ld_not_disjoint32_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int8_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptosi float %1 to i8 %conv = fptosi float %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptosi float %0 to i8 %conv = fptosi float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_cst_align32_int8_t_float() { define dso_local signext i8 @ld_cst_align32_int8_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_int8_t_float: ; CHECK-LABEL: ld_cst_align32_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptosi float %0 to i8 %conv = fptosi float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_cst_align64_int8_t_float() { define dso_local signext i8 @ld_cst_align64_int8_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_int8_t_float: ; CHECK-P10-LABEL: ld_cst_align64_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int8_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_int8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptosi float %0 to i8 %conv = fptosi float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_0_int8_t_double(i64 %ptr) { define dso_local signext i8 @ld_0_int8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_int8_t_double: ; CHECK-LABEL: ld_0_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_or_int8_t_double(i64 %ptr, i8 zeroext %off) { define dso_local signext i8 @ld_or_int8_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_int8_t_double: ; CHECK-LABEL: ld_or_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptosi double %1 to i8 %conv1 = fptosi double %1 to i8
ret i8 %conv1 ret i8 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_not_disjoint16_int8_t_double(i64 %ptr) { define dso_local signext i8 @ld_not_disjoint16_int8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_int8_t_double: ; CHECK-LABEL: ld_not_disjoint16_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_disjoint_align16_int8_t_double(i64 %ptr) { define dso_local signext i8 @ld_disjoint_align16_int8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_int8_t_double: ; CHECK-LABEL: ld_disjoint_align16_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_not_disjoint32_int8_t_double(i64 %ptr) { define dso_local signext i8 @ld_not_disjoint32_int8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_int8_t_double: ; CHECK-LABEL: ld_not_disjoint32_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
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; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_int8_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_int8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptosi double %1 to i8 %conv = fptosi double %1 to i8
ret i8 %conv ret i8 %conv
} }
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entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_cst_align32_int8_t_double() { define dso_local signext i8 @ld_cst_align32_int8_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_int8_t_double: ; CHECK-LABEL: ld_cst_align32_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local signext i8 @ld_cst_align64_int8_t_double() { define dso_local signext i8 @ld_cst_align64_int8_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_int8_t_double: ; CHECK-P10-LABEL: ld_cst_align64_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: extsw r3, r3 ; CHECK-P10-NEXT: extsw r3, r3
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_int8_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_int8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-PREP10-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) { define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) {
▲ Show 20 Lines • Show All 2,514 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096 %0 = load i64, i64* inttoptr (i64 1000000000000 to i64*), align 4096
%conv = trunc i64 %0 to i8 %conv = trunc i64 %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_0_uint8_t_float(i64 %ptr) { define dso_local zeroext i8 @ld_0_uint8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint8_t_float: ; CHECK-LABEL: ld_0_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_or_uint8_t_float(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i8 @ld_or_uint8_t_float(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint8_t_float: ; CHECK-LABEL: ld_or_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv1 = fptoui float %1 to i8 %conv1 = fptoui float %1 to i8
ret i8 %conv1 ret i8 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_float(i64 %ptr) { define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint8_t_float: ; CHECK-LABEL: ld_not_disjoint16_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_float(i64 %ptr) { define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint8_t_float: ; CHECK-LABEL: ld_disjoint_align16_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfs f0, 24(r3) ; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfs f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 8 %1 = load float, float* %0, align 8
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_float(i64 %ptr) { define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_float(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint8_t_float: ; CHECK-LABEL: ld_not_disjoint32_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint8_t_float: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
%1 = load float, float* %0, align 4 %1 = load float, float* %0, align 4
%conv = fptoui float %1 to i8 %conv = fptoui float %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16 %0 = load float, float* inttoptr (i64 4080 to float*), align 16
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_align32_uint8_t_float() { define dso_local zeroext i8 @ld_cst_align32_uint8_t_float() {
; CHECK-P10-LABEL: ld_cst_align32_uint8_t_float: ; CHECK-LABEL: ld_cst_align32_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfs f0, -27108(r3) ; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfs f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4 %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_float() { define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_float() {
; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_float: ; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lfs f0, 0(r4) ; CHECK-P10-NEXT: lfs f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64_uint8_t_float: ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign64_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r3, 29
; CHECK-P8-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-NEXT: oris r3, r3, 54437
; CHECK-P8-NEXT: ori r3, r3, 4097
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4 %0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_align64_uint8_t_float() { define dso_local zeroext i8 @ld_cst_align64_uint8_t_float() {
; CHECK-P10-LABEL: ld_cst_align64_uint8_t_float: ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfs f0, 0(r3) ; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint8_t_float: ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfs f0, 0(r3) ; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfsx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096 %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_0_uint8_t_double(i64 %ptr) { define dso_local zeroext i8 @ld_0_uint8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_0_uint8_t_double: ; CHECK-LABEL: ld_0_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_0_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_0_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_or_uint8_t_double(i64 %ptr, i8 zeroext %off) { define dso_local zeroext i8 @ld_or_uint8_t_double(i64 %ptr, i8 zeroext %off) {
; CHECK-P10-LABEL: ld_or_uint8_t_double: ; CHECK-LABEL: ld_or_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_or_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_or_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%conv = zext i8 %off to i64 %conv = zext i8 %off to i64
%or = or i64 %conv, %ptr %or = or i64 %conv, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv1 = fptoui double %1 to i8 %conv1 = fptoui double %1 to i8
ret i8 %conv1 ret i8 %conv1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_double(i64 %ptr) { define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint16_uint8_t_double: ; CHECK-LABEL: ld_not_disjoint16_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint16_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint16_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_double(i64 %ptr) { define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_disjoint_align16_uint8_t_double: ; CHECK-LABEL: ld_disjoint_align16_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: lfd f0, 24(r3) ; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align16_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: lfd f0, 24(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align16_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_double(i64 %ptr) { define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_double(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint32_uint8_t_double: ; CHECK-LABEL: ld_not_disjoint32_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-P10-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_not_disjoint32_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: oris r3, r3, 1
; CHECK-P9-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint32_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_uint8_t_double: ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_not_disjoint64_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
%conv = fptoui double %1 to i8 %conv = fptoui double %1 to i8
ret i8 %conv ret i8 %conv
} }
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
entry: entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16 %0 = load double, double* inttoptr (i64 4080 to double*), align 16
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_align32_uint8_t_double() { define dso_local zeroext i8 @ld_cst_align32_uint8_t_double() {
; CHECK-P10-LABEL: ld_cst_align32_uint8_t_double: ; CHECK-LABEL: ld_cst_align32_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: lfd f0, -27108(r3) ; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: ld_cst_align32_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: lfd f0, -27108(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align32_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8 %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_double() { define dso_local zeroext i8 @ld_cst_unalign64_uint8_t_double() {
; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_double: ; CHECK-P10-LABEL: ld_cst_unalign64_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lfd f0, 0(r4) ; CHECK-P10-NEXT: lfd f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64_uint8_t_double: ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-PREP10-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-PREP10-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-PREP10-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_unalign64_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r3, 29
; CHECK-P8-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-NEXT: oris r3, r3, 54437
; CHECK-P8-NEXT: ori r3, r3, 4097
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8 %0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local zeroext i8 @ld_cst_align64_uint8_t_double() { define dso_local zeroext i8 @ld_cst_align64_uint8_t_double() {
; CHECK-P10-LABEL: ld_cst_align64_uint8_t_double: ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lfd f0, 0(r3) ; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0 ; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0 ; CHECK-P10-NEXT: mffprwz r3, f0
; CHECK-P10-NEXT: clrldi r3, r3, 32 ; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_uint8_t_double: ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lfd f0, 0(r3) ; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-PREP10-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: clrldi r3, r3, 32 ; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: ld_cst_align64_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: lfdx f0, 0, r3
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry: entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096 %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint8_t_uint8_t(i64 %ptr, i8 zeroext %str) { define dso_local void @st_0_uint8_t_uint8_t(i64 %ptr, i8 zeroext %str) {
▲ Show 20 Lines • Show All 1,125 Lines • ▼ Show 20 Lines
entry: entry:
%conv = zext i8 %str to i64 %conv = zext i8 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint8_t_float(i64 %ptr, i8 zeroext %str) { define dso_local void @st_0_uint8_t_float(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint8_t_float: ; CHECK-LABEL: st_0_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint8_t_float(i64 %ptr, i8 zeroext %off, i8 zeroext %str) { define dso_local void @st_or1_uint8_t_float(i64 %ptr, i8 zeroext %off, i8 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint8_t_float: ; CHECK-LABEL: st_or1_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint8_t_float(i64 %ptr, i8 zeroext %str) { define dso_local void @st_not_disjoint16_uint8_t_float(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint8_t_float: ; CHECK-LABEL: st_not_disjoint16_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint8_t_float(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align16_uint8_t_float(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint8_t_float: ; CHECK-LABEL: st_disjoint_align16_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint8_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-P10-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint8_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint8_t_float(i8 zeroext %str) { define dso_local void @st_cst_align32_uint8_t_float(i8 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint8_t_float: ; CHECK-LABEL: st_cst_align32_uint8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint8_t_float(i8 zeroext %str) { define dso_local void @st_cst_align64_uint8_t_float(i8 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint8_t_float: ; CHECK-P8-LABEL: st_cst_align64_uint8_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to float %conv = uitofp i8 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_uint8_t_double(i64 %ptr, i8 zeroext %str) { define dso_local void @st_0_uint8_t_double(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_0_uint8_t_double: ; CHECK-LABEL: st_0_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_uint8_t_double(i64 %ptr, i8 zeroext %off, i8 zeroext %str) { define dso_local void @st_or1_uint8_t_double(i64 %ptr, i8 zeroext %off, i8 zeroext %str) {
; CHECK-P10-LABEL: st_or1_uint8_t_double: ; CHECK-LABEL: st_or1_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r5 ; CHECK-NEXT: mtfprwz f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_uint8_t_double(i64 %ptr, i8 zeroext %str) { define dso_local void @st_not_disjoint16_uint8_t_double(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_uint8_t_double: ; CHECK-LABEL: st_not_disjoint16_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_uint8_t_double(i64 %ptr, i8 zeroext %str) { define dso_local void @st_disjoint_align16_uint8_t_double(i64 %ptr, i8 zeroext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_uint8_t_double: ; CHECK-LABEL: st_disjoint_align16_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r4 ; CHECK-NEXT: mtfprwz f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_uint8_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-P10-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_uint8_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r4 ; CHECK-PREP10-NEXT: mtfprwz f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvuxddp f0, f0 ; CHECK-PREP10-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
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entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_uint8_t_double(i8 zeroext %str) { define dso_local void @st_cst_align32_uint8_t_double(i8 zeroext %str) {
; CHECK-P10-LABEL: st_cst_align32_uint8_t_double: ; CHECK-LABEL: st_cst_align32_uint8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvuxddp f0, f0 ; CHECK-NEXT: xscvuxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_uint8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvuxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_uint8_t_double(i8 zeroext %str) { define dso_local void @st_cst_align64_uint8_t_double(i8 zeroext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_uint8_t_double: ; CHECK-P8-LABEL: st_cst_align64_uint8_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwz f0, r3 ; CHECK-P8-NEXT: mtfprwz f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvuxddp f0, f0 ; CHECK-P8-NEXT: xscvuxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = uitofp i8 %str to double %conv = uitofp i8 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
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entry: entry:
%conv = sext i8 %str to i64 %conv = sext i8 %str to i64
store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096 store i64 %conv, i64* inttoptr (i64 1000000000000 to i64*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int8_t_float(i64 %ptr, i8 signext %str) { define dso_local void @st_0_int8_t_float(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_0_int8_t_float: ; CHECK-LABEL: st_0_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%0 = inttoptr i64 %ptr to float* %0 = inttoptr i64 %ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to float* %0 = bitcast i8* %add.ptr to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int8_t_float(i64 %ptr, i8 zeroext %off, i8 signext %str) { define dso_local void @st_or1_int8_t_float(i64 %ptr, i8 zeroext %off, i8 signext %str) {
; CHECK-P10-LABEL: st_or1_int8_t_float: ; CHECK-LABEL: st_or1_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int8_t_float(i64 %ptr, i8 signext %str) { define dso_local void @st_not_disjoint16_int8_t_float(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int8_t_float: ; CHECK-LABEL: st_not_disjoint16_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int8_t_float(i64 %ptr, i8 signext %str) { define dso_local void @st_disjoint_align16_int8_t_float(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int8_t_float: ; CHECK-LABEL: st_disjoint_align16_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, 24(r3) ; CHECK-NEXT: stfs f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 8 store float %conv, float* %0, align 8
ret void ret void
} }
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; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int8_t_float: ; CHECK-P8-LABEL: st_not_disjoint32_int8_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-P10-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfs f0, 0(r3) ; CHECK-P10-NEXT: stfs f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int8_t_float: ; CHECK-PREP10-LABEL: st_not_disjoint64_int8_t_float:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-PREP10-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfs f0, 0(r3) ; CHECK-PREP10-NEXT: stfs f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to float* %0 = inttoptr i64 %or to float*
store float %conv, float* %0, align 4 store float %conv, float* %0, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
store float %conv, float* inttoptr (i64 4080 to float*), align 16 store float %conv, float* inttoptr (i64 4080 to float*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int8_t_float(i8 signext %str) { define dso_local void @st_cst_align32_int8_t_float(i8 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int8_t_float: ; CHECK-LABEL: st_cst_align32_int8_t_float:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-P10-NEXT: stfs f0, -27108(r3) ; CHECK-NEXT: stfs f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int8_t_float:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: stfs f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int8_t_float:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: stfsx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
store float %conv, float* inttoptr (i64 9999900 to float*), align 4 store float %conv, float* inttoptr (i64 9999900 to float*), align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int8_t_float(i8 signext %str) { define dso_local void @st_cst_align64_int8_t_float(i8 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int8_t_float: ; CHECK-P8-LABEL: st_cst_align64_int8_t_float:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfsx f0, 0, r3 ; CHECK-P8-NEXT: stfs f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to float %conv = sitofp i8 %str to float
store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096 store float %conv, float* inttoptr (i64 1000000000000 to float*), align 4096
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_0_int8_t_double(i64 %ptr, i8 signext %str) { define dso_local void @st_0_int8_t_double(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_0_int8_t_double: ; CHECK-LABEL: st_0_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_0_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_0_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%0 = inttoptr i64 %ptr to double* %0 = inttoptr i64 %ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
%0 = bitcast i8* %add.ptr to double* %0 = bitcast i8* %add.ptr to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_int8_t_double(i64 %ptr, i8 zeroext %off, i8 signext %str) { define dso_local void @st_or1_int8_t_double(i64 %ptr, i8 zeroext %off, i8 signext %str) {
; CHECK-P10-LABEL: st_or1_int8_t_double: ; CHECK-LABEL: st_or1_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r5 ; CHECK-NEXT: mtfprwa f0, r5
; CHECK-P10-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_or1_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r5
; CHECK-P9-NEXT: or r3, r4, r3
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_or1_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r5
; CHECK-P8-NEXT: or r3, r4, r3
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%conv1 = zext i8 %off to i64 %conv1 = zext i8 %off to i64
%or = or i64 %conv1, %ptr %or = or i64 %conv1, %ptr
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_int8_t_double(i64 %ptr, i8 signext %str) { define dso_local void @st_not_disjoint16_int8_t_double(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_not_disjoint16_int8_t_double: ; CHECK-LABEL: st_not_disjoint16_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_not_disjoint16_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: ori r3, r3, 6
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint16_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 6
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%or = or i64 %ptr, 6 %or = or i64 %ptr, 6
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_int8_t_double(i64 %ptr, i8 signext %str) { define dso_local void @st_disjoint_align16_int8_t_double(i64 %ptr, i8 signext %str) {
; CHECK-P10-LABEL: st_disjoint_align16_int8_t_double: ; CHECK-LABEL: st_disjoint_align16_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r4 ; CHECK-NEXT: mtfprwa f0, r4
; CHECK-P10-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, 24(r3) ; CHECK-NEXT: stfd f0, 24(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_disjoint_align16_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: rldicr r3, r3, 0, 51
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, 24(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_disjoint_align16_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-NEXT: ori r3, r3, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%and = and i64 %ptr, -4096 %and = and i64 %ptr, -4096
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%or = or i64 %and, 24 %or = or i64 %and, 24
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
Show All 19 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: st_not_disjoint32_int8_t_double: ; CHECK-P8-LABEL: st_not_disjoint32_int8_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: ori r3, r3, 34463 ; CHECK-P8-NEXT: ori r3, r3, 34463
; CHECK-P8-NEXT: oris r3, r3, 1 ; CHECK-P8-NEXT: oris r3, r3, 1
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%or = or i64 %ptr, 99999 %or = or i64 %ptr, 99999
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-P10-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stfd f0, 0(r3) ; CHECK-P10-NEXT: stfd f0, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_int8_t_double: ; CHECK-PREP10-LABEL: st_not_disjoint64_int8_t_double:
; CHECK-P9: # %bb.0: # %entry ; CHECK-PREP10: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r4 ; CHECK-PREP10-NEXT: mtfprwa f0, r4
; CHECK-P9-NEXT: li r4, 29 ; CHECK-PREP10-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-PREP10-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: xscvsxddp f0, f0 ; CHECK-PREP10-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stfd f0, 0(r3) ; CHECK-PREP10-NEXT: stfd f0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-PREP10-NEXT: blr
;
; CHECK-P8-LABEL: st_not_disjoint64_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: li r4, 29
; CHECK-P8-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: oris r4, r4, 54437
; CHECK-P8-NEXT: ori r4, r4, 4097
; CHECK-P8-NEXT: or r3, r3, r4
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
%or = or i64 %ptr, 1000000000001 %or = or i64 %ptr, 1000000000001
%0 = inttoptr i64 %or to double* %0 = inttoptr i64 %or to double*
store double %conv, double* %0, align 8 store double %conv, double* %0, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
store double %conv, double* inttoptr (i64 4080 to double*), align 16 store double %conv, double* inttoptr (i64 4080 to double*), align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_int8_t_double(i8 signext %str) { define dso_local void @st_cst_align32_int8_t_double(i8 signext %str) {
; CHECK-P10-LABEL: st_cst_align32_int8_t_double: ; CHECK-LABEL: st_cst_align32_int8_t_double:
; CHECK-P10: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-P10-NEXT: mtfprwa f0, r3 ; CHECK-NEXT: mtfprwa f0, r3
; CHECK-P10-NEXT: lis r3, 153 ; CHECK-NEXT: lis r3, 153
; CHECK-P10-NEXT: xscvsxddp f0, f0 ; CHECK-NEXT: xscvsxddp f0, f0
; CHECK-P10-NEXT: stfd f0, -27108(r3) ; CHECK-NEXT: stfd f0, -27108(r3)
; CHECK-P10-NEXT: blr ; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: st_cst_align32_int8_t_double:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtfprwa f0, r3
; CHECK-P9-NEXT: lis r3, 153
; CHECK-P9-NEXT: xscvsxddp f0, f0
; CHECK-P9-NEXT: stfd f0, -27108(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: st_cst_align32_int8_t_double:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 152
; CHECK-P8-NEXT: ori r3, r3, 38428
; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: stfdx f0, 0, r3
; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
store double %conv, double* inttoptr (i64 9999900 to double*), align 8 store double %conv, double* inttoptr (i64 9999900 to double*), align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_int8_t_double(i8 signext %str) { define dso_local void @st_cst_align64_int8_t_double(i8 signext %str) {
Show All 18 Lines
; ;
; CHECK-P8-LABEL: st_cst_align64_int8_t_double: ; CHECK-P8-LABEL: st_cst_align64_int8_t_double:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprwa f0, r3 ; CHECK-P8-NEXT: mtfprwa f0, r3
; CHECK-P8-NEXT: lis r3, 3725 ; CHECK-P8-NEXT: lis r3, 3725
; CHECK-P8-NEXT: ori r3, r3, 19025 ; CHECK-P8-NEXT: ori r3, r3, 19025
; CHECK-P8-NEXT: xscvsxddp f0, f0 ; CHECK-P8-NEXT: xscvsxddp f0, f0
; CHECK-P8-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-NEXT: stfdx f0, 0, r3 ; CHECK-P8-NEXT: stfd f0, 0(r3)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = sitofp i8 %str to double %conv = sitofp i8 %str to double
store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096 store double %conv, double* inttoptr (i64 1000000000000 to double*), align 4096
ret void ret void
} }

llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; P8LE-LABEL: s2v_test_f1: ; P8LE-LABEL: s2v_test_f1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfdx f0, 0, r3 ; P8LE-NEXT: lfdx f0, 0, r3
; P8LE-NEXT: xxmrghd v2, v2, vs0 ; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f1: ; P8BE-LABEL: s2v_test_f1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfdx f0, 0, r3 ; P8BE-NEXT: lfd f0, 0(r3)
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1 ; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
entry: entry:
%0 = load double, double* %f64, align 8 %0 = load double, double* %f64, align 8
%vecins = insertelement <2 x double> %vec, double %0, i32 0 %vecins = insertelement <2 x double> %vec, double %0, i32 0
ret <2 x double> %vecins ret <2 x double> %vecins
} }
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; P8LE-LABEL: s2v_test_f5: ; P8LE-LABEL: s2v_test_f5:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lfdx f0, 0, r5 ; P8LE-NEXT: lfdx f0, 0, r5
; P8LE-NEXT: xxmrghd v2, v2, vs0 ; P8LE-NEXT: xxmrghd v2, v2, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; P8BE-LABEL: s2v_test_f5: ; P8BE-LABEL: s2v_test_f5:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lfdx f0, 0, r5 ; P8BE-NEXT: lfd f0, 0(r5)
; P8BE-NEXT: xxpermdi v2, vs0, v2, 1 ; P8BE-NEXT: xxpermdi v2, vs0, v2, 1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
entry: entry:
%0 = load double, double* %ptr1, align 8 %0 = load double, double* %ptr1, align 8
%vecins = insertelement <2 x double> %vec, double %0, i32 0 %vecins = insertelement <2 x double> %vec, double %0, i32 0
ret <2 x double> %vecins ret <2 x double> %vecins
} }

llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll

Show All 21 Lines
; P9BE-NEXT: lfs f0, 0(r3) ; P9BE-NEXT: lfs f0, 0(r3)
; P9BE-NEXT: lfs f1, 0(r4) ; P9BE-NEXT: lfs f1, 0(r4)
; P9BE-NEXT: xsaddsp f0, f0, f1 ; P9BE-NEXT: xsaddsp f0, f0, f1
; P9BE-NEXT: stfs f0, 0(r5) ; P9BE-NEXT: stfs f0, 0(r5)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: test_liwzx1: ; P8LE-LABEL: test_liwzx1:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lfsx f0, 0, r3 ; P8LE-NEXT: lfs f0, 0(r3)
; P8LE-NEXT: lfsx f1, 0, r4 ; P8LE-NEXT: lfs f1, 0(r4)
; P8LE-NEXT: xsaddsp f0, f0, f1 ; P8LE-NEXT: xsaddsp f0, f0, f1
; P8LE-NEXT: stfsx f0, 0, r5 ; P8LE-NEXT: stfs f0, 0(r5)
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: test_liwzx1: ; P8BE-LABEL: test_liwzx1:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lfsx f0, 0, r3 ; P8BE-NEXT: lfs f0, 0(r3)
; P8BE-NEXT: lfsx f1, 0, r4 ; P8BE-NEXT: lfs f1, 0(r4)
; P8BE-NEXT: xsaddsp f0, f0, f1 ; P8BE-NEXT: xsaddsp f0, f0, f1
; P8BE-NEXT: stfsx f0, 0, r5 ; P8BE-NEXT: stfs f0, 0(r5)
; P8BE-NEXT: blr ; P8BE-NEXT: blr
%a = load <1 x float>, <1 x float>* %A %a = load <1 x float>, <1 x float>* %A
%b = load <1 x float>, <1 x float>* %B %b = load <1 x float>, <1 x float>* %B
%X = fadd <1 x float> %a, %b %X = fadd <1 x float> %a, %b
store <1 x float> %X, <1 x float>* %C store <1 x float> %X, <1 x float>* %C
Show All 16 Lines
; P9BE-NEXT: mr r3, r5 ; P9BE-NEXT: mr r3, r5
; P9BE-NEXT: lfs f1, 0(r4) ; P9BE-NEXT: lfs f1, 0(r4)
; P9BE-NEXT: xssubsp f0, f0, f1 ; P9BE-NEXT: xssubsp f0, f0, f1
; P9BE-NEXT: stfs f0, 0(r5) ; P9BE-NEXT: stfs f0, 0(r5)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: test_liwzx2: ; P8LE-LABEL: test_liwzx2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lfsx f0, 0, r3 ; P8LE-NEXT: lfs f0, 0(r3)
; P8LE-NEXT: lfsx f1, 0, r4 ; P8LE-NEXT: lfs f1, 0(r4)
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: xssubsp f0, f0, f1 ; P8LE-NEXT: xssubsp f0, f0, f1
; P8LE-NEXT: stfsx f0, 0, r5 ; P8LE-NEXT: stfs f0, 0(r5)
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: test_liwzx2: ; P8BE-LABEL: test_liwzx2:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lfsx f0, 0, r3 ; P8BE-NEXT: lfs f0, 0(r3)
; P8BE-NEXT: lfsx f1, 0, r4 ; P8BE-NEXT: lfs f1, 0(r4)
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: xssubsp f0, f0, f1 ; P8BE-NEXT: xssubsp f0, f0, f1
; P8BE-NEXT: stfsx f0, 0, r5 ; P8BE-NEXT: stfs f0, 0(r5)
; P8BE-NEXT: blr ; P8BE-NEXT: blr
%a = load <1 x float>, <1 x float>* %A %a = load <1 x float>, <1 x float>* %A
%b = load <1 x float>, <1 x float>* %B %b = load <1 x float>, <1 x float>* %B
%X = fsub <1 x float> %a, %b %X = fsub <1 x float> %a, %b
store <1 x float> %X, <1 x float>* %C store <1 x float> %X, <1 x float>* %C
ret <1 x float>* %C ret <1 x float>* %C
} }

llvm/test/CodeGen/PowerPC/select_const.ll

Show First 20 Lines • Show All 720 Lines • ▼ Show 20 Lines
; ISEL-LABEL: sel_constants_fadd_constant: ; ISEL-LABEL: sel_constants_fadd_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fadd_constant: ; NO_ISEL-LABEL: sel_constants_fadd_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI42_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI42_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB42_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB42_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB42_2 ; NO_ISEL-NEXT: b .LBB42_2
; NO_ISEL-NEXT: .LBB42_2: ; NO_ISEL-NEXT: .LBB42_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fadd double %sel, 5.1 %bo = fadd double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_fsub_constant(i1 %cond) { define double @sel_constants_fsub_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fsub_constant: ; ISEL-LABEL: sel_constants_fsub_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fsub_constant: ; NO_ISEL-LABEL: sel_constants_fsub_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI43_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI43_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB43_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB43_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB43_2 ; NO_ISEL-NEXT: b .LBB43_2
; NO_ISEL-NEXT: .LBB43_2: ; NO_ISEL-NEXT: .LBB43_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fsub double %sel, 5.1 %bo = fsub double %sel, 5.1
ret double %bo ret double %bo
} }
define double @fsub_constant_sel_constants(i1 %cond) { define double @fsub_constant_sel_constants(i1 %cond) {
; ISEL-LABEL: fsub_constant_sel_constants: ; ISEL-LABEL: fsub_constant_sel_constants:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: fsub_constant_sel_constants: ; NO_ISEL-LABEL: fsub_constant_sel_constants:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI44_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI44_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB44_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB44_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB44_2 ; NO_ISEL-NEXT: b .LBB44_2
; NO_ISEL-NEXT: .LBB44_2: ; NO_ISEL-NEXT: .LBB44_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fsub double 5.1, %sel %bo = fsub double 5.1, %sel
ret double %bo ret double %bo
} }
define double @sel_constants_fmul_constant(i1 %cond) { define double @sel_constants_fmul_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fmul_constant: ; ISEL-LABEL: sel_constants_fmul_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fmul_constant: ; NO_ISEL-LABEL: sel_constants_fmul_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI45_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI45_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB45_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB45_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB45_2 ; NO_ISEL-NEXT: b .LBB45_2
; NO_ISEL-NEXT: .LBB45_2: ; NO_ISEL-NEXT: .LBB45_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fmul double %sel, 5.1 %bo = fmul double %sel, 5.1
ret double %bo ret double %bo
} }
define double @sel_constants_fdiv_constant(i1 %cond) { define double @sel_constants_fdiv_constant(i1 %cond) {
; ISEL-LABEL: sel_constants_fdiv_constant: ; ISEL-LABEL: sel_constants_fdiv_constant:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: sel_constants_fdiv_constant: ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI46_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI46_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB46_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB46_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB46_2 ; NO_ISEL-NEXT: b .LBB46_2
; NO_ISEL-NEXT: .LBB46_2: ; NO_ISEL-NEXT: .LBB46_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fdiv double %sel, 5.1 %bo = fdiv double %sel, 5.1
ret double %bo ret double %bo
} }
define double @fdiv_constant_sel_constants(i1 %cond) { define double @fdiv_constant_sel_constants(i1 %cond) {
; ISEL-LABEL: fdiv_constant_sel_constants: ; ISEL-LABEL: fdiv_constant_sel_constants:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: fdiv_constant_sel_constants: ; NO_ISEL-LABEL: fdiv_constant_sel_constants:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI47_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI47_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB47_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB47_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB47_2 ; NO_ISEL-NEXT: b .LBB47_2
; NO_ISEL-NEXT: .LBB47_2: ; NO_ISEL-NEXT: .LBB47_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = fdiv double 5.1, %sel %bo = fdiv double 5.1, %sel
ret double %bo ret double %bo
} }
define double @sel_constants_frem_constant(i1 %cond) { define double @sel_constants_frem_constant(i1 %cond) {
; ALL-LABEL: sel_constants_frem_constant: ; ALL-LABEL: sel_constants_frem_constant:
Show All 17 Lines
; ISEL-LABEL: frem_constant_sel_constants: ; ISEL-LABEL: frem_constant_sel_constants:
; ISEL: # %bb.0: ; ISEL: # %bb.0:
; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: andi. 3, 3, 1
; ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha ; ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha
; ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha
; ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l ; ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l
; ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l
; ISEL-NEXT: iselgt 3, 3, 4 ; ISEL-NEXT: iselgt 3, 3, 4
; ISEL-NEXT: lfdx 1, 0, 3 ; ISEL-NEXT: lfd 1, 0(3)
; ISEL-NEXT: blr ; ISEL-NEXT: blr
; ;
; NO_ISEL-LABEL: frem_constant_sel_constants: ; NO_ISEL-LABEL: frem_constant_sel_constants:
; NO_ISEL: # %bb.0: ; NO_ISEL: # %bb.0:
; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: andi. 3, 3, 1
; NO_ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha ; NO_ISEL-NEXT: addis 4, 2, .LCPI49_0@toc@ha
; NO_ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI49_1@toc@ha
; NO_ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l ; NO_ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l
; NO_ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l
; NO_ISEL-NEXT: bc 12, 1, .LBB49_2 ; NO_ISEL-NEXT: bc 12, 1, .LBB49_2
; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: # %bb.1:
; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: ori 3, 4, 0
; NO_ISEL-NEXT: b .LBB49_2 ; NO_ISEL-NEXT: b .LBB49_2
; NO_ISEL-NEXT: .LBB49_2: ; NO_ISEL-NEXT: .LBB49_2:
; NO_ISEL-NEXT: lfdx 1, 0, 3 ; NO_ISEL-NEXT: lfd 1, 0(3)
; NO_ISEL-NEXT: blr ; NO_ISEL-NEXT: blr
%sel = select i1 %cond, double -4.0, double 23.3 %sel = select i1 %cond, double -4.0, double 23.3
%bo = frem double 5.1, %sel %bo = frem double 5.1, %sel
ret double %bo ret double %bo
} }

llvm/test/CodeGen/PowerPC/store_fptoi.ll

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpsxds 2, 0 ; CHECK-NEXT: xscvdpsxds 2, 0
; CHECK-NEXT: stxsd 2, 0(4) ; CHECK-NEXT: stxsd 2, 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sdw: ; CHECK-PWR8-LABEL: dpConv2sdw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i64 %conv = fptosi double %0 to i64
store i64 %conv, i64* %b, align 8 store i64 %conv, i64* %b, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) { define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) {
; CHECK-LABEL: dpConv2sw: ; CHECK-LABEL: dpConv2sw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stfiwx 0, 0, 4 ; CHECK-NEXT: stfiwx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sw: ; CHECK-PWR8-LABEL: dpConv2sw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) { define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) {
; CHECK-LABEL: dpConv2shw: ; CHECK-LABEL: dpConv2shw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsihx 0, 0, 4 ; CHECK-NEXT: stxsihx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2shw: ; CHECK-PWR8-LABEL: dpConv2shw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sth 3, 0(4) ; CHECK-PWR8-NEXT: sth 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i16 %conv = fptosi double %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) { define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) {
; CHECK-LABEL: dpConv2sb: ; CHECK-LABEL: dpConv2sb:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsibx 0, 0, 4 ; CHECK-NEXT: stxsibx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sb: ; CHECK-PWR8-LABEL: dpConv2sb:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stb 3, 0(4) ; CHECK-PWR8-NEXT: stb 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) { define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) {
; CHECK-LABEL: spConv2sdw: ; CHECK-LABEL: spConv2sdw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxds 2, 0 ; CHECK-NEXT: xscvdpsxds 2, 0
; CHECK-NEXT: stxsd 2, 0(4) ; CHECK-NEXT: stxsd 2, 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sdw: ; CHECK-PWR8-LABEL: spConv2sdw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
store i64 %conv, i64* %b, align 8 store i64 %conv, i64* %b, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sw(float* nocapture readonly %a, i32* nocapture %b) { define void @spConv2sw(float* nocapture readonly %a, i32* nocapture %b) {
; CHECK-LABEL: spConv2sw: ; CHECK-LABEL: spConv2sw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stfiwx 0, 0, 4 ; CHECK-NEXT: stfiwx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sw: ; CHECK-PWR8-LABEL: spConv2sw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2shw(float* nocapture readonly %a, i16* nocapture %b) { define void @spConv2shw(float* nocapture readonly %a, i16* nocapture %b) {
; CHECK-LABEL: spConv2shw: ; CHECK-LABEL: spConv2shw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsihx 0, 0, 4 ; CHECK-NEXT: stxsihx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2shw: ; CHECK-PWR8-LABEL: spConv2shw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sth 3, 0(4) ; CHECK-PWR8-NEXT: sth 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i16 %conv = fptosi float %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2sb(float* nocapture readonly %a, i8* nocapture %b) { define void @spConv2sb(float* nocapture readonly %a, i8* nocapture %b) {
; CHECK-LABEL: spConv2sb: ; CHECK-LABEL: spConv2sb:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsibx 0, 0, 4 ; CHECK-NEXT: stxsibx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sb: ; CHECK-PWR8-LABEL: spConv2sb:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stb 3, 0(4) ; CHECK-PWR8-NEXT: stb 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i8 %conv = fptosi float %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
Show All 9 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 3 ; CHECK-NEXT: sldi 3, 5, 3
; CHECK-NEXT: xscvdpsxds 0, 0 ; CHECK-NEXT: xscvdpsxds 0, 0
; CHECK-NEXT: stxsdx 0, 4, 3 ; CHECK-NEXT: stxsdx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sdw_x: ; CHECK-PWR8-LABEL: dpConv2sdw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: sldi 3, 5, 3
; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i64 %conv = fptosi double %0 to i64
Show All 12 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 2 ; CHECK-NEXT: sldi 3, 5, 2
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stfiwx 0, 4, 3 ; CHECK-NEXT: stfiwx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sw_x: ; CHECK-PWR8-LABEL: dpConv2sw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: sldi 3, 5, 2
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i32 %conv = fptosi double %0 to i32
Show All 12 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 1 ; CHECK-NEXT: sldi 3, 5, 1
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsihx 0, 4, 3 ; CHECK-NEXT: stxsihx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2shw_x: ; CHECK-PWR8-LABEL: dpConv2shw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: sldi 5, 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sthx 3, 4, 5 ; CHECK-PWR8-NEXT: sthx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsibx 0, 4, 5 ; CHECK-NEXT: stxsibx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2sb_x: ; CHECK-PWR8-LABEL: dpConv2sb_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stbx 3, 4, 5 ; CHECK-PWR8-NEXT: stbx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptosi double %0 to i8 %conv = fptosi double %0 to i8
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxds 0, 0 ; CHECK-NEXT: xscvdpsxds 0, 0
; CHECK-NEXT: sldi 5, 5, 3 ; CHECK-NEXT: sldi 5, 5, 3
; CHECK-NEXT: stxsdx 0, 4, 5 ; CHECK-NEXT: stxsdx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sdw_x: ; CHECK-PWR8-LABEL: spConv2sdw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: sldi 3, 5, 3
; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i64 %conv = fptosi float %0 to i64
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: sldi 5, 5, 2 ; CHECK-NEXT: sldi 5, 5, 2
; CHECK-NEXT: stfiwx 0, 4, 5 ; CHECK-NEXT: stfiwx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sw_x: ; CHECK-PWR8-LABEL: spConv2sw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: sldi 3, 5, 2
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i32 %conv = fptosi float %0 to i32
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: sldi 5, 5, 1 ; CHECK-NEXT: sldi 5, 5, 1
; CHECK-NEXT: stxsihx 0, 4, 5 ; CHECK-NEXT: stxsihx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2shw_x: ; CHECK-PWR8-LABEL: spConv2shw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: sldi 5, 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sthx 3, 4, 5 ; CHECK-PWR8-NEXT: sthx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpsxws 0, 0 ; CHECK-NEXT: xscvdpsxws 0, 0
; CHECK-NEXT: stxsibx 0, 4, 5 ; CHECK-NEXT: stxsibx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2sb_x: ; CHECK-PWR8-LABEL: spConv2sb_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stbx 3, 4, 5 ; CHECK-PWR8-NEXT: stbx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 signext %idx) { i32 signext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptosi float %0 to i8 %conv = fptosi float %0 to i8
Show All 15 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpuxds 2, 0 ; CHECK-NEXT: xscvdpuxds 2, 0
; CHECK-NEXT: stxsd 2, 0(4) ; CHECK-NEXT: stxsd 2, 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2udw: ; CHECK-PWR8-LABEL: dpConv2udw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
store i64 %conv, i64* %b, align 8 store i64 %conv, i64* %b, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) { define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) {
; CHECK-LABEL: dpConv2uw: ; CHECK-LABEL: dpConv2uw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stfiwx 0, 0, 4 ; CHECK-NEXT: stfiwx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2uw: ; CHECK-PWR8-LABEL: dpConv2uw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) { define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) {
; CHECK-LABEL: dpConv2uhw: ; CHECK-LABEL: dpConv2uhw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsihx 0, 0, 4 ; CHECK-NEXT: stxsihx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2uhw: ; CHECK-PWR8-LABEL: dpConv2uhw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sth 3, 0(4) ; CHECK-PWR8-NEXT: sth 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) { define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) {
; CHECK-LABEL: dpConv2ub: ; CHECK-LABEL: dpConv2ub:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsibx 0, 0, 4 ; CHECK-NEXT: stxsibx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2ub: ; CHECK-PWR8-LABEL: dpConv2ub:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stb 3, 0(4) ; CHECK-PWR8-NEXT: stb 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) { define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) {
; CHECK-LABEL: spConv2udw: ; CHECK-LABEL: spConv2udw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxds 2, 0 ; CHECK-NEXT: xscvdpuxds 2, 0
; CHECK-NEXT: stxsd 2, 0(4) ; CHECK-NEXT: stxsd 2, 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2udw: ; CHECK-PWR8-LABEL: spConv2udw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
store i64 %conv, i64* %b, align 8 store i64 %conv, i64* %b, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2uw(float* nocapture readonly %a, i32* nocapture %b) { define void @spConv2uw(float* nocapture readonly %a, i32* nocapture %b) {
; CHECK-LABEL: spConv2uw: ; CHECK-LABEL: spConv2uw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stfiwx 0, 0, 4 ; CHECK-NEXT: stfiwx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2uw: ; CHECK-PWR8-LABEL: spConv2uw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
store i32 %conv, i32* %b, align 4 store i32 %conv, i32* %b, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2uhw(float* nocapture readonly %a, i16* nocapture %b) { define void @spConv2uhw(float* nocapture readonly %a, i16* nocapture %b) {
; CHECK-LABEL: spConv2uhw: ; CHECK-LABEL: spConv2uhw:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsihx 0, 0, 4 ; CHECK-NEXT: stxsihx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2uhw: ; CHECK-PWR8-LABEL: spConv2uhw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sth 3, 0(4) ; CHECK-PWR8-NEXT: sth 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
store i16 %conv, i16* %b, align 2 store i16 %conv, i16* %b, align 2
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @spConv2ub(float* nocapture readonly %a, i8* nocapture %b) { define void @spConv2ub(float* nocapture readonly %a, i8* nocapture %b) {
; CHECK-LABEL: spConv2ub: ; CHECK-LABEL: spConv2ub:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsibx 0, 0, 4 ; CHECK-NEXT: stxsibx 0, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2ub: ; CHECK-PWR8-LABEL: spConv2ub:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stb 3, 0(4) ; CHECK-PWR8-NEXT: stb 3, 0(4)
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
store i8 %conv, i8* %b, align 1 store i8 %conv, i8* %b, align 1
Show All 9 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 3 ; CHECK-NEXT: sldi 3, 5, 3
; CHECK-NEXT: xscvdpuxds 0, 0 ; CHECK-NEXT: xscvdpuxds 0, 0
; CHECK-NEXT: stxsdx 0, 4, 3 ; CHECK-NEXT: stxsdx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2udw_x: ; CHECK-PWR8-LABEL: dpConv2udw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: sldi 3, 5, 3
; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i64 %conv = fptoui double %0 to i64
Show All 12 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 2 ; CHECK-NEXT: sldi 3, 5, 2
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stfiwx 0, 4, 3 ; CHECK-NEXT: stfiwx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2uw_x: ; CHECK-PWR8-LABEL: dpConv2uw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: sldi 3, 5, 2
; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
Show All 12 Lines
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: sldi 3, 5, 1 ; CHECK-NEXT: sldi 3, 5, 1
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsihx 0, 4, 3 ; CHECK-NEXT: stxsihx 0, 4, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2uhw_x: ; CHECK-PWR8-LABEL: dpConv2uhw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: sldi 5, 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sthx 3, 4, 5 ; CHECK-PWR8-NEXT: sthx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsibx 0, 4, 5 ; CHECK-NEXT: stxsibx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: dpConv2ub_x: ; CHECK-PWR8-LABEL: dpConv2ub_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfdx 0, 0, 3 ; CHECK-PWR8-NEXT: lfd 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stbx 3, 4, 5 ; CHECK-PWR8-NEXT: stbx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxds 0, 0 ; CHECK-NEXT: xscvdpuxds 0, 0
; CHECK-NEXT: sldi 5, 5, 3 ; CHECK-NEXT: sldi 5, 5, 3
; CHECK-NEXT: stxsdx 0, 4, 5 ; CHECK-NEXT: stxsdx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2udw_x: ; CHECK-PWR8-LABEL: spConv2udw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: sldi 3, 5, 3
; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0
; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i64 %conv = fptoui float %0 to i64
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: sldi 5, 5, 2 ; CHECK-NEXT: sldi 5, 5, 2
; CHECK-NEXT: stfiwx 0, 4, 5 ; CHECK-NEXT: stfiwx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2uw_x: ; CHECK-PWR8-LABEL: spConv2uw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: sldi 3, 5, 2
; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0
; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
Show All 12 Lines
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: sldi 5, 5, 1 ; CHECK-NEXT: sldi 5, 5, 1
; CHECK-NEXT: stxsihx 0, 4, 5 ; CHECK-NEXT: stxsihx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2uhw_x: ; CHECK-PWR8-LABEL: spConv2uhw_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: sldi 5, 5, 1
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: sthx 3, 4, 5 ; CHECK-PWR8-NEXT: sthx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: lfs 0, 0(3)
; CHECK-NEXT: xscvdpuxws 0, 0 ; CHECK-NEXT: xscvdpuxws 0, 0
; CHECK-NEXT: stxsibx 0, 4, 5 ; CHECK-NEXT: stxsibx 0, 4, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: spConv2ub_x: ; CHECK-PWR8-LABEL: spConv2ub_x:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: lfsx 0, 0, 3 ; CHECK-PWR8-NEXT: lfs 0, 0(3)
; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0
; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0
; CHECK-PWR8-NEXT: stbx 3, 4, 5 ; CHECK-PWR8-NEXT: stbx 3, 4, 5
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
i32 zeroext %idx) { i32 zeroext %idx) {
entry: entry:
%0 = load float, float* %a, align 4 %0 = load float, float* %a, align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
%idxprom = zext i32 %idx to i64 %idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom %arrayidx = getelementptr inbounds i8, i8* %b, i64 %idxprom
store i8 %conv, i8* %arrayidx, align 1 store i8 %conv, i8* %arrayidx, align 1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/swaps-le-6.ll

Show All 40 Lines
; CHECK-P9-NOVECTOR: xxmrgld vs0, vs1, vs0 ; CHECK-P9-NOVECTOR: xxmrgld vs0, vs1, vs0
; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3 ; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
; CHECK-P9-NOVECTOR: blr ; CHECK-P9-NOVECTOR: blr
; ;
; CHECK-P9-LABEL: bar0: ; CHECK-P9-LABEL: bar0:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3) ; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: lxvx vs0, 0, r3 ; CHECK-P9: lxv vs0, 0(r3)
; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: lfd f1, 0(r3) ; CHECK-P9: lfd f1, 0(r3)
; CHECK-P9: addis r3, r2, .LC2@toc@ha ; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxswapd vs1, f1
; CHECK-P9: xxpermdi vs0, vs0, vs1, 1 ; CHECK-P9: xxpermdi vs0, vs0, vs1, 1
; CHECK-P9: stxvx vs0, 0, r3 ; CHECK-P9: stxv vs0, 0(r3)
; CHECK-P9: blr ; CHECK-P9: blr
entry: entry:
%0 = load <2 x double>, <2 x double>* @x, align 16 %0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 0 %vecins = insertelement <2 x double> %0, double %1, i32 0
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }
Show All 20 Lines
; CHECK-P9-NOVECTOR: xxpermdi vs0, vs0, vs1, 1 ; CHECK-P9-NOVECTOR: xxpermdi vs0, vs0, vs1, 1
; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3 ; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
; CHECK-P9-NOVECTOR: blr ; CHECK-P9-NOVECTOR: blr
; ;
; CHECK-P9-LABEL: bar1: ; CHECK-P9-LABEL: bar1:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: addis r3, r2, .LC0@toc@ha
; CHECK-P9: ld r3, .LC0@toc@l(r3) ; CHECK-P9: ld r3, .LC0@toc@l(r3)
; CHECK-P9: lxvx vs0, 0, r3 ; CHECK-P9: lxv vs0, 0(r3)
; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: addis r3, r2, .LC1@toc@ha
; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: ld r3, .LC1@toc@l(r3)
; CHECK-P9: lfd f1, 0(r3) ; CHECK-P9: lfd f1, 0(r3)
; CHECK-P9: addis r3, r2, .LC2@toc@ha ; CHECK-P9: addis r3, r2, .LC2@toc@ha
; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: ld r3, .LC2@toc@l(r3)
; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxswapd vs1, f1
; CHECK-P9: xxmrgld vs0, vs1, vs0 ; CHECK-P9: xxmrgld vs0, vs1, vs0
; CHECK-P9: stxvx vs0, 0, r3 ; CHECK-P9: stxv vs0, 0(r3)
; CHECK-P9: blr ; CHECK-P9: blr
entry: entry:
%0 = load <2 x double>, <2 x double>* @x, align 16 %0 = load <2 x double>, <2 x double>* @x, align 16
%1 = load double, double* @y, align 8 %1 = load double, double* @y, align 8
%vecins = insertelement <2 x double> %0, double %1, i32 1 %vecins = insertelement <2 x double> %0, double %1, i32 1
store <2 x double> %vecins, <2 x double>* @z, align 16 store <2 x double> %vecins, <2 x double>* @z, align 16
ret void ret void
} }

llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll

Show All 17 Lines
; CHECK-LABEL: speculatable_callee_non_return_use_only: ; CHECK-LABEL: speculatable_callee_non_return_use_only:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: stfdx f1, 0, r30 ; CHECK-NEXT: stfd f1, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call double @callee(double %a) #2 %call = tail call double @callee(double %a) #2
store double %call, double* %res, align 8 store double %call, double* %res, align 8
ret void ret void
} }
; Callee should not be tail called since it is not at a tail call position. ; Callee should not be tail called since it is not at a tail call position.
define dso_local double @speculatable_callee_multi_use (double* nocapture %res, double %a) #0 { define dso_local double @speculatable_callee_multi_use (double* nocapture %res, double %a) #0 {
; CHECK-LABEL: speculatable_callee_multi_use: ; CHECK-LABEL: speculatable_callee_multi_use:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: stfdx f1, 0, r30 ; CHECK-NEXT: stfd f1, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call double @callee(double %a) #2 %call = tail call double @callee(double %a) #2
store double %call, double* %res, align 8 store double %call, double* %res, align 8
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llvm/test/CodeGen/PowerPC/toc-float.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: lfs 0, FArr@toc@l+12(3) ; CHECK-P9-NEXT: lfs 0, FArr@toc@l+12(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: lfs 1, .LCPI2_0@toc@l(3) ; CHECK-P9-NEXT: lfs 1, .LCPI2_0@toc@l(3)
; CHECK-P9-NEXT: xsaddsp 1, 0, 1 ; CHECK-P9-NEXT: xsaddsp 1, 0, 1
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: floatConstantArray: ; CHECK-P8-LABEL: floatConstantArray:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis 3, 2, FArr@toc@ha ; CHECK-P8-NEXT: addis 3, 2, FArr@toc@ha+12
; CHECK-P8-NEXT: addis 4, 2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis 4, 2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: addi 3, 3, FArr@toc@l ; CHECK-P8-NEXT: lfs 0, FArr@toc@l+12(3)
; CHECK-P8-NEXT: lfs 1, .LCPI2_0@toc@l(4) ; CHECK-P8-NEXT: lfs 1, .LCPI2_0@toc@l(4)
; CHECK-P8-NEXT: lfs 0, 12(3)
; CHECK-P8-NEXT: xsaddsp 1, 0, 1 ; CHECK-P8-NEXT: xsaddsp 1, 0, 1
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4 %1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4
%2 = fadd float %1, 0x400B333340000000 %2 = fadd float %1, 0x400B333340000000
ret float %2 ret float %2
} }
define float @floatConstant() { define float @floatConstant() {
Show All 22 Lines
; CHECK-P9-NEXT: lfd 0, d@toc@l+24(3) ; CHECK-P9-NEXT: lfd 0, d@toc@l+24(3)
; CHECK-P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: lfd 1, .LCPI4_0@toc@l(3) ; CHECK-P9-NEXT: lfd 1, .LCPI4_0@toc@l(3)
; CHECK-P9-NEXT: xsadddp 1, 0, 1 ; CHECK-P9-NEXT: xsadddp 1, 0, 1
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: doubleConstantArray: ; CHECK-P8-LABEL: doubleConstantArray:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis 3, 2, d@toc@ha ; CHECK-P8-NEXT: addis 3, 2, d@toc@ha+24
; CHECK-P8-NEXT: addis 4, 2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis 4, 2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: addi 3, 3, d@toc@l ; CHECK-P8-NEXT: lfd 0, d@toc@l+24(3)
; CHECK-P8-NEXT: lfd 1, .LCPI4_0@toc@l(4) ; CHECK-P8-NEXT: lfd 1, .LCPI4_0@toc@l(4)
; CHECK-P8-NEXT: lfd 0, 24(3)
; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: xsadddp 1, 0, 1
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8 %1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8
%2 = fadd double %1, 6.880000e+00 %2 = fadd double %1, 6.880000e+00
ret double %2 ret double %2
} }
@arr = hidden local_unnamed_addr global [20000 x double] zeroinitializer, align 8 @arr = hidden local_unnamed_addr global [20000 x double] zeroinitializer, align 8
Show All 14 Lines
; ;
; CHECK-P8-LABEL: doubleLargeConstantArray: ; CHECK-P8-LABEL: doubleLargeConstantArray:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: addis 3, 2, arr@toc@ha ; CHECK-P8-NEXT: addis 3, 2, arr@toc@ha
; CHECK-P8-NEXT: li 4, 0 ; CHECK-P8-NEXT: li 4, 0
; CHECK-P8-NEXT: addis 5, 2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis 5, 2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: addi 3, 3, arr@toc@l ; CHECK-P8-NEXT: addi 3, 3, arr@toc@l
; CHECK-P8-NEXT: ori 4, 4, 32768 ; CHECK-P8-NEXT: ori 4, 4, 32768
; CHECK-P8-NEXT: lfdx 0, 3, 4
; CHECK-P8-NEXT: lfd 1, .LCPI5_0@toc@l(5) ; CHECK-P8-NEXT: lfd 1, .LCPI5_0@toc@l(5)
; CHECK-P8-NEXT: lfdx 0, 3, 4
; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: xsadddp 1, 0, 1
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8 %1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8
%2 = fadd double %1, 6.880000e+00 %2 = fadd double %1, 6.880000e+00
ret double %2 ret double %2
} }
@vec_arr = global [10 x <4 x i32>] zeroinitializer, align 16 @vec_arr = global [10 x <4 x i32>] zeroinitializer, align 16
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llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
%1 = load <2 x double>, <2 x double>* %0, align 16 %1 = load <2 x double>, <2 x double>* %0, align 16
ret <2 x double> %1 ret <2 x double> %1
} }
; ISEL matches address mode xoaddr. ; ISEL matches address mode xoaddr.
define void @test_xoaddr(i32* %arr, i32* %arrTo) { define void @test_xoaddr(i32* %arr, i32* %arrTo) {
; CHECK-LABEL: test_xoaddr: ; CHECK-LABEL: test_xoaddr:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: li r5, 8
; CHECK-NEXT: addi r4, r4, 4 ; CHECK-NEXT: lxvx vs0, r3, r5
; CHECK-NEXT: lxvx vs0, 0, r3 ; CHECK-NEXT: li r3, 4
; CHECK-NEXT: stxvx vs0, 0, r4 ; CHECK-NEXT: stxvx vs0, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1 %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1
%0 = bitcast i32* %arrayidx to <4 x i32>* %0 = bitcast i32* %arrayidx to <4 x i32>*
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
%1 = bitcast i32* %arrayidx1 to <4 x i32>* %1 = bitcast i32* %arrayidx1 to <4 x i32>*
%2 = load <4 x i32>, <4 x i32>* %1, align 8 %2 = load <4 x i32>, <4 x i32>* %1, align 8
store <4 x i32> %2, <4 x i32>* %0, align 8 store <4 x i32> %2, <4 x i32>* %0, align 8
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llvm/test/CodeGen/PowerPC/unaligned.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-LABEL: foo5: ; CHECK-LABEL: foo5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfd 0, 0(3) ; CHECK-NEXT: lfd 0, 0(3)
; CHECK-NEXT: stfd 0, 0(4) ; CHECK-NEXT: stfd 0, 0(4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-VSX-LABEL: foo5: ; CHECK-VSX-LABEL: foo5:
; CHECK-VSX: # %bb.0: # %entry ; CHECK-VSX: # %bb.0: # %entry
; CHECK-VSX-NEXT: lfdx 0, 0, 3 ; CHECK-VSX-NEXT: lfd 0, 0(3)
; CHECK-VSX-NEXT: stfdx 0, 0, 4 ; CHECK-VSX-NEXT: stfd 0, 0(4)
; CHECK-VSX-NEXT: blr ; CHECK-VSX-NEXT: blr
entry: entry:
%v = load double, double* %p, align 1 %v = load double, double* %p, align 1
store double %v, double* %r, align 1 store double %v, double* %r, align 1
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/vavg.ll

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
} }
define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) { define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) {
; CHECK-P9-LABEL: test_v8i16_sign_negative: ; CHECK-P9-LABEL: test_v8i16_sign_negative:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vadduhm 2, 2, 3
; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx 35, 0, 3 ; CHECK-P9-NEXT: lxv 35, 0(3)
; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vadduhm 2, 2, 3
; CHECK-P9-NEXT: vspltish 3, 1 ; CHECK-P9-NEXT: vspltish 3, 1
; CHECK-P9-NEXT: vsrah 2, 2, 3 ; CHECK-P9-NEXT: vsrah 2, 2, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LABEL: test_v8i16_sign_negative: ; CHECK-P8-LABEL: test_v8i16_sign_negative:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha
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llvm/test/CodeGen/PowerPC/vec-itofp.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8: ; CHECK-P9-LABEL: test8:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8: ; CHECK-BE-LABEL: test8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v2 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = uitofp <8 x i16> %0 to <8 x double> %1 = uitofp <8 x i16> %0 to <8 x double>
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; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4: ; CHECK-P9-LABEL: test4:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4: ; CHECK-BE-LABEL: test4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = uitofp <4 x i16> %0 to <4 x double> %1 = uitofp <4 x i16> %0 to <4 x double>
Show All 16 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2: ; CHECK-P9-LABEL: test2:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v2 ; CHECK-P9-NEXT: xvcvuxddp vs0, v2
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2: ; CHECK-BE-LABEL: test2:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v2 ; CHECK-BE-NEXT: xvcvuxddp vs0, v2
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16 %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
%1 = uitofp <2 x i16> %0 to <2 x double> %1 = uitofp <2 x i16> %0 to <2 x double>
store <2 x double> %1, <2 x double>* %Sink, align 16 store <2 x double> %1, <2 x double>* %Sink, align 16
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: stest8: ; CHECK-P9-LABEL: stest8:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: stest8: ; CHECK-BE-LABEL: stest8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
Show All 31 Lines
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: stest4: ; CHECK-P9-LABEL: stest4:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: stest4: ; CHECK-BE-LABEL: stest4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
Show All 21 Lines
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: stest2: ; CHECK-P9-LABEL: stest2:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs0, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v2
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: stest2: ; CHECK-BE-LABEL: stest2:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs0, v2 ; CHECK-BE-NEXT: xvcvsxddp vs0, v2
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16 %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
%1 = sitofp <2 x i16> %0 to <2 x double> %1 = sitofp <2 x i16> %0 to <2 x double>
store <2 x double> %1, <2 x double>* %Sink, align 16 store <2 x double> %1, <2 x double>* %Sink, align 16
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = uitofp <4 x i16> %0 to <4 x float> %1 = uitofp <4 x i16> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 22 Lines
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <8 x i16> %a to <8 x float> %0 = uitofp <8 x i16> %a to <8 x float>
store <8 x float> %0, <8 x float>* %agg.result, align 32 store <8 x float> %0, <8 x float>* %agg.result, align 32
Show All 31 Lines
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r4 ; CHECK-P9-NEXT: lxv v4, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: xvcvuxwsp vs0, v0 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0
; CHECK-P9-NEXT: lxvx v0, 0, r4 ; CHECK-P9-NEXT: lxv v0, 0(r4)
; CHECK-P9-NEXT: vperm v3, v5, v3, v0 ; CHECK-P9-NEXT: vperm v3, v5, v3, v0
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v4 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
; CHECK-P9-NEXT: vperm v2, v5, v2, v0 ; CHECK-P9-NEXT: vperm v2, v5, v2, v0
; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: xvcvuxwsp vs0, v0 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0
; CHECK-BE-NEXT: lxvx v0, 0, r4 ; CHECK-BE-NEXT: lxv v0, 0(r4)
; CHECK-BE-NEXT: vperm v3, v5, v3, v0 ; CHECK-BE-NEXT: vperm v3, v5, v3, v0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
; CHECK-BE-NEXT: vperm v3, v2, v5, v4 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
; CHECK-BE-NEXT: vperm v2, v5, v2, v0 ; CHECK-BE-NEXT: vperm v2, v5, v2, v0
; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
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; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4
; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4
; CHECK-BE-NEXT: vmrghh v3, v3, v3 ; CHECK-BE-NEXT: vmrghh v3, v3, v3
; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vmrghh v2, v2, v2
; CHECK-BE-NEXT: vextsh2w v0, v0 ; CHECK-BE-NEXT: vextsh2w v0, v0
; CHECK-BE-NEXT: vextsh2w v4, v4 ; CHECK-BE-NEXT: vextsh2w v4, v4
; CHECK-BE-NEXT: vextsh2w v3, v3 ; CHECK-BE-NEXT: vextsh2w v3, v3
; CHECK-BE-NEXT: vextsh2w v2, v2 ; CHECK-BE-NEXT: vextsh2w v2, v2
Show All 15 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Show All 21 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = uitofp <2 x i16> %0 to <2 x double> %1 = uitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 21 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = uitofp <4 x i16> %0 to <4 x double> %1 = uitofp <4 x i16> %0 to <4 x double>
Show All 38 Lines
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v2 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <8 x i16> %a to <8 x double> %0 = uitofp <8 x i16> %a to <8 x double>
store <8 x double> %0, <8 x double>* %agg.result, align 64 store <8 x double> %0, <8 x double>* %agg.result, align 64
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 16(r4) ; CHECK-P9-NEXT: lxv v2, 16(r4)
; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v4, 0, r4 ; CHECK-P9-NEXT: lxv v4, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
; CHECK-P9-NEXT: xvcvuxddp vs0, v0 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0
; CHECK-P9-NEXT: lxvx v0, 0, r4 ; CHECK-P9-NEXT: lxv v0, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v1, v5, v3, v0 ; CHECK-P9-NEXT: vperm v1, v5, v3, v0
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v1 ; CHECK-P9-NEXT: xvcvuxddp vs1, v1
; CHECK-P9-NEXT: lxvx v1, 0, r4 ; CHECK-P9-NEXT: lxv v1, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v6, v5, v3, v1 ; CHECK-P9-NEXT: vperm v6, v5, v3, v1
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v6 ; CHECK-P9-NEXT: xvcvuxddp vs2, v6
; CHECK-P9-NEXT: lxvx v6, 0, r4 ; CHECK-P9-NEXT: lxv v6, 0(r4)
; CHECK-P9-NEXT: vperm v3, v5, v3, v6 ; CHECK-P9-NEXT: vperm v3, v5, v3, v6
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v3 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v4 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
; CHECK-P9-NEXT: xvcvuxddp vs4, v3 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v0 ; CHECK-P9-NEXT: vperm v3, v5, v2, v0
; CHECK-P9-NEXT: xvcvuxddp vs5, v3 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
; CHECK-P9-NEXT: vperm v3, v5, v2, v1 ; CHECK-P9-NEXT: vperm v3, v5, v2, v1
Show All 9 Lines
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 16(r4) ; CHECK-BE-NEXT: lxv v2, 16(r4)
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: vperm v0, v3, v5, v4
; CHECK-BE-NEXT: xvcvuxddp vs0, v0 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0
; CHECK-BE-NEXT: lxvx v0, 0, r4 ; CHECK-BE-NEXT: lxv v0, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: vperm v1, v5, v3, v0
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v1 ; CHECK-BE-NEXT: xvcvuxddp vs1, v1
; CHECK-BE-NEXT: lxvx v1, 0, r4 ; CHECK-BE-NEXT: lxv v1, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v6, v5, v3, v1 ; CHECK-BE-NEXT: vperm v6, v5, v3, v1
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v6 ; CHECK-BE-NEXT: xvcvuxddp vs2, v6
; CHECK-BE-NEXT: lxvx v6, 0, r4 ; CHECK-BE-NEXT: lxv v6, 0(r4)
; CHECK-BE-NEXT: vperm v3, v5, v3, v6 ; CHECK-BE-NEXT: vperm v3, v5, v3, v6
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v3 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
; CHECK-BE-NEXT: vperm v3, v2, v5, v4 ; CHECK-BE-NEXT: vperm v3, v2, v5, v4
; CHECK-BE-NEXT: xvcvuxddp vs4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
; CHECK-BE-NEXT: vperm v3, v5, v2, v0 ; CHECK-BE-NEXT: vperm v3, v5, v2, v0
; CHECK-BE-NEXT: xvcvuxddp vs5, v3 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
; CHECK-BE-NEXT: vperm v3, v5, v2, v1 ; CHECK-BE-NEXT: vperm v3, v5, v2, v1
Show All 30 Lines
; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = sitofp <2 x i16> %0 to <2 x double> %1 = sitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
Show All 28 Lines
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <8 x i16> %a to <8 x double> %0 = sitofp <8 x i16> %a to <8 x double>
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: lxv v2, 0(r4)
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r5 ; CHECK-P9-NEXT: lxv v3, 0(r5)
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-P9-NEXT: lxvx v5, 0, r5 ; CHECK-P9-NEXT: lxv v5, 0(r5)
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: vperm v4, v2, v2, v3 ; CHECK-P9-NEXT: vperm v4, v2, v2, v3
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: lxvx v0, 0, r5 ; CHECK-P9-NEXT: lxv v0, 0(r5)
; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: xvcvsxddp vs0, v4 ; CHECK-P9-NEXT: xvcvsxddp vs0, v4
; CHECK-P9-NEXT: vperm v4, v2, v2, v5 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5
; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l
; CHECK-P9-NEXT: lxvx v1, 0, r5 ; CHECK-P9-NEXT: lxv v1, 0(r5)
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4
; CHECK-P9-NEXT: vperm v4, v2, v2, v0 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0
; CHECK-P9-NEXT: vperm v2, v2, v2, v1 ; CHECK-P9-NEXT: vperm v2, v2, v2, v1
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: vextsh2d v4, v4
; CHECK-P9-NEXT: xvcvsxddp vs2, v4 ; CHECK-P9-NEXT: xvcvsxddp vs2, v4
; CHECK-P9-NEXT: lxv v4, 16(r4) ; CHECK-P9-NEXT: lxv v4, 16(r4)
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; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: lxv v1, 16(r4) ; CHECK-BE-NEXT: lxv v1, 16(r4)
; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: lxvx v2, 0, r5 ; CHECK-BE-NEXT: lxv v2, 0(r5)
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r5 ; CHECK-BE-NEXT: lxv v3, 0(r5)
; CHECK-BE-NEXT: vperm v0, v5, v4, v2 ; CHECK-BE-NEXT: vperm v0, v5, v4, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v2 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs2, v2
; CHECK-BE-NEXT: vperm v2, v5, v1, v3 ; CHECK-BE-NEXT: vperm v2, v5, v1, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v0 ; CHECK-BE-NEXT: xvcvsxddp vs0, v0
; CHECK-BE-NEXT: vperm v0, v5, v4, v3 ; CHECK-BE-NEXT: vperm v0, v5, v4, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: lxvx v2, 0, r4 ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: xvcvsxddp vs1, v0 ; CHECK-BE-NEXT: xvcvsxddp vs1, v0
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vperm v3, v4, v4, v2 ; CHECK-BE-NEXT: vperm v3, v4, v4, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v2 ; CHECK-BE-NEXT: vperm v2, v1, v1, v2
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs4, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: xvcvsxddp vs6, v2 ; CHECK-BE-NEXT: xvcvsxddp vs6, v2
; CHECK-BE-NEXT: vperm v4, v4, v4, v3 ; CHECK-BE-NEXT: vperm v4, v4, v4, v3
; CHECK-BE-NEXT: vperm v2, v1, v1, v3 ; CHECK-BE-NEXT: vperm v2, v1, v1, v3
; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsh2d v4, v4 ; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs5, v4 ; CHECK-BE-NEXT: xvcvsxddp vs5, v4
Show All 10 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = uitofp <4 x i8> %0 to <4 x float> %1 = uitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
Show All 19 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = uitofp <8 x i8> %0 to <8 x float> %1 = uitofp <8 x i8> %0 to <8 x float>
Show All 34 Lines
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <16 x i8> %a to <16 x float> %0 = uitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
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; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp v2, v2 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = sitofp <4 x i8> %0 to <4 x float> %1 = sitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
Show All 24 Lines
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
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; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stvx v2, r3, r4 ; CHECK-P8-NEXT: stvx v2, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
; CHECK-P9-NEXT: xvcvsxwsp vs2, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs2, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x float> %0 = sitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

Show All 21 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = uitofp <2 x i8> %0 to <2 x double> %1 = uitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
Show All 21 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r4 ; CHECK-P9-NEXT: mtvsrws v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v2 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r4 ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v2 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = uitofp <4 x i8> %0 to <4 x double> %1 = uitofp <4 x i8> %0 to <4 x double>
Show All 40 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v2 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v2 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = uitofp <8 x i8> %0 to <8 x double> %1 = uitofp <8 x i8> %0 to <8 x double>
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxddp vs0, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: xvcvuxddp vs1, v3 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: xvcvuxddp vs2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: xvcvuxddp vs3, v3 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: xvcvuxddp vs4, v3 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: xvcvuxddp vs5, v3 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: xvcvuxddp vs6, v3 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: xvcvuxddp vs7, v2 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
; CHECK-BE-NEXT: xvcvuxddp vs0, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: xvcvuxddp vs1, v3 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: xvcvuxddp vs2, v3 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvuxddp vs3, v3 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: xvcvuxddp vs4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: xvcvuxddp vs5, v3 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: xvcvuxddp vs6, v3 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: xvcvuxddp vs7, v2 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 112(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = uitofp <16 x i8> %a to <16 x double> %0 = uitofp <16 x i8> %a to <16 x double>
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
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; CHECK-P8-NEXT: xvcvsxddp v2, v2 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxv v3, 0(r3)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r3 ; CHECK-BE-NEXT: lxv v3, 0(r3)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = sitofp <2 x i8> %0 to <2 x double> %1 = sitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
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; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r4 ; CHECK-P9-NEXT: mtvsrws v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r4 ; CHECK-BE-NEXT: mtvsrws v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 0(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
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; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: mtvsrd v2, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 0(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 32(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
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; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs0, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: stxv vs0, 0(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs1, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs2, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: stxv vs2, 32(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs4, v3 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: stxv vs4, 64(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs5, v3 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: stxv vs5, 80(r3)
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
; CHECK-P9-NEXT: xvcvsxddp vs6, v3 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxv v3, 0(r4)
; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs0, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs1, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 48(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs2, v4 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4
; CHECK-BE-NEXT: lxvx v4, 0, r4 ; CHECK-BE-NEXT: lxv v4, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 80(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 112(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs4, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs5, v3 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 32(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs6, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: lxvx v3, 0, r4 ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: stxv vs7, 96(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x double> %0 = sitofp <16 x i8> %a to <16 x double>
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_int_ext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
define <4 x i32> @vextsb2wLE(<16 x i8> %a) { define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
; CHECK-LE-LABEL: vextsb2wLE: ; CHECK-LE-LABEL: vextsb2wLE:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: vextsb2w 2, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: vextsb2wLE: ; CHECK-BE-LABEL: vextsb2wLE:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: vextsb2w 2, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 0 %vecext = extractelement <16 x i8> %a, i32 0
%conv = sext i8 %vecext to i32 %conv = sext i8 %vecext to i32
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
Show All 14 Lines
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: vextsb2d 2, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: vextsb2dLE: ; CHECK-BE-LABEL: vextsb2dLE:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: vextsb2d 2, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 0 %vecext = extractelement <16 x i8> %a, i32 0
%conv = sext i8 %vecext to i64 %conv = sext i8 %vecext to i64
%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
%vecext1 = extractelement <16 x i8> %a, i32 8 %vecext1 = extractelement <16 x i8> %a, i32 8
%conv2 = sext i8 %vecext1 to i64 %conv2 = sext i8 %vecext1 to i64
%vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
ret <2 x i64> %vecinit3 ret <2 x i64> %vecinit3
} }
define <4 x i32> @vextsh2wLE(<8 x i16> %a) { define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
; CHECK-LE-LABEL: vextsh2wLE: ; CHECK-LE-LABEL: vextsh2wLE:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: vextsh2w 2, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: vextsh2wLE: ; CHECK-BE-LABEL: vextsh2wLE:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: vextsh2w 2, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 0 %vecext = extractelement <8 x i16> %a, i32 0
%conv = sext i16 %vecext to i32 %conv = sext i16 %vecext to i32
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
Show All 14 Lines
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: vextsh2d 2, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: vextsh2dLE: ; CHECK-BE-LABEL: vextsh2dLE:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxvx 35, 0, 3 ; CHECK-BE-NEXT: lxv 35, 0(3)
; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: vextsh2d 2, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 0 %vecext = extractelement <8 x i16> %a, i32 0
%conv = sext i16 %vecext to i64 %conv = sext i16 %vecext to i64
%vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
▲ Show 20 Lines • Show All 300 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvdivdp 34, 1, 0 ; PC64LE-NEXT: xvdivdp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fdiv_v2f64: ; PC64LE9-LABEL: constrained_vector_fdiv_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI1_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI1_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI1_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI1_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI1_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI1_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: xvdivdp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%div = call <2 x double> @llvm.experimental.constrained.fdiv.v2f64( %div = call <2 x double> @llvm.experimental.constrained.fdiv.v2f64(
<2 x double> <double 1.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 2.000000e+00>,
<2 x double> <double 1.000000e+01, double 1.000000e+01>, <2 x double> <double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %div ret <2 x double> %div
} }
define <3 x float> @constrained_vector_fdiv_v3f32() #0 { define <3 x float> @constrained_vector_fdiv_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fdiv_v3f32: ; PC64LE-LABEL: constrained_vector_fdiv_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI2_3@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI2_3@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI2_2@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI2_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI2_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI2_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI2_3@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI2_3@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI2_2@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI2_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI2_1@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI2_1@toc@ha
; PC64LE-NEXT: xsdivsp 1, 1, 0
; PC64LE-NEXT: lfs 3, .LCPI2_1@toc@l(3) ; PC64LE-NEXT: lfs 3, .LCPI2_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI2_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI2_4@toc@ha
; PC64LE-NEXT: xsdivsp 2, 2, 0 ; PC64LE-NEXT: xsdivsp 1, 1, 0
; PC64LE-NEXT: addi 3, 3, .LCPI2_4@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI2_4@toc@l
; PC64LE-NEXT: xsdivsp 2, 2, 0
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xsdivsp 0, 3, 0 ; PC64LE-NEXT: xsdivsp 0, 3, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 34, 1, 1, 3
; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
Show All 9 Lines
; PC64LE9-NEXT: lfs 1, .LCPI2_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI2_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI2_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI2_2@toc@ha
; PC64LE9-NEXT: xsdivsp 1, 1, 0 ; PC64LE9-NEXT: xsdivsp 1, 1, 0
; PC64LE9-NEXT: lfs 2, .LCPI2_2@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI2_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI2_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI2_3@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI2_3@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI2_3@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI2_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI2_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI2_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI2_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xsdivsp 2, 2, 0 ; PC64LE9-NEXT: xsdivsp 2, 2, 0
; PC64LE9-NEXT: xsdivsp 0, 3, 0 ; PC64LE9-NEXT: xsdivsp 0, 3, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xscvdpspn 0, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
Show All 35 Lines
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI3_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI3_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI3_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI3_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI3_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI3_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI3_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI3_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI3_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI3_2@toc@l
; PC64LE9-NEXT: xsdivdp 3, 1, 0 ; PC64LE9-NEXT: xsdivdp 3, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI3_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI3_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI3_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI3_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvdivdp 2, 1, 0 ; PC64LE9-NEXT: xvdivdp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%div = call <3 x double> @llvm.experimental.constrained.fdiv.v3f64( %div = call <3 x double> @llvm.experimental.constrained.fdiv.v3f64(
<3 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00>, <3 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00>,
Show All 21 Lines
; PC64LE-NEXT: xvdivdp 35, 1, 0 ; PC64LE-NEXT: xvdivdp 35, 1, 0
; PC64LE-NEXT: xvdivdp 34, 2, 0 ; PC64LE-NEXT: xvdivdp 34, 2, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fdiv_v4f64: ; PC64LE9-LABEL: constrained_vector_fdiv_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI4_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI4_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI4_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI4_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI4_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI4_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI4_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI4_2@toc@l
; PC64LE9-NEXT: xvdivdp 35, 1, 0 ; PC64LE9-NEXT: xvdivdp 35, 1, 0
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: xvdivdp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64( %div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00, <4 x double> <double 1.000000e+00, double 2.000000e+00,
double 3.000000e+00, double 4.000000e+00>, double 3.000000e+00, double 4.000000e+00>,
<4 x double> <double 1.000000e+01, double 1.000000e+01, <4 x double> <double 1.000000e+01, double 1.000000e+01,
double 1.000000e+01, double 1.000000e+01>, double 1.000000e+01, double 1.000000e+01>,
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: addis 4, 2, .LCPI6_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI6_1@toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI6_1@toc@l(4) ; PC64LE-NEXT: lfs 31, .LCPI6_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI6_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI6_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI6_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI6_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI6_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI6_2@toc@l(3)
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
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; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: addis 4, 2, .LCPI7_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI7_1@toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI7_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI7_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI7_1@toc@l(4) ; PC64LE-NEXT: lfs 31, .LCPI7_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI7_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI7_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI7_2@toc@ha
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: addis 3, 2, .LCPI7_2@toc@ha
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfs 1, .LCPI7_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI7_2@toc@l(3)
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI7_3@toc@ha
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: addis 3, 2, .LCPI7_3@toc@ha
; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: fmr 29, 1
; PC64LE-NEXT: lfs 1, .LCPI7_3@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI7_3@toc@l(3)
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 29 ; PC64LE-NEXT: xscvdpspn 0, 29
; PC64LE-NEXT: addis 3, 2, .LCPI7_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI7_4@toc@ha
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI7_4@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI7_4@toc@l
Show All 37 Lines
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI7_3@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI7_3@toc@l(3)
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
Show All 16 Lines
; PC64LE-LABEL: constrained_vector_frem_v3f64: ; PC64LE-LABEL: constrained_vector_frem_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: addis 4, 2, .LCPI8_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI8_1@toc@ha
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfs 31, .LCPI8_1@toc@l(4)
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI8_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI8_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI8_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI8_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI8_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI8_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI8_2@toc@l(3)
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; PC64LE-LABEL: constrained_vector_frem_v4f64: ; PC64LE-LABEL: constrained_vector_frem_v4f64:
; PC64LE: # %bb.0: ; PC64LE: # %bb.0:
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: addis 4, 2, .LCPI9_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI9_1@toc@ha
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfs 31, .LCPI9_1@toc@l(4)
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI9_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI9_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI9_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI9_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI9_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI9_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI9_2@toc@l(3)
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: addis 3, 2, .LCPI9_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI9_3@toc@ha
; PC64LE-NEXT: xxmrghd 63, 1, 0 ; PC64LE-NEXT: xxmrghd 63, 1, 0
; PC64LE-NEXT: lfs 1, .LCPI9_3@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI9_3@toc@l(3)
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI9_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI9_4@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI9_4@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI9_4@toc@l(3)
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: vmr 2, 31 ; PC64LE-NEXT: vmr 2, 31
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvmuldp 34, 1, 0 ; PC64LE-NEXT: xvmuldp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fmul_v2f64: ; PC64LE9-LABEL: constrained_vector_fmul_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI11_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI11_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI11_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI11_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI11_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI11_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI11_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI11_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: xvmuldp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64( %mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, <2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 2.000000e+00, double 3.000000e+00>, <2 x double> <double 2.000000e+00, double 3.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %mul ret <2 x double> %mul
} }
define <3 x float> @constrained_vector_fmul_v3f32() #0 { define <3 x float> @constrained_vector_fmul_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fmul_v3f32: ; PC64LE-LABEL: constrained_vector_fmul_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI12_1@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI12_1@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI12_3@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI12_3@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI12_2@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI12_1@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI12_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI12_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI12_3@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI12_3@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI12_2@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI12_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha
; PC64LE-NEXT: xsmulsp 1, 0, 1
; PC64LE-NEXT: lfs 3, .LCPI12_0@toc@l(3) ; PC64LE-NEXT: lfs 3, .LCPI12_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI12_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI12_4@toc@ha
; PC64LE-NEXT: xsmulsp 2, 0, 2 ; PC64LE-NEXT: xsmulsp 1, 0, 1
; PC64LE-NEXT: addi 3, 3, .LCPI12_4@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI12_4@toc@l
; PC64LE-NEXT: xsmulsp 2, 0, 2
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xsmulsp 0, 0, 3 ; PC64LE-NEXT: xsmulsp 0, 0, 3
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 34, 1, 1, 3
; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
Show All 9 Lines
; PC64LE9-NEXT: lfs 1, .LCPI12_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI12_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI12_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI12_2@toc@ha
; PC64LE9-NEXT: xsmulsp 0, 1, 0 ; PC64LE9-NEXT: xsmulsp 0, 1, 0
; PC64LE9-NEXT: lfs 2, .LCPI12_2@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI12_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI12_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI12_3@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI12_3@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI12_3@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI12_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI12_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI12_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI12_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xsmulsp 2, 1, 2 ; PC64LE9-NEXT: xsmulsp 2, 1, 2
; PC64LE9-NEXT: xsmulsp 1, 1, 3 ; PC64LE9-NEXT: xsmulsp 1, 1, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 1, 1
; PC64LE9-NEXT: xxsldwi 34, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 34, 1, 1, 3
; PC64LE9-NEXT: xscvdpspn 1, 2 ; PC64LE9-NEXT: xscvdpspn 1, 2
; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
Show All 36 Lines
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI13_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI13_0@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI13_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI13_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI13_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI13_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI13_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI13_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI13_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI13_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI13_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI13_2@toc@l
; PC64LE9-NEXT: xsmuldp 3, 0, 1 ; PC64LE9-NEXT: xsmuldp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI13_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI13_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI13_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI13_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmuldp 2, 1, 0 ; PC64LE9-NEXT: xvmuldp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%mul = call <3 x double> @llvm.experimental.constrained.fmul.v3f64( %mul = call <3 x double> @llvm.experimental.constrained.fmul.v3f64(
<3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
Show All 22 Lines
; PC64LE-NEXT: xvmuldp 35, 1, 0 ; PC64LE-NEXT: xvmuldp 35, 1, 0
; PC64LE-NEXT: xvmuldp 34, 1, 2 ; PC64LE-NEXT: xvmuldp 34, 1, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fmul_v4f64: ; PC64LE9-LABEL: constrained_vector_fmul_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI14_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI14_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI14_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI14_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI14_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI14_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI14_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI14_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI14_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI14_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI14_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI14_2@toc@l
; PC64LE9-NEXT: xvmuldp 35, 1, 0 ; PC64LE9-NEXT: xvmuldp 35, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: xvmuldp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64( %mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 2.000000e+00, double 3.000000e+00, <4 x double> <double 2.000000e+00, double 3.000000e+00,
double 4.000000e+00, double 5.000000e+00>, double 4.000000e+00, double 5.000000e+00>,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvadddp 34, 1, 0 ; PC64LE-NEXT: xvadddp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v2f64: ; PC64LE9-LABEL: constrained_vector_fadd_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI16_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI16_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI16_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI16_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI16_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI16_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI16_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: xvadddp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64( %add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, <2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %add ret <2 x double> %add
} }
define <3 x float> @constrained_vector_fadd_v3f32() #0 { define <3 x float> @constrained_vector_fadd_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fadd_v3f32: ; PC64LE-LABEL: constrained_vector_fadd_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI17_2@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI17_2@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI17_1@toc@ha
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: lfs 0, .LCPI17_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI17_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI17_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI17_2@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI17_2@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI17_1@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI17_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI17_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI17_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI17_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI17_3@toc@l
; PC64LE-NEXT: xsaddsp 1, 0, 1 ; PC64LE-NEXT: xsaddsp 1, 0, 1
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xsaddsp 2, 0, 2 ; PC64LE-NEXT: xsaddsp 2, 0, 2
; PC64LE-NEXT: xsaddsp 0, 0, 3 ; PC64LE-NEXT: xsaddsp 0, 0, 3
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 2, 2
Show All 12 Lines
; PC64LE9-NEXT: lfs 0, .LCPI17_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI17_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI17_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI17_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI17_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI17_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_2@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI17_2@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI17_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l
; PC64LE9-NEXT: xsaddsp 1, 0, 1 ; PC64LE9-NEXT: xsaddsp 1, 0, 1
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xsaddsp 2, 0, 2 ; PC64LE9-NEXT: xsaddsp 2, 0, 2
; PC64LE9-NEXT: xsaddsp 0, 0, 3 ; PC64LE9-NEXT: xsaddsp 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xscvdpspn 0, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
Show All 34 Lines
; PC64LE9-LABEL: constrained_vector_fadd_v3f64: ; PC64LE9-LABEL: constrained_vector_fadd_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1 ; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfd 0, .LCPI18_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI18_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l
; PC64LE9-NEXT: xsadddp 3, 0, 1 ; PC64LE9-NEXT: xsadddp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvadddp 2, 1, 0 ; PC64LE9-NEXT: xvadddp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%add = call <3 x double> @llvm.experimental.constrained.fadd.v3f64( %add = call <3 x double> @llvm.experimental.constrained.fadd.v3f64(
<3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <3 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
Show All 22 Lines
; PC64LE-NEXT: xvadddp 35, 1, 0 ; PC64LE-NEXT: xvadddp 35, 1, 0
; PC64LE-NEXT: xvadddp 34, 1, 2 ; PC64LE-NEXT: xvadddp 34, 1, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v4f64: ; PC64LE9-LABEL: constrained_vector_fadd_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI19_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI19_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI19_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI19_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI19_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI19_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI19_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI19_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI19_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI19_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI19_2@toc@l
; PC64LE9-NEXT: xvadddp 35, 1, 0 ; PC64LE9-NEXT: xvadddp 35, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: xvadddp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64( %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvsubdp 34, 1, 0 ; PC64LE-NEXT: xvsubdp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v2f64: ; PC64LE9-LABEL: constrained_vector_fsub_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: xvsubdp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64( %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, <2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %sub ret <2 x double> %sub
} }
define <3 x float> @constrained_vector_fsub_v3f32() #0 { define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fsub_v3f32: ; PC64LE-LABEL: constrained_vector_fsub_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI22_2@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI22_2@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI22_1@toc@ha
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: lfs 0, .LCPI22_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI22_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI22_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI22_2@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI22_2@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI22_3@toc@l
; PC64LE-NEXT: xssubsp 1, 0, 1 ; PC64LE-NEXT: xssubsp 1, 0, 1
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xssubsp 2, 0, 2 ; PC64LE-NEXT: xssubsp 2, 0, 2
; PC64LE-NEXT: xssubsp 0, 0, 3 ; PC64LE-NEXT: xssubsp 0, 0, 3
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 2, 2
Show All 12 Lines
; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l
; PC64LE9-NEXT: xssubsp 1, 0, 1 ; PC64LE9-NEXT: xssubsp 1, 0, 1
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xssubsp 2, 0, 2 ; PC64LE9-NEXT: xssubsp 2, 0, 2
; PC64LE9-NEXT: xssubsp 0, 0, 3 ; PC64LE9-NEXT: xssubsp 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xscvdpspn 0, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
Show All 34 Lines
; PC64LE9-LABEL: constrained_vector_fsub_v3f64: ; PC64LE9-LABEL: constrained_vector_fsub_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1 ; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l
; PC64LE9-NEXT: xssubdp 3, 0, 1 ; PC64LE9-NEXT: xssubdp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xvsubdp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64( %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
<3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
Show All 22 Lines
; PC64LE-NEXT: xvsubdp 35, 1, 0 ; PC64LE-NEXT: xvsubdp 35, 1, 0
; PC64LE-NEXT: xvsubdp 34, 1, 2 ; PC64LE-NEXT: xvsubdp 34, 1, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v4f64: ; PC64LE9-LABEL: constrained_vector_fsub_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l
; PC64LE9-NEXT: xvsubdp 35, 1, 0 ; PC64LE9-NEXT: xvsubdp 35, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: xvsubdp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64( %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
Show All 33 Lines
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xvsqrtdp 34, 0 ; PC64LE-NEXT: xvsqrtdp 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sqrt_v2f64: ; PC64LE9-LABEL: constrained_vector_sqrt_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI26_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI26_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI26_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI26_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: xvsqrtdp 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sqrt = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64( %sqrt = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
<2 x double> <double 42.0, double 42.1>, <2 x double> <double 42.0, double 42.1>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %sqrt ret <2 x double> %sqrt
} }
define <3 x float> @constrained_vector_sqrt_v3f32() #0 { define <3 x float> @constrained_vector_sqrt_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_sqrt_v3f32: ; PC64LE-LABEL: constrained_vector_sqrt_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI27_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI27_2@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI27_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI27_2@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI27_2@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI27_1@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI27_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI27_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha
; PC64LE-NEXT: xssqrtsp 0, 0
; PC64LE-NEXT: lfs 2, .LCPI27_0@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI27_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI27_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI27_3@toc@ha
; PC64LE-NEXT: xssqrtsp 1, 1 ; PC64LE-NEXT: xssqrtsp 0, 0
; PC64LE-NEXT: addi 3, 3, .LCPI27_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI27_3@toc@l
; PC64LE-NEXT: xssqrtsp 1, 1
; PC64LE-NEXT: xssqrtsp 2, 2 ; PC64LE-NEXT: xssqrtsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE-NEXT: xscvdpspn 0, 2 ; PC64LE-NEXT: xscvdpspn 0, 2
; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
Show All 16 Lines
; PC64LE9-NEXT: xssqrtsp 2, 2 ; PC64LE9-NEXT: xssqrtsp 2, 2
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 1, 1
; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 2, 2
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32( %sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %sqrt ret <3 x float> %sqrt
Show All 17 Lines
; ;
; PC64LE9-LABEL: constrained_vector_sqrt_v3f64: ; PC64LE9-LABEL: constrained_vector_sqrt_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI28_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI28_0@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI28_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI28_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI28_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI28_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI28_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI28_1@toc@l
; PC64LE9-NEXT: xssqrtdp 3, 0 ; PC64LE9-NEXT: xssqrtdp 3, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvsqrtdp 2, 0 ; PC64LE9-NEXT: xvsqrtdp 2, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sqrt = call <3 x double> @llvm.experimental.constrained.sqrt.v3f64( %sqrt = call <3 x double> @llvm.experimental.constrained.sqrt.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>, <3 x double> <double 42.0, double 42.1, double 42.2>,
Show All 16 Lines
; PC64LE-NEXT: xvsqrtdp 35, 0 ; PC64LE-NEXT: xvsqrtdp 35, 0
; PC64LE-NEXT: xvsqrtdp 34, 1 ; PC64LE-NEXT: xvsqrtdp 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sqrt_v4f64: ; PC64LE9-LABEL: constrained_vector_sqrt_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI29_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI29_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI29_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI29_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI29_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI29_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI29_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI29_1@toc@l
; PC64LE9-NEXT: xvsqrtdp 35, 0 ; PC64LE9-NEXT: xvsqrtdp 35, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: xvsqrtdp 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64( %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
<4 x double> <double 42.0, double 42.1, <4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>, double 42.2, double 42.3>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: addis 4, 2, .LCPI31_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI31_1@toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI31_1@toc@l(4) ; PC64LE-NEXT: lfs 31, .LCPI31_1@toc@l(4)
; PC64LE-NEXT: lfd 1, .LCPI31_0@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI31_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI31_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI31_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI31_2@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI31_2@toc@l(3)
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: addis 4, 2, .LCPI32_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI32_1@toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI32_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI32_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI32_1@toc@l(4) ; PC64LE-NEXT: lfs 31, .LCPI32_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI32_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI32_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI32_2@toc@ha
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: addis 3, 2, .LCPI32_2@toc@ha
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfs 1, .LCPI32_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI32_2@toc@l(3)
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI32_3@toc@ha
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: addis 3, 2, .LCPI32_3@toc@ha
; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: fmr 29, 1
; PC64LE-NEXT: lfs 1, .LCPI32_3@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI32_3@toc@l(3)
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 29 ; PC64LE-NEXT: xscvdpspn 0, 29
; PC64LE-NEXT: addis 3, 2, .LCPI32_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI32_4@toc@ha
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI32_4@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI32_4@toc@l
Show All 37 Lines
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: lfs 1, .LCPI32_3@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI32_3@toc@l(3)
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
Show All 16 Lines
; PC64LE-LABEL: constrained_vector_pow_v3f64: ; PC64LE-LABEL: constrained_vector_pow_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: addis 4, 2, .LCPI33_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI33_1@toc@ha
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfs 31, .LCPI33_1@toc@l(4)
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI33_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI33_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI33_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI33_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI33_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI33_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI33_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI33_2@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI33_2@toc@l(3)
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; PC64LE-LABEL: constrained_vector_pow_v4f64: ; PC64LE-LABEL: constrained_vector_pow_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1) ; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: addis 4, 2, .LCPI34_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI34_1@toc@ha
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: lfs 31, .LCPI34_1@toc@l(4)
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI34_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI34_0@toc@ha
; PC64LE-NEXT: lfs 31, .LCPI34_1@toc@l(4)
; PC64LE-NEXT: lfd 1, .LCPI34_0@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI34_0@toc@l(3)
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI34_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI34_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI34_2@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI34_2@toc@l(3)
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: addis 3, 2, .LCPI34_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI34_3@toc@ha
; PC64LE-NEXT: xxmrghd 63, 1, 0 ; PC64LE-NEXT: xxmrghd 63, 1, 0
; PC64LE-NEXT: lfd 1, .LCPI34_3@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI34_3@toc@l(3)
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: fmr 2, 31
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: addis 3, 2, .LCPI34_4@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI34_4@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI34_4@toc@l(3) ; PC64LE-NEXT: lfd 1, .LCPI34_4@toc@l(3)
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: vmr 2, 31 ; PC64LE-NEXT: vmr 2, 31
; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, 88(1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: lfs 1, .LCPI37_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI37_2@toc@l(3)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
▲ Show 20 Lines • Show All 354 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xvrdpic 34, 0 ; PC64LE-NEXT: xvrdpic 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_rint_v2f64: ; PC64LE9-LABEL: constrained_vector_rint_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI76_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI76_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI76_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI76_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: xvrdpic 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <2 x double> @llvm.experimental.constrained.rint.v2f64( %rint = call <2 x double> @llvm.experimental.constrained.rint.v2f64(
<2 x double> <double 42.1, double 42.0>, <2 x double> <double 42.1, double 42.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %rint ret <2 x double> %rint
} }
define <3 x float> @constrained_vector_rint_v3f32() #0 { define <3 x float> @constrained_vector_rint_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_rint_v3f32: ; PC64LE-LABEL: constrained_vector_rint_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI77_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI77_2@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI77_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI77_2@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI77_2@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI77_1@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI77_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI77_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha
; PC64LE-NEXT: xsrdpic 0, 0
; PC64LE-NEXT: lfs 2, .LCPI77_0@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI77_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI77_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI77_3@toc@ha
; PC64LE-NEXT: xsrdpic 1, 1 ; PC64LE-NEXT: xsrdpic 0, 0
; PC64LE-NEXT: addi 3, 3, .LCPI77_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI77_3@toc@l
; PC64LE-NEXT: xsrdpic 1, 1
; PC64LE-NEXT: xsrdpic 2, 2 ; PC64LE-NEXT: xsrdpic 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE-NEXT: xscvdpspn 0, 2 ; PC64LE-NEXT: xscvdpspn 0, 2
; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
Show All 16 Lines
; PC64LE9-NEXT: xsrdpic 2, 2 ; PC64LE9-NEXT: xsrdpic 2, 2
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 1, 1
; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 2, 2
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32( %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %rint ret <3 x float> %rint
Show All 17 Lines
; ;
; PC64LE9-LABEL: constrained_vector_rint_v3f64: ; PC64LE9-LABEL: constrained_vector_rint_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI78_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI78_0@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI78_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI78_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI78_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI78_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI78_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI78_1@toc@l
; PC64LE9-NEXT: xsrdpic 3, 0 ; PC64LE9-NEXT: xsrdpic 3, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvrdpic 2, 0 ; PC64LE9-NEXT: xvrdpic 2, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <3 x double> @llvm.experimental.constrained.rint.v3f64( %rint = call <3 x double> @llvm.experimental.constrained.rint.v3f64(
<3 x double> <double 42.0, double 42.1, double 42.2>, <3 x double> <double 42.0, double 42.1, double 42.2>,
Show All 16 Lines
; PC64LE-NEXT: xvrdpic 34, 0 ; PC64LE-NEXT: xvrdpic 34, 0
; PC64LE-NEXT: xvrdpic 35, 1 ; PC64LE-NEXT: xvrdpic 35, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_rint_v4f64: ; PC64LE9-LABEL: constrained_vector_rint_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI79_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI79_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI79_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI79_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI79_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI79_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI79_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI79_1@toc@l
; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: xvrdpic 34, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvrdpic 35, 0 ; PC64LE9-NEXT: xvrdpic 35, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <4 x double> @llvm.experimental.constrained.rint.v4f64( %rint = call <4 x double> @llvm.experimental.constrained.rint.v4f64(
<4 x double> <double 42.1, double 42.2, <4 x double> <double 42.1, double 42.2,
double 42.3, double 42.4>, double 42.3, double 42.4>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: xscvdpspn 0, 31
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvmaxdp 34, 1, 0 ; PC64LE-NEXT: xvmaxdp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v2f64: ; PC64LE9-LABEL: constrained_vector_maxnum_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI86_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI86_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI86_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI86_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI86_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI86_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI86_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI86_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: xvmaxdp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64( %max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
<2 x double> <double 43.0, double 42.0>, <2 x double> <double 43.0, double 42.0>,
<2 x double> <double 41.0, double 40.0>, <2 x double> <double 41.0, double 40.0>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %max ret <2 x double> %max
Show All 18 Lines
; PC64LE-NEXT: addis 3, 2, .LCPI87_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI87_2@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI87_3@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI87_3@toc@ha
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfs 1, .LCPI87_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI87_2@toc@l(3)
; PC64LE-NEXT: lfs 2, .LCPI87_3@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI87_3@toc@l(4)
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: fmr 29, 1
; PC64LE-NEXT: addis 3, 2, .LCPI87_4@toc@ha
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
; PC64LE-NEXT: addis 3, 2, .LCPI87_4@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI87_4@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI87_4@toc@l(3)
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 29 ; PC64LE-NEXT: xscvdpspn 0, 29
; PC64LE-NEXT: addis 3, 2, .LCPI87_5@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI87_5@toc@ha
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI87_5@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI87_5@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
Show All 37 Lines
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: lfs 2, .LCPI87_4@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI87_4@toc@l(3)
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: lfs 1, .LCPI88_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI88_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI88_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI88_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI88_1@toc@l(3)
; PC64LE9-NEXT: bl fmax ; PC64LE9-NEXT: bl fmax
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmaxdp 2, 1, 0 ; PC64LE9-NEXT: xvmaxdp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
Show All 27 Lines
; PC64LE-NEXT: xvmaxdp 34, 1, 0 ; PC64LE-NEXT: xvmaxdp 34, 1, 0
; PC64LE-NEXT: xvmaxdp 35, 3, 2 ; PC64LE-NEXT: xvmaxdp 35, 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v4f64: ; PC64LE9-LABEL: constrained_vector_maxnum_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI89_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI89_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI89_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI89_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI89_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI89_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI89_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI89_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI89_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI89_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI89_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI89_2@toc@l
; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: xvmaxdp 34, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI89_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI89_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI89_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI89_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmaxdp 35, 1, 0 ; PC64LE9-NEXT: xvmaxdp 35, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64( %max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
<4 x double> <double 44.0, double 45.0, <4 x double> <double 44.0, double 45.0,
double 46.0, double 47.0>, double 46.0, double 47.0>,
<4 x double> <double 40.0, double 41.0, <4 x double> <double 40.0, double 41.0,
double 42.0, double 43.0>, double 42.0, double 43.0>,
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvmindp 34, 1, 0 ; PC64LE-NEXT: xvmindp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v2f64: ; PC64LE9-LABEL: constrained_vector_minnum_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI91_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI91_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI91_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI91_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI91_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI91_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI91_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI91_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: xvmindp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64( %min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
<2 x double> <double 43.0, double 42.0>, <2 x double> <double 43.0, double 42.0>,
<2 x double> <double 41.0, double 40.0>, <2 x double> <double 41.0, double 40.0>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %min ret <2 x double> %min
Show All 18 Lines
; PC64LE-NEXT: addis 3, 2, .LCPI92_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI92_2@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI92_3@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI92_3@toc@ha
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfs 1, .LCPI92_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI92_2@toc@l(3)
; PC64LE-NEXT: lfs 2, .LCPI92_3@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI92_3@toc@l(4)
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: fmr 29, 1
; PC64LE-NEXT: addis 3, 2, .LCPI92_4@toc@ha
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
; PC64LE-NEXT: addis 3, 2, .LCPI92_4@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI92_4@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI92_4@toc@l(3)
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 29 ; PC64LE-NEXT: xscvdpspn 0, 29
; PC64LE-NEXT: addis 3, 2, .LCPI92_5@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI92_5@toc@ha
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: addi 3, 3, .LCPI92_5@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI92_5@toc@l
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
Show All 37 Lines
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: lfs 2, .LCPI92_4@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI92_4@toc@l(3)
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xscvdpspn 0, 29
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xscvdpspn 0, 30
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
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; PC64LE9-NEXT: lfs 1, .LCPI93_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI93_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI93_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI93_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI93_1@toc@l(3)
; PC64LE9-NEXT: bl fmin ; PC64LE9-NEXT: bl fmin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmindp 2, 1, 0 ; PC64LE9-NEXT: xvmindp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
Show All 27 Lines
; PC64LE-NEXT: xvmindp 34, 1, 0 ; PC64LE-NEXT: xvmindp 34, 1, 0
; PC64LE-NEXT: xvmindp 35, 3, 2 ; PC64LE-NEXT: xvmindp 35, 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v4f64: ; PC64LE9-LABEL: constrained_vector_minnum_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI94_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI94_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI94_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI94_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI94_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI94_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI94_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI94_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI94_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI94_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI94_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI94_2@toc@l
; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: xvmindp 34, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI94_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI94_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI94_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI94_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxv 1, 0(3)
; PC64LE9-NEXT: xvmindp 35, 1, 0 ; PC64LE9-NEXT: xvmindp 35, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64( %min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64(
<4 x double> <double 44.0, double 45.0, <4 x double> <double 44.0, double 45.0,
double 46.0, double 47.0>, double 46.0, double 47.0>,
<4 x double> <double 40.0, double 41.0, <4 x double> <double 40.0, double 41.0,
double 42.0, double 43.0>, double 42.0, double 43.0>,
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: xscvdpsxws 0, 1 ; PC64LE9-NEXT: xscvdpsxws 0, 1
; PC64LE9-NEXT: mtvsrws 34, 3 ; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 35, 3 ; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI97_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI97_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI97_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI97_2@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI97_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI97_3@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI97_3@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI97_3@toc@l(3)
; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: xscvdpsxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: mtvsrws 36, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
Show All 12 Lines
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xvcvspsxws 34, 34 ; PC64LE-NEXT: xvcvspsxws 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f32: ; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI98_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI98_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI98_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI98_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvspsxws 34, 0 ; PC64LE9-NEXT: xvcvspsxws 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32( %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(
<4 x float><float 42.0, float 43.0, <4 x float><float 42.0, float 43.0,
float 44.0, float 45.0>, float 44.0, float 45.0>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x i32> %result ret <4 x i32> %result
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 { define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f32: ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI101_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI101_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI101_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI101_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI101_2@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI101_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI101_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI101_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI101_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI101_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI101_2@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI101_2@toc@l(3)
; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 0, 0
; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 1, 1
; PC64LE-NEXT: xscvdpsxds 2, 2 ; PC64LE-NEXT: xscvdpsxds 2, 2
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mffprd 5, 2 ; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
Show All 21 Lines
} }
define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32() #0 { define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32() #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f32: ; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI102_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI102_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI102_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI102_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI102_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI102_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI102_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI102_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI102_1@toc@l(4)
; PC64LE-NEXT: addis 4, 2, .LCPI102_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI102_2@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI102_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI102_2@toc@l(3)
; PC64LE-NEXT: lfs 3, .LCPI102_3@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI102_3@toc@ha
; PC64LE-NEXT: lfs 3, .LCPI102_3@toc@l(3)
; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 0, 0
; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 1, 1
; PC64LE-NEXT: xscvdpsxds 2, 2 ; PC64LE-NEXT: xscvdpsxds 2, 2
; PC64LE-NEXT: xscvdpsxds 3, 3 ; PC64LE-NEXT: xscvdpsxds 3, 3
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mtfprd 0, 3 ; PC64LE-NEXT: mtfprd 0, 3
; PC64LE-NEXT: mffprd 3, 2 ; PC64LE-NEXT: mffprd 3, 2
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI105_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI105_1@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI105_1@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI105_1@toc@l(3)
; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: xscvdpsxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 35, 3 ; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI105_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI105_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI105_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI105_2@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI105_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI105_3@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI105_3@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI105_3@toc@l(3)
; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: xscvdpsxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: mtvsrws 36, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64( %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(
<3 x double><double 42.1, double 42.2, <3 x double><double 42.1, double 42.2,
double 42.3>, double 42.3>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x i32> %result ret <3 x i32> %result
} }
define <4 x i32> @constrained_vector_fptosi_v4i32_v4f64() #0 { define <4 x i32> @constrained_vector_fptosi_v4i32_v4f64() #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f64: ; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI106_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI106_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI106_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI106_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI106_2@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI106_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI106_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI106_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI106_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI106_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI106_1@toc@l(4)
; PC64LE-NEXT: lfd 2, .LCPI106_2@toc@l(5) ; PC64LE-NEXT: addis 4, 2, .LCPI106_3@toc@ha
; PC64LE-NEXT: lfd 3, .LCPI106_3@toc@l(3) ; PC64LE-NEXT: lfd 2, .LCPI106_2@toc@l(3)
; PC64LE-NEXT: lfd 3, .LCPI106_3@toc@l(4)
; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 0, 0
; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 1, 1
; PC64LE-NEXT: xscvdpsxws 2, 2 ; PC64LE-NEXT: xscvdpsxws 2, 2
; PC64LE-NEXT: xscvdpsxws 3, 3 ; PC64LE-NEXT: xscvdpsxws 3, 3
; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 3, 0
; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mffprwz 4, 1
; PC64LE-NEXT: mffprwz 5, 2 ; PC64LE-NEXT: mffprwz 5, 2
; PC64LE-NEXT: mffprwz 6, 3 ; PC64LE-NEXT: mffprwz 6, 3
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xvcvdpsxds 34, 0 ; PC64LE-NEXT: xvcvdpsxds 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f64: ; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI108_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI108_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI108_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: xvcvdpsxds 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64( %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(
<2 x double><double 42.1, double 42.2>, <2 x double><double 42.1, double 42.2>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 { define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 {
; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f64: ; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI109_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI109_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI109_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI109_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI109_2@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI109_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI109_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI109_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI109_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI109_1@toc@l(4)
; PC64LE-NEXT: lfd 2, .LCPI109_2@toc@l(5) ; PC64LE-NEXT: lfd 2, .LCPI109_2@toc@l(3)
; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 0, 0
; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 1, 1
; PC64LE-NEXT: xscvdpsxds 2, 2 ; PC64LE-NEXT: xscvdpsxds 2, 2
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mffprd 5, 2 ; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
Show All 34 Lines
; PC64LE-NEXT: xvcvdpsxds 35, 0 ; PC64LE-NEXT: xvcvdpsxds 35, 0
; PC64LE-NEXT: xvcvdpsxds 34, 1 ; PC64LE-NEXT: xvcvdpsxds 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f64: ; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI110_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI110_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI110_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI110_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI110_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI110_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI110_1@toc@l
; PC64LE9-NEXT: xvcvdpsxds 35, 0 ; PC64LE9-NEXT: xvcvdpsxds 35, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: xvcvdpsxds 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f64( %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f64(
<4 x double><double 42.1, double 42.2, <4 x double><double 42.1, double 42.2,
double 42.3, double 42.4>, double 42.3, double 42.4>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x i64> %result ret <4 x i64> %result
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: xscvdpuxws 0, 1 ; PC64LE9-NEXT: xscvdpuxws 0, 1
; PC64LE9-NEXT: mtvsrws 34, 3 ; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 35, 3 ; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI113_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI113_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI113_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI113_2@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI113_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI113_3@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI113_3@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI113_3@toc@l(3)
; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: xscvdpuxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: mtvsrws 36, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
Show All 12 Lines
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xvcvspuxws 34, 34 ; PC64LE-NEXT: xvcvspuxws 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f32: ; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI114_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI114_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI114_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvspuxws 34, 0 ; PC64LE9-NEXT: xvcvspuxws 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32( %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(
<4 x float><float 42.0, float 43.0, <4 x float><float 42.0, float 43.0,
float 44.0, float 45.0>, float 44.0, float 45.0>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x i32> %result ret <4 x i32> %result
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 { define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f32: ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI117_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI117_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI117_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI117_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI117_2@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI117_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI117_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI117_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI117_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI117_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI117_2@toc@l(5) ; PC64LE-NEXT: lfs 2, .LCPI117_2@toc@l(3)
; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 0, 0
; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 1, 1
; PC64LE-NEXT: xscvdpuxds 2, 2 ; PC64LE-NEXT: xscvdpuxds 2, 2
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mffprd 5, 2 ; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
Show All 21 Lines
} }
define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 { define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f32: ; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI118_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI118_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI118_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI118_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI118_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI118_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI118_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI118_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI118_1@toc@l(4)
; PC64LE-NEXT: addis 4, 2, .LCPI118_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI118_2@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI118_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI118_2@toc@l(3)
; PC64LE-NEXT: lfs 3, .LCPI118_3@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI118_3@toc@ha
; PC64LE-NEXT: lfs 3, .LCPI118_3@toc@l(3)
; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 0, 0
; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 1, 1
; PC64LE-NEXT: xscvdpuxds 2, 2 ; PC64LE-NEXT: xscvdpuxds 2, 2
; PC64LE-NEXT: xscvdpuxds 3, 3 ; PC64LE-NEXT: xscvdpuxds 3, 3
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mtfprd 0, 3 ; PC64LE-NEXT: mtfprd 0, 3
; PC64LE-NEXT: mffprd 3, 2 ; PC64LE-NEXT: mffprd 3, 2
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI121_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI121_1@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI121_1@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI121_1@toc@l(3)
; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: xscvdpuxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 35, 3 ; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI121_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI121_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI121_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI121_2@toc@l
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI121_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI121_3@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI121_3@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI121_3@toc@l(3)
; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: xscvdpuxws 0, 0
; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: mtvsrws 36, 3 ; PC64LE9-NEXT: mtvsrws 36, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64( %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(
<3 x double><double 42.1, double 42.2, <3 x double><double 42.1, double 42.2,
double 42.3>, double 42.3>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x i32> %result ret <3 x i32> %result
} }
define <4 x i32> @constrained_vector_fptoui_v4i32_v4f64() #0 { define <4 x i32> @constrained_vector_fptoui_v4i32_v4f64() #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f64: ; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI122_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI122_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI122_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI122_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI122_2@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI122_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI122_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI122_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI122_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI122_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI122_1@toc@l(4)
; PC64LE-NEXT: lfd 2, .LCPI122_2@toc@l(5) ; PC64LE-NEXT: addis 4, 2, .LCPI122_3@toc@ha
; PC64LE-NEXT: lfd 3, .LCPI122_3@toc@l(3) ; PC64LE-NEXT: lfd 2, .LCPI122_2@toc@l(3)
; PC64LE-NEXT: lfd 3, .LCPI122_3@toc@l(4)
; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 0, 0
; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 1, 1
; PC64LE-NEXT: xscvdpuxws 2, 2 ; PC64LE-NEXT: xscvdpuxws 2, 2
; PC64LE-NEXT: xscvdpuxws 3, 3 ; PC64LE-NEXT: xscvdpuxws 3, 3
; PC64LE-NEXT: mffprwz 3, 0 ; PC64LE-NEXT: mffprwz 3, 0
; PC64LE-NEXT: mffprwz 4, 1 ; PC64LE-NEXT: mffprwz 4, 1
; PC64LE-NEXT: mffprwz 5, 2 ; PC64LE-NEXT: mffprwz 5, 2
; PC64LE-NEXT: mffprwz 6, 3 ; PC64LE-NEXT: mffprwz 6, 3
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xvcvdpuxds 34, 0 ; PC64LE-NEXT: xvcvdpuxds 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f64: ; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI124_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI124_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI124_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: xvcvdpuxds 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64( %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(
<2 x double><double 42.1, double 42.2>, <2 x double><double 42.1, double 42.2>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 { define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 {
; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f64: ; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI125_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI125_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI125_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI125_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI125_2@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI125_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI125_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI125_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI125_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI125_1@toc@l(4)
; PC64LE-NEXT: lfd 2, .LCPI125_2@toc@l(5) ; PC64LE-NEXT: lfd 2, .LCPI125_2@toc@l(3)
; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 0, 0
; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 1, 1
; PC64LE-NEXT: xscvdpuxds 2, 2 ; PC64LE-NEXT: xscvdpuxds 2, 2
; PC64LE-NEXT: mffprd 3, 0 ; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: mffprd 4, 1 ; PC64LE-NEXT: mffprd 4, 1
; PC64LE-NEXT: mffprd 5, 2 ; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
Show All 34 Lines
; PC64LE-NEXT: xvcvdpuxds 35, 0 ; PC64LE-NEXT: xvcvdpuxds 35, 0
; PC64LE-NEXT: xvcvdpuxds 34, 1 ; PC64LE-NEXT: xvcvdpuxds 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f64: ; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI126_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI126_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI126_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI126_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI126_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI126_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI126_1@toc@l
; PC64LE9-NEXT: xvcvdpuxds 35, 0 ; PC64LE9-NEXT: xvcvdpuxds 35, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: xvcvdpuxds 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f64( %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f64(
<4 x double><double 42.1, double 42.2, <4 x double><double 42.1, double 42.2,
double 42.3, double 42.4>, double 42.3, double 42.4>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x i64> %result ret <4 x i64> %result
Show All 20 Lines %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %result ret <1 x float> %result
} }
define <2 x float> @constrained_vector_fptrunc_v2f64() #0 { define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
; PC64LE-LABEL: constrained_vector_fptrunc_v2f64: ; PC64LE-LABEL: constrained_vector_fptrunc_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI128_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI128_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI128_1@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI128_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI128_0@toc@l(3)
; PC64LE-NEXT: lfd 1, .LCPI128_1@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI128_1@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI128_1@toc@l(3)
; PC64LE-NEXT: xsrsp 0, 0 ; PC64LE-NEXT: xsrsp 0, 0
; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xsrsp 1, 1
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
Show All 19 Lines %result = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x float> %result ret <2 x float> %result
} }
define <3 x float> @constrained_vector_fptrunc_v3f64() #0 { define <3 x float> @constrained_vector_fptrunc_v3f64() #0 {
; PC64LE-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI129_1@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI129_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI129_0@toc@l(3)
; PC64LE-NEXT: lfd 1, .LCPI129_1@toc@l(4) ; PC64LE-NEXT: addis 3, 2, .LCPI129_1@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI129_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI129_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI129_3@toc@ha
; PC64LE-NEXT: xsrsp 0, 0
; PC64LE-NEXT: lfd 2, .LCPI129_3@toc@l(3) ; PC64LE-NEXT: lfd 2, .LCPI129_3@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI129_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI129_2@toc@ha
; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xsrsp 0, 0
; PC64LE-NEXT: addi 3, 3, .LCPI129_2@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI129_2@toc@l
; PC64LE-NEXT: xsrsp 1, 1
; PC64LE-NEXT: xsrsp 2, 2 ; PC64LE-NEXT: xsrsp 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE-NEXT: xscvdpspn 0, 2 ; PC64LE-NEXT: xscvdpspn 0, 2
; PC64LE-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
Show All 11 Lines
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: lfd 0, .LCPI129_1@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI129_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI129_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI129_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI129_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI129_2@toc@l
; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xsrsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI129_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI129_3@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI129_3@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI129_3@toc@l(3)
; PC64LE9-NEXT: xsrsp 0, 0 ; PC64LE9-NEXT: xsrsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64( %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
<3 x double><double 42.1, double 42.2, <3 x double><double 42.1, double 42.2,
double 42.3>, double 42.3>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %result ret <3 x float> %result
} }
define <4 x float> @constrained_vector_fptrunc_v4f64() #0 { define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
; PC64LE-LABEL: constrained_vector_fptrunc_v4f64: ; PC64LE-LABEL: constrained_vector_fptrunc_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI130_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI130_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI130_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI130_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI130_2@toc@ha
; PC64LE-NEXT: addis 6, 2, .LCPI130_3@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI130_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI130_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI130_2@toc@ha
; PC64LE-NEXT: lfd 1, .LCPI130_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI130_1@toc@l(4)
; PC64LE-NEXT: lfd 2, .LCPI130_2@toc@l(5) ; PC64LE-NEXT: addis 4, 2, .LCPI130_3@toc@ha
; PC64LE-NEXT: lfd 3, .LCPI130_3@toc@l(6) ; PC64LE-NEXT: lfd 2, .LCPI130_2@toc@l(3)
; PC64LE-NEXT: lfd 3, .LCPI130_3@toc@l(4)
; PC64LE-NEXT: xxmrghd 0, 1, 0 ; PC64LE-NEXT: xxmrghd 0, 1, 0
; PC64LE-NEXT: xxmrghd 1, 3, 2 ; PC64LE-NEXT: xxmrghd 1, 3, 2
; PC64LE-NEXT: xvcvdpsp 34, 0 ; PC64LE-NEXT: xvcvdpsp 34, 0
; PC64LE-NEXT: xvcvdpsp 35, 1 ; PC64LE-NEXT: xvcvdpsp 35, 1
; PC64LE-NEXT: vmrgew 2, 3, 2 ; PC64LE-NEXT: vmrgew 2, 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64: ; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesentry:
ret <2 x double> %result ret <2 x double> %result
} }
define <3 x double> @constrained_vector_fpext_v3f32() #0 { define <3 x double> @constrained_vector_fpext_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_fpext_v3f32: ; PC64LE-LABEL: constrained_vector_fpext_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI133_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI133_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI133_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI133_2@toc@ha
; PC64LE-NEXT: lfs 3, .LCPI133_0@toc@l(3) ; PC64LE-NEXT: lfs 3, .LCPI133_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI133_2@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI133_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI133_1@toc@l(4)
; PC64LE-NEXT: lfs 1, .LCPI133_2@toc@l(5) ; PC64LE-NEXT: lfs 1, .LCPI133_2@toc@l(3)
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fpext_v3f32: ; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI133_0@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI133_0@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI133_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI133_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI133_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI133_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI133_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI133_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI133_2@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI133_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI133_2@toc@l(3)
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32( %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
<3 x float><float 42.0, float 43.0, <3 x float><float 42.0, float 43.0,
float 44.0>, float 44.0>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %result ret <3 x double> %result
} }
define <4 x double> @constrained_vector_fpext_v4f32() #0 { define <4 x double> @constrained_vector_fpext_v4f32() #0 {
; PC64LE-LABEL: constrained_vector_fpext_v4f32: ; PC64LE-LABEL: constrained_vector_fpext_v4f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI134_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI134_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI134_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI134_2@toc@ha
; PC64LE-NEXT: addis 6, 2, .LCPI134_3@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI134_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI134_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI134_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI134_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI134_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI134_2@toc@l(5) ; PC64LE-NEXT: addis 4, 2, .LCPI134_3@toc@ha
; PC64LE-NEXT: lfs 3, .LCPI134_3@toc@l(6) ; PC64LE-NEXT: lfs 2, .LCPI134_2@toc@l(3)
; PC64LE-NEXT: lfs 3, .LCPI134_3@toc@l(4)
; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: xxmrghd 35, 3, 2 ; PC64LE-NEXT: xxmrghd 35, 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fpext_v4f32: ; PC64LE9-LABEL: constrained_vector_fpext_v4f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI134_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI134_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI134_0@toc@l(3)
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xvrdpip 0, 0 ; PC64LE-NEXT: xvrdpip 0, 0
; PC64LE-NEXT: xxswapd 34, 1 ; PC64LE-NEXT: xxswapd 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_ceil_v2f64: ; PC64LE9-LABEL: constrained_vector_ceil_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI136_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI136_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI136_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI136_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI136_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI136_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI136_1@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xvrdpip 0, 0 ; PC64LE9-NEXT: xvrdpip 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%ceil = call <2 x double> @llvm.experimental.constrained.ceil.v2f64( %ceil = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
<2 x double> <double 1.1, double 1.9>, <2 x double> <double 1.1, double 1.9>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %ceil ret <2 x double> %ceil
} }
define <3 x float> @constrained_vector_ceil_v3f32() #0 { define <3 x float> @constrained_vector_ceil_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_ceil_v3f32: ; PC64LE-LABEL: constrained_vector_ceil_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI137_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI137_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI137_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI137_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI137_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI137_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI137_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI137_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI137_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI137_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI137_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI137_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI137_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI137_3@toc@l
; PC64LE-NEXT: xsrdpip 0, 0 ; PC64LE-NEXT: xsrdpip 0, 0
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xsrdpip 0, 1 ; PC64LE-NEXT: xsrdpip 0, 1
; PC64LE-NEXT: xsrdpip 0, 2 ; PC64LE-NEXT: xsrdpip 0, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_ceil_v3f32: ; PC64LE9-LABEL: constrained_vector_ceil_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI137_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI137_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI137_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI137_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI137_1@toc@ha
; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: xsrdpip 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI137_1@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI137_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI137_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI137_2@toc@ha
; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: xsrdpip 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI137_2@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI137_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI137_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI137_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI137_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI137_3@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: xsrdpip 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32( %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
<3 x float> <float 1.5, float 2.5, float 3.5>, <3 x float> <float 1.5, float 2.5, float 3.5>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %ceil ret <3 x float> %ceil
} }
Show All 16 Lines
; ;
; PC64LE9-LABEL: constrained_vector_ceil_v3f64: ; PC64LE9-LABEL: constrained_vector_ceil_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI138_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI138_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI138_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI138_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI138_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI138_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI138_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI138_1@toc@l
; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: xsrdpip 0, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI138_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI138_2@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI138_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI138_2@toc@l(3)
; PC64LE9-NEXT: xvrdpip 0, 0 ; PC64LE9-NEXT: xvrdpip 0, 0
; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 2, 1
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64( %ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64(
Show All 40 Lines
; PC64LE-NEXT: xvrdpim 0, 0 ; PC64LE-NEXT: xvrdpim 0, 0
; PC64LE-NEXT: xxswapd 34, 1 ; PC64LE-NEXT: xxswapd 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_floor_v2f64: ; PC64LE9-LABEL: constrained_vector_floor_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI140_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI140_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI140_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI140_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI140_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI140_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI140_1@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xvrdpim 0, 0 ; PC64LE9-NEXT: xvrdpim 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%floor = call <2 x double> @llvm.experimental.constrained.floor.v2f64( %floor = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
<2 x double> <double 1.1, double 1.9>, <2 x double> <double 1.1, double 1.9>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %floor ret <2 x double> %floor
} }
define <3 x float> @constrained_vector_floor_v3f32() #0 { define <3 x float> @constrained_vector_floor_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_floor_v3f32: ; PC64LE-LABEL: constrained_vector_floor_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI141_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI141_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI141_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI141_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI141_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI141_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI141_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI141_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI141_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI141_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI141_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI141_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI141_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI141_3@toc@l
; PC64LE-NEXT: xsrdpim 0, 0 ; PC64LE-NEXT: xsrdpim 0, 0
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xsrdpim 0, 1 ; PC64LE-NEXT: xsrdpim 0, 1
; PC64LE-NEXT: xsrdpim 0, 2 ; PC64LE-NEXT: xsrdpim 0, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_floor_v3f32: ; PC64LE9-LABEL: constrained_vector_floor_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI141_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI141_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI141_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI141_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI141_1@toc@ha
; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: xsrdpim 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI141_1@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI141_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI141_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI141_2@toc@ha
; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: xsrdpim 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI141_2@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI141_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI141_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI141_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI141_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI141_3@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: xsrdpim 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32( %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
<3 x float> <float 1.5, float 2.5, float 3.5>, <3 x float> <float 1.5, float 2.5, float 3.5>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %floor ret <3 x float> %floor
} }
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; ;
; PC64LE9-LABEL: constrained_vector_floor_v3f64: ; PC64LE9-LABEL: constrained_vector_floor_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI142_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI142_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI142_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI142_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI142_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI142_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI142_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI142_1@toc@l
; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: xsrdpim 0, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI142_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI142_2@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI142_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI142_2@toc@l(3)
; PC64LE9-NEXT: xvrdpim 0, 0 ; PC64LE9-NEXT: xvrdpim 0, 0
; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 2, 1
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64( %floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64(
Show All 39 Lines
; PC64LE-NEXT: xvrdpi 0, 0 ; PC64LE-NEXT: xvrdpi 0, 0
; PC64LE-NEXT: xxswapd 34, 1 ; PC64LE-NEXT: xxswapd 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_round_v2f64: ; PC64LE9-LABEL: constrained_vector_round_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI144_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI144_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI144_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI144_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI144_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI144_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI144_1@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xvrdpi 0, 0 ; PC64LE9-NEXT: xvrdpi 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%round = call <2 x double> @llvm.experimental.constrained.round.v2f64( %round = call <2 x double> @llvm.experimental.constrained.round.v2f64(
<2 x double> <double 1.1, double 1.9>, <2 x double> <double 1.1, double 1.9>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %round ret <2 x double> %round
} }
define <3 x float> @constrained_vector_round_v3f32() #0 { define <3 x float> @constrained_vector_round_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_round_v3f32: ; PC64LE-LABEL: constrained_vector_round_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI145_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI145_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI145_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI145_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI145_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI145_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI145_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI145_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI145_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI145_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI145_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI145_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI145_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI145_3@toc@l
; PC64LE-NEXT: xsrdpi 0, 0 ; PC64LE-NEXT: xsrdpi 0, 0
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xsrdpi 0, 1 ; PC64LE-NEXT: xsrdpi 0, 1
; PC64LE-NEXT: xsrdpi 0, 2 ; PC64LE-NEXT: xsrdpi 0, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_round_v3f32: ; PC64LE9-LABEL: constrained_vector_round_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI145_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI145_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI145_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI145_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI145_1@toc@ha
; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: xsrdpi 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI145_1@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI145_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI145_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI145_2@toc@ha
; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: xsrdpi 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI145_2@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI145_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI145_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI145_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI145_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI145_3@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: xsrdpi 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%round = call <3 x float> @llvm.experimental.constrained.round.v3f32( %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
<3 x float> <float 1.5, float 2.5, float 3.5>, <3 x float> <float 1.5, float 2.5, float 3.5>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %round ret <3 x float> %round
} }
define <3 x double> @constrained_vector_round_v3f64() #0 { define <3 x double> @constrained_vector_round_v3f64() #0 {
; PC64LE-LABEL: constrained_vector_round_v3f64: ; PC64LE-LABEL: constrained_vector_round_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 4, 2, .LCPI146_1@toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI146_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI146_0@toc@ha
; PC64LE-NEXT: addi 4, 4, .LCPI146_1@toc@l ; PC64LE-NEXT: addis 4, 2, .LCPI146_1@toc@ha
; PC64LE-NEXT: lxvd2x 1, 0, 4
; PC64LE-NEXT: addis 4, 2, .LCPI146_3@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI146_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI146_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI146_2@toc@ha ; PC64LE-NEXT: addi 3, 4, .LCPI146_1@toc@l
; PC64LE-NEXT: addis 4, 2, .LCPI146_3@toc@ha
; PC64LE-NEXT: lfs 2, .LCPI146_3@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI146_3@toc@l(4)
; PC64LE-NEXT: lxvd2x 1, 0, 3
; PC64LE-NEXT: addis 3, 2, .LCPI146_2@toc@ha
; PC64LE-NEXT: xsrdpi 0, 0 ; PC64LE-NEXT: xsrdpi 0, 0
; PC64LE-NEXT: fmr 3, 2
; PC64LE-NEXT: xvrdpi 0, 1 ; PC64LE-NEXT: xvrdpi 0, 1
; PC64LE-NEXT: lfs 1, .LCPI146_2@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI146_2@toc@l(3)
; PC64LE-NEXT: fmr 3, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_round_v3f64: ; PC64LE9-LABEL: constrained_vector_round_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI146_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI146_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI146_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI146_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI146_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI146_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI146_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI146_1@toc@l
; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: xsrdpi 0, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI146_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI146_2@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI146_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI146_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI146_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI146_3@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI146_3@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI146_3@toc@l(3)
; PC64LE9-NEXT: xvrdpi 0, 0 ; PC64LE9-NEXT: xvrdpi 0, 0
; PC64LE9-NEXT: fmr 3, 2 ; PC64LE9-NEXT: fmr 3, 2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
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; PC64LE-NEXT: xvrdpiz 0, 0 ; PC64LE-NEXT: xvrdpiz 0, 0
; PC64LE-NEXT: xxswapd 34, 1 ; PC64LE-NEXT: xxswapd 34, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_trunc_v2f64: ; PC64LE9-LABEL: constrained_vector_trunc_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI148_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI148_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI148_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI148_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI148_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI148_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI148_1@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xvrdpiz 0, 0 ; PC64LE9-NEXT: xvrdpiz 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%trunc = call <2 x double> @llvm.experimental.constrained.trunc.v2f64( %trunc = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
<2 x double> <double 1.1, double 1.9>, <2 x double> <double 1.1, double 1.9>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %trunc ret <2 x double> %trunc
} }
define <3 x float> @constrained_vector_trunc_v3f32() #0 { define <3 x float> @constrained_vector_trunc_v3f32() #0 {
; PC64LE-LABEL: constrained_vector_trunc_v3f32: ; PC64LE-LABEL: constrained_vector_trunc_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI149_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI149_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI149_0@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI149_1@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI149_1@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI149_2@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI149_2@toc@ha
; PC64LE-NEXT: lfs 1, .LCPI149_1@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI149_2@toc@l(3) ; PC64LE-NEXT: lfs 2, .LCPI149_2@toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI149_3@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI149_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI149_3@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI149_3@toc@l
; PC64LE-NEXT: xsrdpiz 0, 0 ; PC64LE-NEXT: xsrdpiz 0, 0
; PC64LE-NEXT: lvx 2, 0, 3 ; PC64LE-NEXT: lvx 2, 0, 3
; PC64LE-NEXT: xsrdpiz 0, 1 ; PC64LE-NEXT: xsrdpiz 0, 1
; PC64LE-NEXT: xsrdpiz 0, 2 ; PC64LE-NEXT: xsrdpiz 0, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_trunc_v3f32: ; PC64LE9-LABEL: constrained_vector_trunc_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI149_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI149_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI149_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI149_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI149_1@toc@ha
; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: xsrdpiz 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI149_1@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI149_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI149_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI149_2@toc@ha
; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: xsrdpiz 0, 0
; PC64LE9-NEXT: lfs 0, .LCPI149_2@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI149_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI149_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI149_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI149_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI149_3@toc@l
; PC64LE9-NEXT: lxvx 34, 0, 3 ; PC64LE9-NEXT: lxv 34, 0(3)
; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: xsrdpiz 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32( %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
<3 x float> <float 1.5, float 2.5, float 3.5>, <3 x float> <float 1.5, float 2.5, float 3.5>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %trunc ret <3 x float> %trunc
} }
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; ;
; PC64LE9-LABEL: constrained_vector_trunc_v3f64: ; PC64LE9-LABEL: constrained_vector_trunc_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI150_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI150_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI150_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI150_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI150_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI150_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI150_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI150_1@toc@l
; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: xsrdpiz 0, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxv 0, 0(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI150_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI150_2@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI150_2@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI150_2@toc@l(3)
; PC64LE9-NEXT: xvrdpiz 0, 0 ; PC64LE9-NEXT: xvrdpiz 0, 0
; PC64LE9-NEXT: fmr 2, 1 ; PC64LE9-NEXT: fmr 2, 1
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64( %trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64(
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; PC64LE-NEXT: vsrad 2, 2, 3 ; PC64LE-NEXT: vsrad 2, 2, 3
; PC64LE-NEXT: xvcvsxddp 34, 34 ; PC64LE-NEXT: xvcvsxddp 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16: ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: vperm 2, 2, 2, 3 ; PC64LE9-NEXT: vperm 2, 2, 2, 3
; PC64LE9-NEXT: vextsh2d 2, 2 ; PC64LE9-NEXT: vextsh2d 2, 2
; PC64LE9-NEXT: xvcvsxddp 34, 34 ; PC64LE9-NEXT: xvcvsxddp 34, 34
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <2 x double> %result = call <2 x double>
@llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x, @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
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; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: mtfprwa 0, 3 ; PC64LE9-NEXT: mtfprwa 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI161_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI161_0@toc@ha
; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 0, 0
; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vmrghw 3, 4, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mfvsrwz 3, 34
; PC64LE9-NEXT: mtfprwa 0, 3 ; PC64LE9-NEXT: mtfprwa 0, 3
; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 2, 3, 4 ; PC64LE9-NEXT: vperm 2, 2, 3, 4
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
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; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: mtfprd 0, 4 ; PC64LE9-NEXT: mtfprd 0, 4
; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: mtfprd 0, 5
; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 0, 0
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x float> %result = call <3 x float>
@llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x, @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
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; PC64LE-NEXT: xvcvuxddp 34, 34 ; PC64LE-NEXT: xvcvuxddp 34, 34
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha
; PC64LE9-NEXT: xxlxor 36, 36, 36 ; PC64LE9-NEXT: xxlxor 36, 36, 36
; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: xvcvuxddp 34, 34 ; PC64LE9-NEXT: xvcvuxddp 34, 34
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <2 x double> %result = call <2 x double>
@llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x, @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
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; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mtfprwz 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI179_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI179_0@toc@ha
; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 0, 0
; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vmrghw 3, 4, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxv 36, 0(3)
; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mfvsrwz 3, 34
; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mtfprwz 0, 3
; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 2, 3, 4 ; PC64LE9-NEXT: vperm 2, 2, 3, 4
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
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; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
; PC64LE9-NEXT: mtfprd 0, 4 ; PC64LE9-NEXT: mtfprd 0, 4
; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 0, 0
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: mtfprd 0, 5
; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 0, 0
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxv 35, 0(3)
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <3 x float> %result = call <3 x float>
@llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x, @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
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llvm/test/CodeGen/PowerPC/vector-extend-sign.ll

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesentry:
ret <2 x i64> %shr ret <2 x i64> %shr
} }
define <2 x i64> @test_none(<2 x i64> %m) { define <2 x i64> @test_none(<2 x i64> %m) {
; CHECK-P9-LABEL: test_none: ; CHECK-P9-LABEL: test_none:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx 35, 0, 3 ; CHECK-P9-NEXT: lxv 35, 0(3)
; CHECK-P9-NEXT: vsld 2, 2, 3 ; CHECK-P9-NEXT: vsld 2, 2, 3
; CHECK-P9-NEXT: vsrad 2, 2, 3 ; CHECK-P9-NEXT: vsrad 2, 2, 3
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-NOALTIVEC-LABEL: test_none: ; CHECK-P9-NOALTIVEC-LABEL: test_none:
; CHECK-P9-NOALTIVEC: # %bb.0: # %entry ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
; CHECK-P9-NOALTIVEC-NEXT: sldi 3, 3, 16 ; CHECK-P9-NOALTIVEC-NEXT: sldi 3, 3, 16
; CHECK-P9-NOALTIVEC-NEXT: sldi 4, 4, 16 ; CHECK-P9-NOALTIVEC-NEXT: sldi 4, 4, 16
Show All 18 Lines

llvm/test/CodeGen/PowerPC/vector-ldst.ll

Show All 38 Linesentry:
%1 = load <16 x i8>, <16 x i8>* %0, align 16 %1 = load <16 x i8>, <16 x i8>* %0, align 16
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_unalign16_vector(i8* nocapture readonly %ptr) { define dso_local <16 x i8> @ld_unalign16_vector(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_unalign16_vector: ; CHECK-LABEL: ld_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 1 ; CHECK-P8-LE-NEXT: addi r3, r3, 1
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: ld_unalign16_vector: ; CHECK-P8-BE-LABEL: ld_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 1 ; CHECK-P8-BE-NEXT: addi r3, r3, 1
; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: lxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1
%0 = bitcast i8* %add.ptr to <16 x i8>* %0 = bitcast i8* %add.ptr to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 16 %1 = load <16 x i8>, <16 x i8>* %0, align 16
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_align16_vector(i8* nocapture readonly %ptr) { define dso_local <16 x i8> @ld_align16_vector(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_vector: ; CHECK-LABEL: ld_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: li r4, 8
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_align16_vector: ; CHECK-P8-LE-LABEL: ld_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 8 ; CHECK-P8-LE-NEXT: addi r3, r3, 8
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Linesentry:
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_or_vector(i64 %ptr, i8 zeroext %off) { define dso_local <16 x i8> @ld_or_vector(i64 %ptr, i8 zeroext %off) {
; CHECK-LABEL: ld_or_vector: ; CHECK-LABEL: ld_or_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_or_vector: ; CHECK-P8-LE-LABEL: ld_or_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: or r3, r4, r3 ; CHECK-P8-LE-NEXT: or r3, r4, r3
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 38 Linesentry:
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_not_disjoint16_vector(i64 %ptr) { define dso_local <16 x i8> @ld_not_disjoint16_vector(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint16_vector: ; CHECK-LABEL: ld_not_disjoint16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint16_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 9 Linesentry:
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_disjoint_unalign16_vector(i64 %ptr) { define dso_local <16 x i8> @ld_disjoint_unalign16_vector(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_unalign16_vector: ; CHECK-LABEL: ld_disjoint_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: li r4, 6
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 12 Linesentry:
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_disjoint_align16_vector(i64 %ptr) { define dso_local <16 x i8> @ld_disjoint_align16_vector(i64 %ptr) {
; CHECK-LABEL: ld_disjoint_align16_vector: ; CHECK-LABEL: ld_disjoint_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 24 ; CHECK-NEXT: li r4, 24
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_disjoint_align16_vector: ; CHECK-P8-LE-LABEL: ld_disjoint_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 24 ; CHECK-P8-LE-NEXT: ori r3, r3, 24
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 13 Lines
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_not_disjoint32_vector(i64 %ptr) { define dso_local <16 x i8> @ld_not_disjoint32_vector(i64 %ptr) {
; CHECK-LABEL: ld_not_disjoint32_vector: ; CHECK-LABEL: ld_not_disjoint32_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint32_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: oris r3, r3, 1 ; CHECK-P8-LE-NEXT: oris r3, r3, 1
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_not_disjoint64_vector(i64 %ptr) { define dso_local <16 x i8> @ld_not_disjoint64_vector(i64 %ptr) {
; CHECK-P10-LABEL: ld_not_disjoint64_vector: ; CHECK-P10-LABEL: ld_not_disjoint64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_not_disjoint64_vector: ; CHECK-P9-LABEL: ld_not_disjoint64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-P9-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-P9-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-P9-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-P9-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-P9-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: lxvx v2, 0, r3 ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_not_disjoint64_vector: ; CHECK-P8-LE-LABEL: ld_not_disjoint64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Linesentry:
ret <16 x i8> %1 ret <16 x i8> %1
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_unalign16_vector() { define dso_local <16 x i8> @ld_cst_unalign16_vector() {
; CHECK-LABEL: ld_cst_unalign16_vector: ; CHECK-LABEL: ld_cst_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: lxvx v2, 0, r3 ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign16_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 255 ; CHECK-P8-LE-NEXT: li r3, 255
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 30 Linesentry:
ret <16 x i8> %0 ret <16 x i8> %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_unalign32_vector() { define dso_local <16 x i8> @ld_cst_unalign32_vector() {
; CHECK-P10-LABEL: ld_cst_unalign32_vector: ; CHECK-P10-LABEL: ld_cst_unalign32_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 99999 ; CHECK-P10-NEXT: pli r3, 99999
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign32_vector: ; CHECK-P9-LABEL: ld_cst_unalign32_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 1 ; CHECK-P9-NEXT: lis r3, 1
; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: lxvx v2, 0, r3 ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign32_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 1 ; CHECK-P8-LE-NEXT: lis r3, 1
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 9 Linesentry:
ret <16 x i8> %0 ret <16 x i8> %0
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_align32_vector() { define dso_local <16 x i8> @ld_cst_align32_vector() {
; CHECK-P10-LABEL: ld_cst_align32_vector: ; CHECK-P10-LABEL: ld_cst_align32_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 9999900 ; CHECK-P10-NEXT: pli r3, 9999900
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align32_vector: ; CHECK-P9-LABEL: ld_cst_align32_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 152 ; CHECK-P9-NEXT: lis r3, 152
; CHECK-P9-NEXT: ori r3, r3, 38428 ; CHECK-P9-NEXT: ori r3, r3, 38428
; CHECK-P9-NEXT: lxvx v2, 0, r3 ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_align32_vector: ; CHECK-P8-LE-LABEL: ld_cst_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 152 ; CHECK-P8-LE-NEXT: lis r3, 152
; CHECK-P8-LE-NEXT: ori r3, r3, 38428 ; CHECK-P8-LE-NEXT: ori r3, r3, 38428
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 11 Lines
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_unalign64_vector() { define dso_local <16 x i8> @ld_cst_unalign64_vector() {
; CHECK-P10-LABEL: ld_cst_unalign64_vector: ; CHECK-P10-LABEL: ld_cst_unalign64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: lxvx v2, 0, r4 ; CHECK-P10-NEXT: lxv v2, 0(r4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_unalign64_vector: ; CHECK-P9-LABEL: ld_cst_unalign64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-P9-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-P9-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-P9-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-P9-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: lxvx v2, 0, r3 ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_unalign64_vector: ; CHECK-P8-LE-LABEL: ld_cst_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 29 ; CHECK-P8-LE-NEXT: li r3, 29
; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-LE-NEXT: oris r3, r3, 54437 ; CHECK-P8-LE-NEXT: oris r3, r3, 54437
; CHECK-P8-LE-NEXT: ori r3, r3, 4097 ; CHECK-P8-LE-NEXT: ori r3, r3, 4097
Show All 14 Lines
} }
; Function Attrs: norecurse nounwind readonly uwtable willreturn ; Function Attrs: norecurse nounwind readonly uwtable willreturn
define dso_local <16 x i8> @ld_cst_align64_vector() { define dso_local <16 x i8> @ld_cst_align64_vector() {
; CHECK-P10-LABEL: ld_cst_align64_vector: ; CHECK-P10-LABEL: ld_cst_align64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lxvx v2, 0, r3 ; CHECK-P10-NEXT: lxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: ld_cst_align64_vector: ; CHECK-P9-LABEL: ld_cst_align64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-P9-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-P9-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-P9-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: lxvx v2, 0, r3 ; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: ld_cst_align64_vector: ; CHECK-P8-LE-LABEL: ld_cst_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 3725 ; CHECK-P8-LE-NEXT: lis r3, 3725
; CHECK-P8-LE-NEXT: ori r3, r3, 19025 ; CHECK-P8-LE-NEXT: ori r3, r3, 19025
; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-LE-NEXT: lvx v2, 0, r3 ; CHECK-P8-LE-NEXT: lvx v2, 0, r3
Show All 32 Linesentry:
store <16 x i8> %str, <16 x i8>* %0, align 16 store <16 x i8> %str, <16 x i8>* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_unalign16_vector(i8* nocapture %ptr, <16 x i8> %str) { define dso_local void @st_unalign16_vector(i8* nocapture %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_unalign16_vector: ; CHECK-LABEL: st_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_unalign16_vector: ; CHECK-P8-LE-LABEL: st_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 1 ; CHECK-P8-LE-NEXT: addi r3, r3, 1
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: st_unalign16_vector: ; CHECK-P8-BE-LABEL: st_unalign16_vector:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: addi r3, r3, 1 ; CHECK-P8-BE-NEXT: addi r3, r3, 1
; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3 ; CHECK-P8-BE-NEXT: stxvw4x v2, 0, r3
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1 %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1
%0 = bitcast i8* %add.ptr to <16 x i8>* %0 = bitcast i8* %add.ptr to <16 x i8>*
store <16 x i8> %str, <16 x i8>* %0, align 16 store <16 x i8> %str, <16 x i8>* %0, align 16
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_align16_vector(i8* nocapture %ptr, <16 x i8> %str) { define dso_local void @st_align16_vector(i8* nocapture %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_align16_vector: ; CHECK-LABEL: st_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 8 ; CHECK-NEXT: li r4, 8
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_align16_vector: ; CHECK-P8-LE-LABEL: st_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: addi r3, r3, 8 ; CHECK-P8-LE-NEXT: addi r3, r3, 8
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_or1_vector(i64 %ptr, i8 zeroext %off, <16 x i8> %str) { define dso_local void @st_or1_vector(i64 %ptr, i8 zeroext %off, <16 x i8> %str) {
; CHECK-LABEL: st_or1_vector: ; CHECK-LABEL: st_or1_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_or1_vector: ; CHECK-P8-LE-LABEL: st_or1_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: or r3, r4, r3 ; CHECK-P8-LE-NEXT: or r3, r4, r3
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 38 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint16_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_not_disjoint16_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_not_disjoint16_vector: ; CHECK-LABEL: st_not_disjoint16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint16_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 9 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_unalign16_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_disjoint_unalign16_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_disjoint_unalign16_vector: ; CHECK-LABEL: st_disjoint_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: li r4, 6
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_unalign16_vector: ; CHECK-P8-LE-LABEL: st_disjoint_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 6 ; CHECK-P8-LE-NEXT: ori r3, r3, 6
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 12 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_disjoint_align16_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_disjoint_align16_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_disjoint_align16_vector: ; CHECK-LABEL: st_disjoint_align16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: ori r3, r3, 24 ; CHECK-NEXT: li r4, 24
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxvx v2, r3, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_disjoint_align16_vector: ; CHECK-P8-LE-LABEL: st_disjoint_align16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51 ; CHECK-P8-LE-NEXT: rldicr r3, r3, 0, 51
; CHECK-P8-LE-NEXT: ori r3, r3, 24 ; CHECK-P8-LE-NEXT: ori r3, r3, 24
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 13 Lines
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint32_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_not_disjoint32_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-LABEL: st_not_disjoint32_vector: ; CHECK-LABEL: st_not_disjoint32_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint32_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: oris r3, r3, 1 ; CHECK-P8-LE-NEXT: oris r3, r3, 1
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_not_disjoint64_vector(i64 %ptr, <16 x i8> %str) { define dso_local void @st_not_disjoint64_vector(i64 %ptr, <16 x i8> %str) {
; CHECK-P10-LABEL: st_not_disjoint64_vector: ; CHECK-P10-LABEL: st_not_disjoint64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 232 ; CHECK-P10-NEXT: pli r4, 232
; CHECK-P10-NEXT: pli r5, 3567587329 ; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_not_disjoint64_vector: ; CHECK-P9-LABEL: st_not_disjoint64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r4, 29 ; CHECK-P9-NEXT: li r4, 29
; CHECK-P9-NEXT: rldic r4, r4, 35, 24 ; CHECK-P9-NEXT: rldic r4, r4, 35, 24
; CHECK-P9-NEXT: oris r4, r4, 54437 ; CHECK-P9-NEXT: oris r4, r4, 54437
; CHECK-P9-NEXT: ori r4, r4, 4097 ; CHECK-P9-NEXT: ori r4, r4, 4097
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-P9-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: stxvx v2, 0, r3 ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_not_disjoint64_vector: ; CHECK-P8-LE-LABEL: st_not_disjoint64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r4, 29 ; CHECK-P8-LE-NEXT: li r4, 29
; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24 ; CHECK-P8-LE-NEXT: rldic r4, r4, 35, 24
; CHECK-P8-LE-NEXT: oris r4, r4, 54437 ; CHECK-P8-LE-NEXT: oris r4, r4, 54437
; CHECK-P8-LE-NEXT: ori r4, r4, 4097 ; CHECK-P8-LE-NEXT: ori r4, r4, 4097
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_unalign16_vector(<16 x i8> %str) { define dso_local void @st_cst_unalign16_vector(<16 x i8> %str) {
; CHECK-LABEL: st_cst_unalign16_vector: ; CHECK-LABEL: st_cst_unalign16_vector:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 255 ; CHECK-NEXT: li r3, 255
; CHECK-NEXT: stxvx v2, 0, r3 ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign16_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign16_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 255 ; CHECK-P8-LE-NEXT: li r3, 255
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
Show All 30 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_unalign32_vector(<16 x i8> %str) { define dso_local void @st_cst_unalign32_vector(<16 x i8> %str) {
; CHECK-P10-LABEL: st_cst_unalign32_vector: ; CHECK-P10-LABEL: st_cst_unalign32_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 99999 ; CHECK-P10-NEXT: pli r3, 99999
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_unalign32_vector: ; CHECK-P9-LABEL: st_cst_unalign32_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 1 ; CHECK-P9-NEXT: lis r3, 1
; CHECK-P9-NEXT: ori r3, r3, 34463 ; CHECK-P9-NEXT: ori r3, r3, 34463
; CHECK-P9-NEXT: stxvx v2, 0, r3 ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign32_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 1 ; CHECK-P8-LE-NEXT: lis r3, 1
; CHECK-P8-LE-NEXT: ori r3, r3, 34463 ; CHECK-P8-LE-NEXT: ori r3, r3, 34463
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 9 Linesentry:
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align32_vector(<16 x i8> %str) { define dso_local void @st_cst_align32_vector(<16 x i8> %str) {
; CHECK-P10-LABEL: st_cst_align32_vector: ; CHECK-P10-LABEL: st_cst_align32_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 9999900 ; CHECK-P10-NEXT: pli r3, 9999900
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align32_vector: ; CHECK-P9-LABEL: st_cst_align32_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 152 ; CHECK-P9-NEXT: lis r3, 152
; CHECK-P9-NEXT: ori r3, r3, 38428 ; CHECK-P9-NEXT: ori r3, r3, 38428
; CHECK-P9-NEXT: stxvx v2, 0, r3 ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_align32_vector: ; CHECK-P8-LE-LABEL: st_cst_align32_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 152 ; CHECK-P8-LE-NEXT: lis r3, 152
; CHECK-P8-LE-NEXT: ori r3, r3, 38428 ; CHECK-P8-LE-NEXT: ori r3, r3, 38428
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
Show All 11 Lines
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_unalign64_vector(<16 x i8> %str) { define dso_local void @st_cst_unalign64_vector(<16 x i8> %str) {
; CHECK-P10-LABEL: st_cst_unalign64_vector: ; CHECK-P10-LABEL: st_cst_unalign64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 232 ; CHECK-P10-NEXT: pli r3, 232
; CHECK-P10-NEXT: pli r4, 3567587329 ; CHECK-P10-NEXT: pli r4, 3567587329
; CHECK-P10-NEXT: rldimi r4, r3, 32, 0 ; CHECK-P10-NEXT: rldimi r4, r3, 32, 0
; CHECK-P10-NEXT: stxvx v2, 0, r4 ; CHECK-P10-NEXT: stxv v2, 0(r4)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_unalign64_vector: ; CHECK-P9-LABEL: st_cst_unalign64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: li r3, 29 ; CHECK-P9-NEXT: li r3, 29
; CHECK-P9-NEXT: rldic r3, r3, 35, 24 ; CHECK-P9-NEXT: rldic r3, r3, 35, 24
; CHECK-P9-NEXT: oris r3, r3, 54437 ; CHECK-P9-NEXT: oris r3, r3, 54437
; CHECK-P9-NEXT: ori r3, r3, 4097 ; CHECK-P9-NEXT: ori r3, r3, 4097
; CHECK-P9-NEXT: stxvx v2, 0, r3 ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_unalign64_vector: ; CHECK-P8-LE-LABEL: st_cst_unalign64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: li r3, 29 ; CHECK-P8-LE-NEXT: li r3, 29
; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 35, 24
; CHECK-P8-LE-NEXT: oris r3, r3, 54437 ; CHECK-P8-LE-NEXT: oris r3, r3, 54437
; CHECK-P8-LE-NEXT: ori r3, r3, 4097 ; CHECK-P8-LE-NEXT: ori r3, r3, 4097
Show All 14 Lines
} }
; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly ; Function Attrs: nofree norecurse nounwind uwtable willreturn writeonly
define dso_local void @st_cst_align64_vector(<16 x i8> %str) { define dso_local void @st_cst_align64_vector(<16 x i8> %str) {
; CHECK-P10-LABEL: st_cst_align64_vector: ; CHECK-P10-LABEL: st_cst_align64_vector:
; CHECK-P10: # %bb.0: # %entry ; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: stxvx v2, 0, r3 ; CHECK-P10-NEXT: stxv v2, 0(r3)
; CHECK-P10-NEXT: blr ; CHECK-P10-NEXT: blr
; ;
; CHECK-P9-LABEL: st_cst_align64_vector: ; CHECK-P9-LABEL: st_cst_align64_vector:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lis r3, 3725 ; CHECK-P9-NEXT: lis r3, 3725
; CHECK-P9-NEXT: ori r3, r3, 19025 ; CHECK-P9-NEXT: ori r3, r3, 19025
; CHECK-P9-NEXT: rldic r3, r3, 12, 24 ; CHECK-P9-NEXT: rldic r3, r3, 12, 24
; CHECK-P9-NEXT: stxvx v2, 0, r3 ; CHECK-P9-NEXT: stxv v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: st_cst_align64_vector: ; CHECK-P8-LE-LABEL: st_cst_align64_vector:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: lis r3, 3725 ; CHECK-P8-LE-NEXT: lis r3, 3725
; CHECK-P8-LE-NEXT: ori r3, r3, 19025 ; CHECK-P8-LE-NEXT: ori r3, r3, 19025
; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24 ; CHECK-P8-LE-NEXT: rldic r3, r3, 12, 24
; CHECK-P8-LE-NEXT: stvx v2, 0, r3 ; CHECK-P8-LE-NEXT: stvx v2, 0, r3
Show All 13 Lines

llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 11,994 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_1_v2i64: ; PWR9-LABEL: ugt_1_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI100_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI100_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI100_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI100_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 1, i64 1> %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_2_v2i64: ; PWR9-LABEL: ult_2_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI101_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI101_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI101_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI101_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 2, i64 2> %3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_2_v2i64: ; PWR9-LABEL: ugt_2_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI102_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI102_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI102_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI102_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 2, i64 2> %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_3_v2i64: ; PWR9-LABEL: ult_3_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI103_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI103_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI103_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI103_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 3, i64 3> %3 = icmp ult <2 x i64> %2, <i64 3, i64 3>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_3_v2i64: ; PWR9-LABEL: ugt_3_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI104_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI104_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI104_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI104_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 3, i64 3> %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_4_v2i64: ; PWR9-LABEL: ult_4_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI105_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI105_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI105_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 4, i64 4> %3 = icmp ult <2 x i64> %2, <i64 4, i64 4>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_4_v2i64: ; PWR9-LABEL: ugt_4_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI106_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI106_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI106_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI106_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 4, i64 4> %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_5_v2i64: ; PWR9-LABEL: ult_5_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI107_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI107_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI107_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI107_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 5, i64 5> %3 = icmp ult <2 x i64> %2, <i64 5, i64 5>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_5_v2i64: ; PWR9-LABEL: ugt_5_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI108_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI108_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI108_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 5, i64 5> %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_6_v2i64: ; PWR9-LABEL: ult_6_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI109_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI109_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI109_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI109_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 6, i64 6> %3 = icmp ult <2 x i64> %2, <i64 6, i64 6>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_6_v2i64: ; PWR9-LABEL: ugt_6_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI110_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI110_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI110_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 6, i64 6> %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_7_v2i64: ; PWR9-LABEL: ult_7_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI111_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI111_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI111_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI111_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 7, i64 7> %3 = icmp ult <2 x i64> %2, <i64 7, i64 7>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_7_v2i64: ; PWR9-LABEL: ugt_7_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI112_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI112_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI112_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI112_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 7, i64 7> %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_8_v2i64: ; PWR9-LABEL: ult_8_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI113_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI113_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI113_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI113_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 8, i64 8> %3 = icmp ult <2 x i64> %2, <i64 8, i64 8>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_8_v2i64: ; PWR9-LABEL: ugt_8_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI114_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI114_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI114_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 8, i64 8> %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_9_v2i64: ; PWR9-LABEL: ult_9_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI115_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI115_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI115_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI115_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 9, i64 9> %3 = icmp ult <2 x i64> %2, <i64 9, i64 9>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_9_v2i64: ; PWR9-LABEL: ugt_9_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI116_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI116_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI116_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI116_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 9, i64 9> %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_10_v2i64: ; PWR9-LABEL: ult_10_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI117_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI117_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI117_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI117_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 10, i64 10> %3 = icmp ult <2 x i64> %2, <i64 10, i64 10>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_10_v2i64: ; PWR9-LABEL: ugt_10_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI118_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI118_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI118_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI118_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 10, i64 10> %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_11_v2i64: ; PWR9-LABEL: ult_11_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI119_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI119_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI119_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI119_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 11, i64 11> %3 = icmp ult <2 x i64> %2, <i64 11, i64 11>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_11_v2i64: ; PWR9-LABEL: ugt_11_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI120_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI120_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI120_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI120_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 11, i64 11> %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_12_v2i64: ; PWR9-LABEL: ult_12_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI121_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI121_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI121_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 12, i64 12> %3 = icmp ult <2 x i64> %2, <i64 12, i64 12>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_12_v2i64: ; PWR9-LABEL: ugt_12_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI122_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI122_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI122_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI122_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 12, i64 12> %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_13_v2i64: ; PWR9-LABEL: ult_13_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI123_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI123_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI123_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI123_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 13, i64 13> %3 = icmp ult <2 x i64> %2, <i64 13, i64 13>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_13_v2i64: ; PWR9-LABEL: ugt_13_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI124_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI124_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI124_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 13, i64 13> %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_14_v2i64: ; PWR9-LABEL: ult_14_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI125_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI125_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI125_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI125_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 14, i64 14> %3 = icmp ult <2 x i64> %2, <i64 14, i64 14>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_14_v2i64: ; PWR9-LABEL: ugt_14_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI126_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI126_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI126_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 14, i64 14> %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_15_v2i64: ; PWR9-LABEL: ult_15_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI127_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI127_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI127_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI127_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 15, i64 15> %3 = icmp ult <2 x i64> %2, <i64 15, i64 15>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_15_v2i64: ; PWR9-LABEL: ugt_15_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI128_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI128_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI128_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI128_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 15, i64 15> %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_16_v2i64: ; PWR9-LABEL: ult_16_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI129_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI129_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI129_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 16, i64 16> %3 = icmp ult <2 x i64> %2, <i64 16, i64 16>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_16_v2i64: ; PWR9-LABEL: ugt_16_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI130_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI130_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI130_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI130_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 16, i64 16> %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_17_v2i64: ; PWR9-LABEL: ult_17_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI131_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI131_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI131_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI131_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 17, i64 17> %3 = icmp ult <2 x i64> %2, <i64 17, i64 17>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_17_v2i64: ; PWR9-LABEL: ugt_17_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI132_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI132_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI132_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI132_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 17, i64 17> %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_18_v2i64: ; PWR9-LABEL: ult_18_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI133_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI133_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI133_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 18, i64 18> %3 = icmp ult <2 x i64> %2, <i64 18, i64 18>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_18_v2i64: ; PWR9-LABEL: ugt_18_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI134_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI134_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI134_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 18, i64 18> %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_19_v2i64: ; PWR9-LABEL: ult_19_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI135_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI135_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI135_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI135_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 19, i64 19> %3 = icmp ult <2 x i64> %2, <i64 19, i64 19>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_19_v2i64: ; PWR9-LABEL: ugt_19_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI136_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI136_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI136_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 19, i64 19> %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_20_v2i64: ; PWR9-LABEL: ult_20_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI137_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI137_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI137_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 20, i64 20> %3 = icmp ult <2 x i64> %2, <i64 20, i64 20>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_20_v2i64: ; PWR9-LABEL: ugt_20_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI138_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI138_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI138_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI138_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 20, i64 20> %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_21_v2i64: ; PWR9-LABEL: ult_21_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI139_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI139_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI139_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI139_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 21, i64 21> %3 = icmp ult <2 x i64> %2, <i64 21, i64 21>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_21_v2i64: ; PWR9-LABEL: ugt_21_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI140_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI140_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI140_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 21, i64 21> %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_22_v2i64: ; PWR9-LABEL: ult_22_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI141_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI141_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI141_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 22, i64 22> %3 = icmp ult <2 x i64> %2, <i64 22, i64 22>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_22_v2i64: ; PWR9-LABEL: ugt_22_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI142_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI142_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI142_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI142_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 22, i64 22> %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_23_v2i64: ; PWR9-LABEL: ult_23_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI143_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI143_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI143_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI143_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 23, i64 23> %3 = icmp ult <2 x i64> %2, <i64 23, i64 23>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_23_v2i64: ; PWR9-LABEL: ugt_23_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI144_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI144_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI144_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 23, i64 23> %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_24_v2i64: ; PWR9-LABEL: ult_24_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI145_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI145_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI145_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 24, i64 24> %3 = icmp ult <2 x i64> %2, <i64 24, i64 24>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_24_v2i64: ; PWR9-LABEL: ugt_24_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI146_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI146_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI146_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI146_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 24, i64 24> %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_25_v2i64: ; PWR9-LABEL: ult_25_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI147_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI147_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI147_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI147_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 25, i64 25> %3 = icmp ult <2 x i64> %2, <i64 25, i64 25>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_25_v2i64: ; PWR9-LABEL: ugt_25_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI148_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI148_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI148_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 25, i64 25> %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_26_v2i64: ; PWR9-LABEL: ult_26_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI149_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI149_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI149_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 26, i64 26> %3 = icmp ult <2 x i64> %2, <i64 26, i64 26>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_26_v2i64: ; PWR9-LABEL: ugt_26_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI150_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI150_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI150_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI150_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 26, i64 26> %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_27_v2i64: ; PWR9-LABEL: ult_27_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI151_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI151_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI151_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI151_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 27, i64 27> %3 = icmp ult <2 x i64> %2, <i64 27, i64 27>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_27_v2i64: ; PWR9-LABEL: ugt_27_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI152_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI152_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI152_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI152_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 27, i64 27> %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_28_v2i64: ; PWR9-LABEL: ult_28_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI153_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI153_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI153_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI153_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 28, i64 28> %3 = icmp ult <2 x i64> %2, <i64 28, i64 28>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_28_v2i64: ; PWR9-LABEL: ugt_28_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI154_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI154_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI154_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI154_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 28, i64 28> %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_29_v2i64: ; PWR9-LABEL: ult_29_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI155_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI155_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI155_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 29, i64 29> %3 = icmp ult <2 x i64> %2, <i64 29, i64 29>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_29_v2i64: ; PWR9-LABEL: ugt_29_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI156_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI156_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI156_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI156_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 29, i64 29> %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_30_v2i64: ; PWR9-LABEL: ult_30_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI157_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI157_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI157_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI157_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 30, i64 30> %3 = icmp ult <2 x i64> %2, <i64 30, i64 30>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_30_v2i64: ; PWR9-LABEL: ugt_30_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI158_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI158_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI158_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI158_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 30, i64 30> %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_31_v2i64: ; PWR9-LABEL: ult_31_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI159_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI159_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI159_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI159_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 31, i64 31> %3 = icmp ult <2 x i64> %2, <i64 31, i64 31>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_31_v2i64: ; PWR9-LABEL: ugt_31_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI160_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI160_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI160_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI160_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 31, i64 31> %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_32_v2i64: ; PWR9-LABEL: ult_32_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI161_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI161_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI161_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI161_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 32, i64 32> %3 = icmp ult <2 x i64> %2, <i64 32, i64 32>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_32_v2i64: ; PWR9-LABEL: ugt_32_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI162_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI162_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI162_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI162_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 32, i64 32> %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_33_v2i64: ; PWR9-LABEL: ult_33_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI163_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI163_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI163_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI163_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 33, i64 33> %3 = icmp ult <2 x i64> %2, <i64 33, i64 33>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_33_v2i64: ; PWR9-LABEL: ugt_33_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI164_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI164_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI164_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI164_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 33, i64 33> %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_34_v2i64: ; PWR9-LABEL: ult_34_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI165_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI165_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI165_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI165_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 34, i64 34> %3 = icmp ult <2 x i64> %2, <i64 34, i64 34>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_34_v2i64: ; PWR9-LABEL: ugt_34_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI166_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI166_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI166_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI166_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 34, i64 34> %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_35_v2i64: ; PWR9-LABEL: ult_35_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI167_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI167_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI167_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI167_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 35, i64 35> %3 = icmp ult <2 x i64> %2, <i64 35, i64 35>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_35_v2i64: ; PWR9-LABEL: ugt_35_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI168_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI168_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI168_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI168_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 35, i64 35> %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_36_v2i64: ; PWR9-LABEL: ult_36_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI169_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI169_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI169_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI169_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 36, i64 36> %3 = icmp ult <2 x i64> %2, <i64 36, i64 36>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_36_v2i64: ; PWR9-LABEL: ugt_36_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI170_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI170_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI170_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI170_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 36, i64 36> %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_37_v2i64: ; PWR9-LABEL: ult_37_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI171_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI171_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI171_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI171_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 37, i64 37> %3 = icmp ult <2 x i64> %2, <i64 37, i64 37>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_37_v2i64: ; PWR9-LABEL: ugt_37_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI172_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI172_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI172_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI172_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 37, i64 37> %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_38_v2i64: ; PWR9-LABEL: ult_38_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI173_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI173_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI173_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 38, i64 38> %3 = icmp ult <2 x i64> %2, <i64 38, i64 38>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_38_v2i64: ; PWR9-LABEL: ugt_38_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI174_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI174_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI174_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI174_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 38, i64 38> %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_39_v2i64: ; PWR9-LABEL: ult_39_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI175_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI175_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI175_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI175_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 39, i64 39> %3 = icmp ult <2 x i64> %2, <i64 39, i64 39>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_39_v2i64: ; PWR9-LABEL: ugt_39_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI176_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI176_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI176_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI176_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 39, i64 39> %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_40_v2i64: ; PWR9-LABEL: ult_40_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI177_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI177_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI177_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI177_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 40, i64 40> %3 = icmp ult <2 x i64> %2, <i64 40, i64 40>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_40_v2i64: ; PWR9-LABEL: ugt_40_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI178_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI178_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI178_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI178_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 40, i64 40> %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_41_v2i64: ; PWR9-LABEL: ult_41_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI179_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI179_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI179_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI179_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 41, i64 41> %3 = icmp ult <2 x i64> %2, <i64 41, i64 41>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_41_v2i64: ; PWR9-LABEL: ugt_41_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI180_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI180_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI180_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI180_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 41, i64 41> %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_42_v2i64: ; PWR9-LABEL: ult_42_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI181_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI181_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI181_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI181_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 42, i64 42> %3 = icmp ult <2 x i64> %2, <i64 42, i64 42>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_42_v2i64: ; PWR9-LABEL: ugt_42_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI182_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI182_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI182_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI182_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 42, i64 42> %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_43_v2i64: ; PWR9-LABEL: ult_43_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI183_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI183_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI183_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI183_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 43, i64 43> %3 = icmp ult <2 x i64> %2, <i64 43, i64 43>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_43_v2i64: ; PWR9-LABEL: ugt_43_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI184_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI184_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI184_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI184_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 43, i64 43> %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_44_v2i64: ; PWR9-LABEL: ult_44_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI185_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI185_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI185_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI185_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 44, i64 44> %3 = icmp ult <2 x i64> %2, <i64 44, i64 44>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_44_v2i64: ; PWR9-LABEL: ugt_44_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI186_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI186_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI186_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI186_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 44, i64 44> %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_45_v2i64: ; PWR9-LABEL: ult_45_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI187_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI187_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI187_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI187_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 45, i64 45> %3 = icmp ult <2 x i64> %2, <i64 45, i64 45>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_45_v2i64: ; PWR9-LABEL: ugt_45_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI188_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI188_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI188_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI188_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 45, i64 45> %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_46_v2i64: ; PWR9-LABEL: ult_46_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI189_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI189_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI189_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI189_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 46, i64 46> %3 = icmp ult <2 x i64> %2, <i64 46, i64 46>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_46_v2i64: ; PWR9-LABEL: ugt_46_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI190_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI190_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI190_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI190_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 46, i64 46> %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_47_v2i64: ; PWR9-LABEL: ult_47_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI191_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI191_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI191_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI191_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 47, i64 47> %3 = icmp ult <2 x i64> %2, <i64 47, i64 47>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_47_v2i64: ; PWR9-LABEL: ugt_47_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI192_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI192_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI192_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI192_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 47, i64 47> %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_48_v2i64: ; PWR9-LABEL: ult_48_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI193_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI193_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI193_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI193_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 48, i64 48> %3 = icmp ult <2 x i64> %2, <i64 48, i64 48>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_48_v2i64: ; PWR9-LABEL: ugt_48_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI194_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI194_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI194_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI194_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 48, i64 48> %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_49_v2i64: ; PWR9-LABEL: ult_49_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI195_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI195_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI195_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI195_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 49, i64 49> %3 = icmp ult <2 x i64> %2, <i64 49, i64 49>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_49_v2i64: ; PWR9-LABEL: ugt_49_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI196_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI196_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI196_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI196_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 49, i64 49> %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_50_v2i64: ; PWR9-LABEL: ult_50_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI197_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI197_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI197_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI197_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 50, i64 50> %3 = icmp ult <2 x i64> %2, <i64 50, i64 50>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_50_v2i64: ; PWR9-LABEL: ugt_50_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI198_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI198_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI198_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI198_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 50, i64 50> %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_51_v2i64: ; PWR9-LABEL: ult_51_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI199_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI199_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI199_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI199_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 51, i64 51> %3 = icmp ult <2 x i64> %2, <i64 51, i64 51>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_51_v2i64: ; PWR9-LABEL: ugt_51_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI200_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI200_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI200_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI200_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 51, i64 51> %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_52_v2i64: ; PWR9-LABEL: ult_52_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI201_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI201_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI201_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI201_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 52, i64 52> %3 = icmp ult <2 x i64> %2, <i64 52, i64 52>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_52_v2i64: ; PWR9-LABEL: ugt_52_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI202_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI202_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI202_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI202_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 52, i64 52> %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_53_v2i64: ; PWR9-LABEL: ult_53_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI203_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI203_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI203_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI203_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 53, i64 53> %3 = icmp ult <2 x i64> %2, <i64 53, i64 53>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_53_v2i64: ; PWR9-LABEL: ugt_53_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI204_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI204_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI204_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI204_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 53, i64 53> %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_54_v2i64: ; PWR9-LABEL: ult_54_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI205_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI205_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI205_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI205_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 54, i64 54> %3 = icmp ult <2 x i64> %2, <i64 54, i64 54>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_54_v2i64: ; PWR9-LABEL: ugt_54_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI206_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI206_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI206_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI206_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 54, i64 54> %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_55_v2i64: ; PWR9-LABEL: ult_55_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI207_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI207_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI207_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI207_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 55, i64 55> %3 = icmp ult <2 x i64> %2, <i64 55, i64 55>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_55_v2i64: ; PWR9-LABEL: ugt_55_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI208_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI208_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI208_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI208_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 55, i64 55> %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_56_v2i64: ; PWR9-LABEL: ult_56_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI209_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI209_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI209_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI209_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 56, i64 56> %3 = icmp ult <2 x i64> %2, <i64 56, i64 56>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_56_v2i64: ; PWR9-LABEL: ugt_56_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI210_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI210_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI210_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI210_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 56, i64 56> %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_57_v2i64: ; PWR9-LABEL: ult_57_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI211_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI211_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI211_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI211_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 57, i64 57> %3 = icmp ult <2 x i64> %2, <i64 57, i64 57>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_57_v2i64: ; PWR9-LABEL: ugt_57_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI212_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI212_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI212_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI212_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 57, i64 57> %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_58_v2i64: ; PWR9-LABEL: ult_58_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI213_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI213_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI213_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI213_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 58, i64 58> %3 = icmp ult <2 x i64> %2, <i64 58, i64 58>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_58_v2i64: ; PWR9-LABEL: ugt_58_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI214_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI214_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI214_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI214_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 58, i64 58> %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_59_v2i64: ; PWR9-LABEL: ult_59_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI215_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI215_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI215_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI215_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 59, i64 59> %3 = icmp ult <2 x i64> %2, <i64 59, i64 59>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_59_v2i64: ; PWR9-LABEL: ugt_59_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI216_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI216_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI216_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI216_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 59, i64 59> %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_60_v2i64: ; PWR9-LABEL: ult_60_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI217_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI217_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI217_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI217_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 60, i64 60> %3 = icmp ult <2 x i64> %2, <i64 60, i64 60>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_60_v2i64: ; PWR9-LABEL: ugt_60_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI218_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI218_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI218_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI218_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 60, i64 60> %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_61_v2i64: ; PWR9-LABEL: ult_61_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI219_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI219_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI219_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI219_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 61, i64 61> %3 = icmp ult <2 x i64> %2, <i64 61, i64 61>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_61_v2i64: ; PWR9-LABEL: ugt_61_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI220_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI220_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI220_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI220_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 61, i64 61> %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_62_v2i64: ; PWR9-LABEL: ult_62_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI221_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI221_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI221_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI221_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 62, i64 62> %3 = icmp ult <2 x i64> %2, <i64 62, i64 62>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 2, 3 ; PWR8-NEXT: vcmpgtud 2, 2, 3
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ugt_62_v2i64: ; PWR9-LABEL: ugt_62_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI222_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI222_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI222_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI222_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: vcmpgtud 2, 2, 3
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ugt <2 x i64> %2, <i64 62, i64 62> %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
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; PWR8-NEXT: vcmpgtud 2, 3, 2 ; PWR8-NEXT: vcmpgtud 2, 3, 2
; PWR8-NEXT: blr ; PWR8-NEXT: blr
; ;
; PWR9-LABEL: ult_63_v2i64: ; PWR9-LABEL: ult_63_v2i64:
; PWR9: # %bb.0: ; PWR9: # %bb.0:
; PWR9-NEXT: addis 3, 2, .LCPI223_0@toc@ha ; PWR9-NEXT: addis 3, 2, .LCPI223_0@toc@ha
; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: vpopcntd 2, 2
; PWR9-NEXT: addi 3, 3, .LCPI223_0@toc@l ; PWR9-NEXT: addi 3, 3, .LCPI223_0@toc@l
; PWR9-NEXT: lxvx 35, 0, 3 ; PWR9-NEXT: lxv 35, 0(3)
; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: vcmpgtud 2, 3, 2
; PWR9-NEXT: blr ; PWR9-NEXT: blr
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 63, i64 63> %3 = icmp ult <2 x i64> %2, <i64 63, i64 63>
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)

llvm/test/CodeGen/PowerPC/vsx-p9.ll

Show All 30 Lines
define void @_Z4testv() { define void @_Z4testv() {
entry: entry:
; CHECK-LABEL: @_Z4testv ; CHECK-LABEL: @_Z4testv
%0 = load <16 x i8>, <16 x i8>* @uca, align 16 %0 = load <16 x i8>, <16 x i8>* @uca, align 16
%1 = load <16 x i8>, <16 x i8>* @ucb, align 16 %1 = load <16 x i8>, <16 x i8>* @ucb, align 16
%add.i = add <16 x i8> %1, %0 %add.i = add <16 x i8> %1, %0
tail call void (...) @sink(<16 x i8> %add.i) tail call void (...) @sink(<16 x i8> %add.i)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vaddubm 2, 3, 2 ; CHECK: vaddubm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%2 = load <16 x i8>, <16 x i8>* @sca, align 16 %2 = load <16 x i8>, <16 x i8>* @sca, align 16
%3 = load <16 x i8>, <16 x i8>* @scb, align 16 %3 = load <16 x i8>, <16 x i8>* @scb, align 16
%add.i22 = add <16 x i8> %3, %2 %add.i22 = add <16 x i8> %3, %2
tail call void (...) @sink(<16 x i8> %add.i22) tail call void (...) @sink(<16 x i8> %add.i22)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vaddubm 2, 3, 2 ; CHECK: vaddubm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%4 = load <8 x i16>, <8 x i16>* @usa, align 16 %4 = load <8 x i16>, <8 x i16>* @usa, align 16
%5 = load <8 x i16>, <8 x i16>* @usb, align 16 %5 = load <8 x i16>, <8 x i16>* @usb, align 16
%add.i21 = add <8 x i16> %5, %4 %add.i21 = add <8 x i16> %5, %4
tail call void (...) @sink(<8 x i16> %add.i21) tail call void (...) @sink(<8 x i16> %add.i21)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduhm 2, 3, 2 ; CHECK: vadduhm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%6 = load <8 x i16>, <8 x i16>* @ssa, align 16 %6 = load <8 x i16>, <8 x i16>* @ssa, align 16
%7 = load <8 x i16>, <8 x i16>* @ssb, align 16 %7 = load <8 x i16>, <8 x i16>* @ssb, align 16
%add.i20 = add <8 x i16> %7, %6 %add.i20 = add <8 x i16> %7, %6
tail call void (...) @sink(<8 x i16> %add.i20) tail call void (...) @sink(<8 x i16> %add.i20)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduhm 2, 3, 2 ; CHECK: vadduhm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%8 = load <4 x i32>, <4 x i32>* @uia, align 16 %8 = load <4 x i32>, <4 x i32>* @uia, align 16
%9 = load <4 x i32>, <4 x i32>* @uib, align 16 %9 = load <4 x i32>, <4 x i32>* @uib, align 16
%add.i19 = add <4 x i32> %9, %8 %add.i19 = add <4 x i32> %9, %8
tail call void (...) @sink(<4 x i32> %add.i19) tail call void (...) @sink(<4 x i32> %add.i19)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduwm 2, 3, 2 ; CHECK: vadduwm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%10 = load <4 x i32>, <4 x i32>* @sia, align 16 %10 = load <4 x i32>, <4 x i32>* @sia, align 16
%11 = load <4 x i32>, <4 x i32>* @sib, align 16 %11 = load <4 x i32>, <4 x i32>* @sib, align 16
%add.i18 = add <4 x i32> %11, %10 %add.i18 = add <4 x i32> %11, %10
tail call void (...) @sink(<4 x i32> %add.i18) tail call void (...) @sink(<4 x i32> %add.i18)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduwm 2, 3, 2 ; CHECK: vadduwm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%12 = load <2 x i64>, <2 x i64>* @ulla, align 16 %12 = load <2 x i64>, <2 x i64>* @ulla, align 16
%13 = load <2 x i64>, <2 x i64>* @ullb, align 16 %13 = load <2 x i64>, <2 x i64>* @ullb, align 16
%add.i17 = add <2 x i64> %13, %12 %add.i17 = add <2 x i64> %13, %12
tail call void (...) @sink(<2 x i64> %add.i17) tail call void (...) @sink(<2 x i64> %add.i17)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vaddudm 2, 3, 2 ; CHECK: vaddudm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%14 = load <2 x i64>, <2 x i64>* @slla, align 16 %14 = load <2 x i64>, <2 x i64>* @slla, align 16
%15 = load <2 x i64>, <2 x i64>* @sllb, align 16 %15 = load <2 x i64>, <2 x i64>* @sllb, align 16
%add.i16 = add <2 x i64> %15, %14 %add.i16 = add <2 x i64> %15, %14
tail call void (...) @sink(<2 x i64> %add.i16) tail call void (...) @sink(<2 x i64> %add.i16)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vaddudm 2, 3, 2 ; CHECK: vaddudm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%16 = load <1 x i128>, <1 x i128>* @uxa, align 16 %16 = load <1 x i128>, <1 x i128>* @uxa, align 16
%17 = load <1 x i128>, <1 x i128>* @uxb, align 16 %17 = load <1 x i128>, <1 x i128>* @uxb, align 16
%add.i15 = add <1 x i128> %17, %16 %add.i15 = add <1 x i128> %17, %16
tail call void (...) @sink(<1 x i128> %add.i15) tail call void (...) @sink(<1 x i128> %add.i15)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduqm 2, 3, 2 ; CHECK: vadduqm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%18 = load <1 x i128>, <1 x i128>* @sxa, align 16 %18 = load <1 x i128>, <1 x i128>* @sxa, align 16
%19 = load <1 x i128>, <1 x i128>* @sxb, align 16 %19 = load <1 x i128>, <1 x i128>* @sxb, align 16
%add.i14 = add <1 x i128> %19, %18 %add.i14 = add <1 x i128> %19, %18
tail call void (...) @sink(<1 x i128> %add.i14) tail call void (...) @sink(<1 x i128> %add.i14)
; CHECK: lxvx 34, 0, 3 ; CHECK: lxv 34, 0(3)
; CHECK: lxvx 35, 0, 3 ; CHECK: lxv 35, 0(3)
; CHECK: vadduqm 2, 3, 2 ; CHECK: vadduqm 2, 3, 2
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%20 = load <4 x float>, <4 x float>* @vfa, align 16 %20 = load <4 x float>, <4 x float>* @vfa, align 16
%21 = load <4 x float>, <4 x float>* @vfb, align 16 %21 = load <4 x float>, <4 x float>* @vfb, align 16
%add.i13 = fadd <4 x float> %20, %21 %add.i13 = fadd <4 x float> %20, %21
tail call void (...) @sink(<4 x float> %add.i13) tail call void (...) @sink(<4 x float> %add.i13)
; CHECK: lxvx 0, 0, 3 ; CHECK: lxv 0, 0(3)
; CHECK: lxvx 1, 0, 3 ; CHECK: lxv 1, 0(3)
; CHECK: xvaddsp 34, 0, 1 ; CHECK: xvaddsp 34, 0, 1
; CHECK: stxv 34, ; CHECK: stxv 34,
; CHECK: bl sink ; CHECK: bl sink
%22 = load <2 x double>, <2 x double>* @vda, align 16 %22 = load <2 x double>, <2 x double>* @vda, align 16
%23 = load <2 x double>, <2 x double>* @vdb, align 16 %23 = load <2 x double>, <2 x double>* @vdb, align 16
%add.i12 = fadd <2 x double> %22, %23 %add.i12 = fadd <2 x double> %22, %23
tail call void (...) @sink(<2 x double> %add.i12) tail call void (...) @sink(<2 x double> %add.i12)
; CHECK: lxvx 0, 0, 3 ; CHECK: lxv 0, 0(3)
; CHECK: lxvx 1, 0, 3 ; CHECK: lxv 1, 0(3)
; CHECK: xvadddp 0, 0, 1 ; CHECK: xvadddp 0, 0, 1
; CHECK: stxv 0, ; CHECK: stxv 0,
; CHECK: bl sink ; CHECK: bl sink
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) { define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) {
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llvm/test/CodeGen/PowerPC/vsx.ll

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; CHECK-LABEL: test44: ; CHECK-LABEL: test44:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi r3, r1, -16 ; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: addi r4, r1, -64 ; CHECK-NEXT: addi r4, r1, -64
; CHECK-NEXT: stxvd2x v2, 0, r3 ; CHECK-NEXT: stxvd2x v2, 0, r3
; CHECK-NEXT: ld r3, -8(r1) ; CHECK-NEXT: ld r3, -8(r1)
; CHECK-NEXT: std r3, -24(r1) ; CHECK-NEXT: std r3, -24(r1)
; CHECK-NEXT: ld r3, -16(r1) ; CHECK-NEXT: ld r3, -16(r1)
; CHECK-NEXT: std r3, -32(r1)
; CHECK-NEXT: lfd f0, -24(r1) ; CHECK-NEXT: lfd f0, -24(r1)
; CHECK-NEXT: std r3, -32(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: fcfidus f0, f0 ; CHECK-NEXT: fcfidus f0, f0
; CHECK-NEXT: stfs f0, -48(r1) ; CHECK-NEXT: stfs f0, -48(r1)
; CHECK-NEXT: lfd f0, -32(r1) ; CHECK-NEXT: lfd f0, -32(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: fcfidus f0, f0 ; CHECK-NEXT: fcfidus f0, f0
; CHECK-NEXT: stfs f0, -64(r1) ; CHECK-NEXT: stfs f0, -64(r1)
; CHECK-NEXT: lxvw4x v2, 0, r3 ; CHECK-NEXT: lxvw4x v2, 0, r3
; CHECK-NEXT: lxvw4x v3, 0, r4 ; CHECK-NEXT: lxvw4x v3, 0, r4
; CHECK-NEXT: vmrghw v2, v3, v2 ; CHECK-NEXT: vmrghw v2, v3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-REG-LABEL: test44: ; CHECK-REG-LABEL: test44:
; CHECK-REG: # %bb.0: ; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: addi r3, r1, -16 ; CHECK-REG-NEXT: addi r3, r1, -16
; CHECK-REG-NEXT: addi r4, r1, -64 ; CHECK-REG-NEXT: addi r4, r1, -64
; CHECK-REG-NEXT: stxvd2x v2, 0, r3 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
; CHECK-REG-NEXT: ld r3, -8(r1) ; CHECK-REG-NEXT: ld r3, -8(r1)
; CHECK-REG-NEXT: std r3, -24(r1) ; CHECK-REG-NEXT: std r3, -24(r1)
; CHECK-REG-NEXT: ld r3, -16(r1) ; CHECK-REG-NEXT: ld r3, -16(r1)
; CHECK-REG-NEXT: std r3, -32(r1)
; CHECK-REG-NEXT: lfd f0, -24(r1) ; CHECK-REG-NEXT: lfd f0, -24(r1)
; CHECK-REG-NEXT: std r3, -32(r1)
; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: fcfidus f0, f0 ; CHECK-REG-NEXT: fcfidus f0, f0
; CHECK-REG-NEXT: stfs f0, -48(r1) ; CHECK-REG-NEXT: stfs f0, -48(r1)
; CHECK-REG-NEXT: lfd f0, -32(r1) ; CHECK-REG-NEXT: lfd f0, -32(r1)
; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: fcfidus f0, f0 ; CHECK-REG-NEXT: fcfidus f0, f0
; CHECK-REG-NEXT: stfs f0, -64(r1) ; CHECK-REG-NEXT: stfs f0, -64(r1)
; CHECK-REG-NEXT: lxvw4x v2, 0, r3 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
; CHECK-REG-NEXT: lxvw4x v3, 0, r4 ; CHECK-REG-NEXT: lxvw4x v3, 0, r4
; CHECK-REG-NEXT: vmrghw v2, v3, v2 ; CHECK-REG-NEXT: vmrghw v2, v3, v2
; CHECK-REG-NEXT: blr ; CHECK-REG-NEXT: blr
; ;
; CHECK-FISL-LABEL: test44: ; CHECK-FISL-LABEL: test44:
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; CHECK-LABEL: test45: ; CHECK-LABEL: test45:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi r3, r1, -16 ; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: addi r4, r1, -64 ; CHECK-NEXT: addi r4, r1, -64
; CHECK-NEXT: stxvd2x v2, 0, r3 ; CHECK-NEXT: stxvd2x v2, 0, r3
; CHECK-NEXT: ld r3, -8(r1) ; CHECK-NEXT: ld r3, -8(r1)
; CHECK-NEXT: std r3, -24(r1) ; CHECK-NEXT: std r3, -24(r1)
; CHECK-NEXT: ld r3, -16(r1) ; CHECK-NEXT: ld r3, -16(r1)
; CHECK-NEXT: std r3, -32(r1)
; CHECK-NEXT: lfd f0, -24(r1) ; CHECK-NEXT: lfd f0, -24(r1)
; CHECK-NEXT: std r3, -32(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: fcfids f0, f0 ; CHECK-NEXT: fcfids f0, f0
; CHECK-NEXT: stfs f0, -48(r1) ; CHECK-NEXT: stfs f0, -48(r1)
; CHECK-NEXT: lfd f0, -32(r1) ; CHECK-NEXT: lfd f0, -32(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: fcfids f0, f0 ; CHECK-NEXT: fcfids f0, f0
; CHECK-NEXT: stfs f0, -64(r1) ; CHECK-NEXT: stfs f0, -64(r1)
; CHECK-NEXT: lxvw4x v2, 0, r3 ; CHECK-NEXT: lxvw4x v2, 0, r3
; CHECK-NEXT: lxvw4x v3, 0, r4 ; CHECK-NEXT: lxvw4x v3, 0, r4
; CHECK-NEXT: vmrghw v2, v3, v2 ; CHECK-NEXT: vmrghw v2, v3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-REG-LABEL: test45: ; CHECK-REG-LABEL: test45:
; CHECK-REG: # %bb.0: ; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: addi r3, r1, -16 ; CHECK-REG-NEXT: addi r3, r1, -16
; CHECK-REG-NEXT: addi r4, r1, -64 ; CHECK-REG-NEXT: addi r4, r1, -64
; CHECK-REG-NEXT: stxvd2x v2, 0, r3 ; CHECK-REG-NEXT: stxvd2x v2, 0, r3
; CHECK-REG-NEXT: ld r3, -8(r1) ; CHECK-REG-NEXT: ld r3, -8(r1)
; CHECK-REG-NEXT: std r3, -24(r1) ; CHECK-REG-NEXT: std r3, -24(r1)
; CHECK-REG-NEXT: ld r3, -16(r1) ; CHECK-REG-NEXT: ld r3, -16(r1)
; CHECK-REG-NEXT: std r3, -32(r1)
; CHECK-REG-NEXT: lfd f0, -24(r1) ; CHECK-REG-NEXT: lfd f0, -24(r1)
; CHECK-REG-NEXT: std r3, -32(r1)
; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: fcfids f0, f0 ; CHECK-REG-NEXT: fcfids f0, f0
; CHECK-REG-NEXT: stfs f0, -48(r1) ; CHECK-REG-NEXT: stfs f0, -48(r1)
; CHECK-REG-NEXT: lfd f0, -32(r1) ; CHECK-REG-NEXT: lfd f0, -32(r1)
; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: fcfids f0, f0 ; CHECK-REG-NEXT: fcfids f0, f0
; CHECK-REG-NEXT: stfs f0, -64(r1) ; CHECK-REG-NEXT: stfs f0, -64(r1)
; CHECK-REG-NEXT: lxvw4x v2, 0, r3 ; CHECK-REG-NEXT: lxvw4x v2, 0, r3
; CHECK-REG-NEXT: lxvw4x v3, 0, r4 ; CHECK-REG-NEXT: lxvw4x v3, 0, r4
; CHECK-REG-NEXT: vmrghw v2, v3, v2 ; CHECK-REG-NEXT: vmrghw v2, v3, v2
; CHECK-REG-NEXT: blr ; CHECK-REG-NEXT: blr
; ;
; CHECK-FISL-LABEL: test45: ; CHECK-FISL-LABEL: test45:
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; CHECK-LABEL: test46: ; CHECK-LABEL: test46:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: stxvw4x v2, 0, r3 ; CHECK-NEXT: stxvw4x v2, 0, r3
; CHECK-NEXT: lfs f0, -44(r1) ; CHECK-NEXT: lfs f0, -44(r1)
; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: stfd f0, -32(r1) ; CHECK-NEXT: stfd f0, -32(r1)
; CHECK-NEXT: lfs f0, -48(r1) ; CHECK-NEXT: lfs f0, -48(r1)
; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: stfd f0, -24(r1)
; CHECK-NEXT: ld r3, -32(r1) ; CHECK-NEXT: ld r3, -32(r1)
; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: std r3, -8(r1) ; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: stfd f0, -24(r1)
; CHECK-NEXT: ld r3, -24(r1) ; CHECK-NEXT: ld r3, -24(r1)
; CHECK-NEXT: std r3, -16(r1) ; CHECK-NEXT: std r3, -16(r1)
; CHECK-NEXT: addi r3, r1, -16 ; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: lxvd2x v2, 0, r3 ; CHECK-NEXT: lxvd2x v2, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-REG-LABEL: test46: ; CHECK-REG-LABEL: test46:
; CHECK-REG: # %bb.0: ; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: stxvw4x v2, 0, r3 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
; CHECK-REG-NEXT: lfs f0, -44(r1) ; CHECK-REG-NEXT: lfs f0, -44(r1)
; CHECK-REG-NEXT: xscvdpuxds f0, f0 ; CHECK-REG-NEXT: xscvdpuxds f0, f0
; CHECK-REG-NEXT: stfd f0, -32(r1) ; CHECK-REG-NEXT: stfd f0, -32(r1)
; CHECK-REG-NEXT: lfs f0, -48(r1) ; CHECK-REG-NEXT: lfs f0, -48(r1)
; CHECK-REG-NEXT: xscvdpuxds f0, f0
; CHECK-REG-NEXT: stfd f0, -24(r1)
; CHECK-REG-NEXT: ld r3, -32(r1) ; CHECK-REG-NEXT: ld r3, -32(r1)
; CHECK-REG-NEXT: xscvdpuxds f0, f0
; CHECK-REG-NEXT: std r3, -8(r1) ; CHECK-REG-NEXT: std r3, -8(r1)
; CHECK-REG-NEXT: stfd f0, -24(r1)
; CHECK-REG-NEXT: ld r3, -24(r1) ; CHECK-REG-NEXT: ld r3, -24(r1)
; CHECK-REG-NEXT: std r3, -16(r1) ; CHECK-REG-NEXT: std r3, -16(r1)
; CHECK-REG-NEXT: addi r3, r1, -16 ; CHECK-REG-NEXT: addi r3, r1, -16
; CHECK-REG-NEXT: lxvd2x v2, 0, r3 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
; CHECK-REG-NEXT: blr ; CHECK-REG-NEXT: blr
; ;
; CHECK-FISL-LABEL: test46: ; CHECK-FISL-LABEL: test46:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
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; CHECK-LABEL: test47: ; CHECK-LABEL: test47:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: stxvw4x v2, 0, r3 ; CHECK-NEXT: stxvw4x v2, 0, r3
; CHECK-NEXT: lfs f0, -44(r1) ; CHECK-NEXT: lfs f0, -44(r1)
; CHECK-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-NEXT: stfd f0, -32(r1) ; CHECK-NEXT: stfd f0, -32(r1)
; CHECK-NEXT: lfs f0, -48(r1) ; CHECK-NEXT: lfs f0, -48(r1)
; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-NEXT: stfd f0, -24(r1)
; CHECK-NEXT: ld r3, -32(r1) ; CHECK-NEXT: ld r3, -32(r1)
; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-NEXT: std r3, -8(r1) ; CHECK-NEXT: std r3, -8(r1)
; CHECK-NEXT: stfd f0, -24(r1)
; CHECK-NEXT: ld r3, -24(r1) ; CHECK-NEXT: ld r3, -24(r1)
; CHECK-NEXT: std r3, -16(r1) ; CHECK-NEXT: std r3, -16(r1)
; CHECK-NEXT: addi r3, r1, -16 ; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: lxvd2x v2, 0, r3 ; CHECK-NEXT: lxvd2x v2, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-REG-LABEL: test47: ; CHECK-REG-LABEL: test47:
; CHECK-REG: # %bb.0: ; CHECK-REG: # %bb.0:
; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: addi r3, r1, -48
; CHECK-REG-NEXT: stxvw4x v2, 0, r3 ; CHECK-REG-NEXT: stxvw4x v2, 0, r3
; CHECK-REG-NEXT: lfs f0, -44(r1) ; CHECK-REG-NEXT: lfs f0, -44(r1)
; CHECK-REG-NEXT: xscvdpsxds f0, f0 ; CHECK-REG-NEXT: xscvdpsxds f0, f0
; CHECK-REG-NEXT: stfd f0, -32(r1) ; CHECK-REG-NEXT: stfd f0, -32(r1)
; CHECK-REG-NEXT: lfs f0, -48(r1) ; CHECK-REG-NEXT: lfs f0, -48(r1)
; CHECK-REG-NEXT: xscvdpsxds f0, f0
; CHECK-REG-NEXT: stfd f0, -24(r1)
; CHECK-REG-NEXT: ld r3, -32(r1) ; CHECK-REG-NEXT: ld r3, -32(r1)
; CHECK-REG-NEXT: xscvdpsxds f0, f0
; CHECK-REG-NEXT: std r3, -8(r1) ; CHECK-REG-NEXT: std r3, -8(r1)
; CHECK-REG-NEXT: stfd f0, -24(r1)
; CHECK-REG-NEXT: ld r3, -24(r1) ; CHECK-REG-NEXT: ld r3, -24(r1)
; CHECK-REG-NEXT: std r3, -16(r1) ; CHECK-REG-NEXT: std r3, -16(r1)
; CHECK-REG-NEXT: addi r3, r1, -16 ; CHECK-REG-NEXT: addi r3, r1, -16
; CHECK-REG-NEXT: lxvd2x v2, 0, r3 ; CHECK-REG-NEXT: lxvd2x v2, 0, r3
; CHECK-REG-NEXT: blr ; CHECK-REG-NEXT: blr
; ;
; CHECK-FISL-LABEL: test47: ; CHECK-FISL-LABEL: test47:
; CHECK-FISL: # %bb.0: ; CHECK-FISL: # %bb.0:
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llvm/test/CodeGen/PowerPC/vsx_builtins.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \ ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-P9
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN
; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-P9
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-INTRIN
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefixes=CHECK,CHECK-INTRIN
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define <4 x i32> @test1(i8* %a) { define <4 x i32> @test1(i8* %a) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvw4x v2, 0, r3 ; CHECK-NEXT: lxvw4x v2, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
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; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31 ; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
%1 = lshr i32 %0, 4 %1 = lshr i32 %0, 4
%.lobit = and i32 %1, 1 %.lobit = and i32 %1, 1
ret i32 %.lobit ret i32 %.lobit
} }
; Function Attrs: nounwind readnone
define <2 x double> @test_lxvd2x(i8* %a) {
; CHECK-P9-LABEL: test_lxvd2x:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv v2, 0(r3)
; CHECK-P9-NEXT: blr
;
; CHECK-NOINTRIN-LABEL: test_lxvd2x:
; CHECK-NOINTRIN: # %bb.0: # %entry
; CHECK-NOINTRIN-NEXT: lxvd2x vs0, 0, r3
; CHECK-NOINTRIN-NEXT: xxswapd v2, vs0
; CHECK-NOINTRIN-NEXT: blr
;
; CHECK-INTRIN-LABEL: test_lxvd2x:
; CHECK-INTRIN: # %bb.0: # %entry
; CHECK-INTRIN-NEXT: lxvd2x v2, 0, r3
; CHECK-INTRIN-NEXT: blr
entry:
%0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %a)
ret <2 x double> %0
}
; Function Attrs: nounwind readnone
declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
; Function Attrs: nounwind readnone
define void @test_stxvd2x(<2 x double> %a, i8* %b) {
; CHECK-P9-LABEL: test_stxvd2x:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: stxv v2, 0(r5)
; CHECK-P9-NEXT: blr
;
; CHECK-NOINTRIN-LABEL: test_stxvd2x:
; CHECK-NOINTRIN: # %bb.0: # %entry
; CHECK-NOINTRIN-NEXT: xxswapd vs0, v2
; CHECK-NOINTRIN-NEXT: stxvd2x vs0, 0, r5
; CHECK-NOINTRIN-NEXT: blr
;
; CHECK-INTRIN-LABEL: test_stxvd2x:
; CHECK-INTRIN: # %bb.0: # %entry
; CHECK-INTRIN-NEXT: stxvd2x v2, 0, r5
; CHECK-INTRIN-NEXT: blr
entry:
tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, i8* %b)
ret void
}
; Function Attrs: nounwind readnone
declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)

llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

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define void @dblToFloat() #0 { define void @dblToFloat() #0 {
entry: entry:
%ff = alloca float, align 4 %ff = alloca float, align 4
%0 = load double, double* @d, align 8 %0 = load double, double* @d, align 8
%conv = fptrunc double %0 to float %conv = fptrunc double %0 to float
store volatile float %conv, float* %ff, align 4 store volatile float %conv, float* %ff, align 4
ret void ret void
; CHECK-LABEL: @dblToFloat ; CHECK-LABEL: @dblToFloat
; CHECK: lfdx [[REGLD5:[0-9]+]], ; CHECK: lfd [[REGLD5:[0-9]+]],
; CHECK: stfs [[REGLD5]], ; CHECK: stfs [[REGLD5]],
; CHECK-P9-LABEL: @dblToFloat ; CHECK-P9-LABEL: @dblToFloat
; CHECK-P9: lfd [[REGLD5:[0-9]+]], ; CHECK-P9: lfd [[REGLD5:[0-9]+]],
; CHECK-P9: stfs [[REGLD5]], ; CHECK-P9: stfs [[REGLD5]],
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @floatToDbl() #0 { define void @floatToDbl() #0 {
entry: entry:
%dd = alloca double, align 8 %dd = alloca double, align 8
%0 = load float, float* @f, align 4 %0 = load float, float* @f, align 4
%conv = fpext float %0 to double %conv = fpext float %0 to double
store volatile double %conv, double* %dd, align 8 store volatile double %conv, double* %dd, align 8
ret void ret void
; CHECK-LABEL: @floatToDbl ; CHECK-LABEL: @floatToDbl
; CHECK: lfsx [[REGLD5:[0-9]+]], ; CHECK: lfs [[REGLD5:[0-9]+]],
; CHECK: stfd [[REGLD5]], ; CHECK: stfd [[REGLD5]],
; CHECK-P9-LABEL: @floatToDbl ; CHECK-P9-LABEL: @floatToDbl
; CHECK-P9: lfs [[REGLD5:[0-9]+]], ; CHECK-P9: lfs [[REGLD5:[0-9]+]],
; CHECK-P9: stfd [[REGLD5]], ; CHECK-P9: stfd [[REGLD5]],
} }