[ARM] Turn sext_inreg(VGetLaneu) into VGetLaneu

[dmgreen]

Summary

This adds a DAG combine for converting sext_inreg of VGetLaneu into VGetLanes, providing the types match correctly.

[SjoerdMeijer]

LGTM

[dmgreen]

Thanks

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (Subtarget->hasNEON()) {
     }
   }
 
   if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
     setTargetDAGCombine(ISD::BUILD_VECTOR);
     setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
     setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
     setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
+    setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
     setTargetDAGCombine(ISD::STORE);
     setTargetDAGCombine(ISD::SIGN_EXTEND);
     setTargetDAGCombine(ISD::ZERO_EXTEND);
     setTargetDAGCombine(ISD::ANY_EXTEND);
     setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
     setTargetDAGCombine(ISD::INTRINSIC_VOID);
     setTargetDAGCombine(ISD::VECREDUCE_ADD);
if (Op0.getValueType() == MVT::v4i32 &&
     SDValue MOV = BV.getOperand(Offset < 2 ? 0 : 1);
     if (MOV.getOpcode() == ARMISD::VMOVDRR)
       return MOV.getOperand(ST->isLittle() ? Offset % 2 : 1 - Offset % 2);
   }
 
   return SDValue();
 }
 
+static SDValue PerformSignExtendInregCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Op = N->getOperand(0);
+  EVT VT = N->getValueType(0);
+
+  // sext_inreg(VGETLANEu) -> VGETLANEs
+  if (Op.getOpcode() == ARMISD::VGETLANEu &&
+      cast<VTSDNode>(N->getOperand(1))->getVT() ==
+          Op.getOperand(0).getValueType().getScalarType())
+    return DAG.getNode(ARMISD::VGETLANEs, SDLoc(N), VT, Op.getOperand(0),
+                       Op.getOperand(1));
+
+  return SDValue();
+}
+
 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
 /// ISD::VECTOR_SHUFFLE.
 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
   // The LLVM shufflevector instruction does not require the shuffle mask
   // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
   // have that requirement.  When translating to ISD::VECTOR_SHUFFLE, if the
   // operands do not match the mask length, they are extended by concatenating
   // them with undef vectors.  That is probably the right thing for other
SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
   case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
   case ARMISD::VMOVhr:  return PerformVMOVhrCombine(N, DCI);
   case ARMISD::VMOVrh:  return PerformVMOVrhCombine(N, DCI);
   case ISD::STORE:      return PerformSTORECombine(N, DCI, Subtarget);
   case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
   case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
   case ISD::EXTRACT_VECTOR_ELT:
     return PerformExtractEltCombine(N, DCI, Subtarget);
+  case ISD::SIGN_EXTEND_INREG: return PerformSignExtendInregCombine(N, DCI.DAG);
   case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
   case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget);
   case ARMISD::VDUP: return PerformVDUPCombine(N, DCI, Subtarget);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
     return PerformVCVTCombine(N, DCI.DAG, Subtarget);
   case ISD::FDIV:
     return PerformVDIVCombine(N, DCI.DAG, Subtarget);

llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
 define float @f(<4 x i16>* nocapture %in) {
 ; CHECK-LABEL: f:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.16 {d16}, [r0:64]
 ; CHECK-NEXT:    vmovl.u16 q8, d16
 ; CHECK-NEXT:    vcvt.f32.u32 q0, q8
; CHECK-NEXT:    bx lr
   %10 = insertelement <4 x i32> %7, i32 %9, i32 2
   %11 = extractelement <4 x i8> %1, i32 3
   %12 = zext i8 %11 to i32
   %13 = insertelement <4 x i32> %10, i32 %12, i32 3
   ret <4 x i32> %13
 }
 
 define float @i(<4 x i16>* nocapture %in) {
-  ; FIXME: The vmov.u + sxt can convert to a vmov.s
 ; CHECK-LABEL: i:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [r0]
-; CHECK-NEXT:    vmov.u16 r0, d16[0]
-; CHECK-NEXT:    sxth r0, r0
+; CHECK-NEXT:    vmov.s16 r0, d16[0]
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
   %1 = load <4 x i16>, <4 x i16>* %in
   %2 = extractelement <4 x i16> %1, i32 0
   %3 = sitofp i16 %2 to float
   ret float %3

 ; CHECK-NEXT:    bx lr
   %1 = load <8 x i8>, <8 x i8>* %in
   %2 = extractelement <8 x i8> %1, i32 7
   %3 = uitofp i8 %2 to float
   ret float %3
 }
 
 define float @k(<8 x i8>* nocapture %in) {
-; FIXME: The vmov.u + sxt can convert to a vmov.s
 ; CHECK-LABEL: k:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr d16, [r0]
-; CHECK-NEXT:    vmov.u8 r0, d16[7]
-; CHECK-NEXT:    sxtb r0, r0
+; CHECK-NEXT:    vmov.s8 r0, d16[7]
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    bx lr
   %1 = load <8 x i8>, <8 x i8>* %in
   %2 = extractelement <8 x i8> %1, i32 7
   %3 = sitofp i8 %2 to float
   ret float %3

llvm/test/CodeGen/Thumb2/mve-div-expand.ll

 entry:
   %out = udiv <8 x i16> %in1, %in2
   ret <8 x i16> %out
 }
 
 define arm_aapcs_vfpcc <8 x i16> @sdiv_i16(<8 x i16> %in1, <8 x i16> %in2) {
 ; CHECK-LABEL: sdiv_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r6, lr}
-; CHECK-NEXT:    push {r4, r5, r6, lr}
-; CHECK-NEXT:    vmov.u16 r0, q1[3]
-; CHECK-NEXT:    vmov.u16 r1, q0[3]
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    vmov.u16 r2, q0[2]
-; CHECK-NEXT:    sdiv r12, r1, r0
-; CHECK-NEXT:    vmov.u16 r1, q1[2]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    vmov.u16 r4, q1[6]
-; CHECK-NEXT:    sdiv r3, r2, r1
-; CHECK-NEXT:    vmov.u16 r1, q1[1]
-; CHECK-NEXT:    vmov.u16 r2, q0[1]
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    vmov.u16 r5, q0[6]
-; CHECK-NEXT:    sdiv r0, r2, r1
-; CHECK-NEXT:    vmov.u16 r1, q1[0]
-; CHECK-NEXT:    vmov.u16 r2, q0[0]
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r0, q1[0]
+; CHECK-NEXT:    vmov.s16 r1, q0[0]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q1[1]
+; CHECK-NEXT:    vmov.s16 r2, q0[1]
+; CHECK-NEXT:    vmov.16 q2[0], r0
 ; CHECK-NEXT:    sdiv r1, r2, r1
-; CHECK-NEXT:    vmov.u16 r2, q1[7]
-; CHECK-NEXT:    vmov.16 q2[0], r1
-; CHECK-NEXT:    sxth.w lr, r2
-; CHECK-NEXT:    vmov.16 q2[1], r0
-; CHECK-NEXT:    vmov.u16 r2, q0[7]
-; CHECK-NEXT:    vmov.16 q2[2], r3
-; CHECK-NEXT:    vmov.u16 r3, q1[4]
-; CHECK-NEXT:    sxth r6, r2
-; CHECK-NEXT:    vmov.u16 r2, q0[4]
-; CHECK-NEXT:    vmov.u16 r1, q1[5]
-; CHECK-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-NEXT:    sxth r3, r3
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    vmov.16 q2[3], r12
-; CHECK-NEXT:    sdiv r2, r2, r3
-; CHECK-NEXT:    sxth r5, r5
-; CHECK-NEXT:    vmov.16 q2[4], r2
-; CHECK-NEXT:    sdiv r0, r0, r1
+; CHECK-NEXT:    vmov.s16 r0, q1[2]
+; CHECK-NEXT:    vmov.16 q2[1], r1
+; CHECK-NEXT:    vmov.s16 r1, q0[2]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q0[3]
+; CHECK-NEXT:    vmov.16 q2[2], r0
+; CHECK-NEXT:    vmov.s16 r0, q1[3]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q0[4]
+; CHECK-NEXT:    vmov.16 q2[3], r0
+; CHECK-NEXT:    vmov.s16 r0, q1[4]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q0[5]
+; CHECK-NEXT:    vmov.16 q2[4], r0
+; CHECK-NEXT:    vmov.s16 r0, q1[5]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q0[6]
 ; CHECK-NEXT:    vmov.16 q2[5], r0
-; CHECK-NEXT:    sdiv r0, r5, r4
+; CHECK-NEXT:    vmov.s16 r0, q1[6]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s16 r1, q0[7]
 ; CHECK-NEXT:    vmov.16 q2[6], r0
-; CHECK-NEXT:    sdiv r0, r6, lr
+; CHECK-NEXT:    vmov.s16 r0, q1[7]
+; CHECK-NEXT:    sdiv r0, r1, r0
 ; CHECK-NEXT:    vmov.16 q2[7], r0
 ; CHECK-NEXT:    vmov q0, q2
-; CHECK-NEXT:    pop {r4, r5, r6, pc}
+; CHECK-NEXT:    bx lr
 entry:
   %out = sdiv <8 x i16> %in1, %in2
   ret <8 x i16> %out
 }
 
 define arm_aapcs_vfpcc <8 x i16> @urem_i16(<8 x i16> %in1, <8 x i16> %in2) {
 ; CHECK-LABEL: urem_i16:
 ; CHECK:       @ %bb.0: @ %entry

 entry:
   %out = urem <8 x i16> %in1, %in2
   ret <8 x i16> %out
 }
 
 define arm_aapcs_vfpcc <8 x i16> @srem_i16(<8 x i16> %in1, <8 x i16> %in2) {
 ; CHECK-LABEL: srem_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT:    vmov.u16 r5, q1[6]
-; CHECK-NEXT:    vmov.u16 r6, q0[6]
-; CHECK-NEXT:    sxth r5, r5
-; CHECK-NEXT:    sxth r6, r6
-; CHECK-NEXT:    vmov.u16 r0, q1[0]
-; CHECK-NEXT:    sdiv r7, r6, r5
-; CHECK-NEXT:    vmov.u16 r2, q1[7]
-; CHECK-NEXT:    sxth.w r8, r0
-; CHECK-NEXT:    vmov.u16 r0, q1[3]
-; CHECK-NEXT:    mls r12, r7, r5, r6
-; CHECK-NEXT:    vmov.u16 r7, q0[7]
-; CHECK-NEXT:    sxth r3, r0
-; CHECK-NEXT:    vmov.u16 r0, q1[2]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r7, r7
-; CHECK-NEXT:    sxth r4, r0
-; CHECK-NEXT:    vmov.u16 r0, q1[5]
-; CHECK-NEXT:    sdiv r6, r7, r2
-; CHECK-NEXT:    mls lr, r6, r2, r7
-; CHECK-NEXT:    vmov.u16 r2, q0[4]
-; CHECK-NEXT:    sxth r1, r0
-; CHECK-NEXT:    vmov.u16 r0, q1[4]
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sdiv r5, r2, r0
-; CHECK-NEXT:    vmov.u16 r6, q0[1]
-; CHECK-NEXT:    mls r0, r5, r0, r2
-; CHECK-NEXT:    vmov.u16 r2, q0[5]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sdiv r5, r2, r1
-; CHECK-NEXT:    sxth r6, r6
-; CHECK-NEXT:    mls r1, r5, r1, r2
-; CHECK-NEXT:    vmov.u16 r2, q0[2]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sdiv r5, r2, r4
-; CHECK-NEXT:    mls r2, r5, r4, r2
-; CHECK-NEXT:    vmov.u16 r4, q0[3]
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
+; CHECK-NEXT:    vmov.s16 r0, q1[6]
+; CHECK-NEXT:    vmov.s16 r1, q0[6]
+; CHECK-NEXT:    sdiv r2, r1, r0
+; CHECK-NEXT:    mls r12, r2, r0, r1
+; CHECK-NEXT:    vmov.s16 r1, q1[7]
+; CHECK-NEXT:    vmov.s16 r2, q0[7]
+; CHECK-NEXT:    sdiv r3, r2, r1
+; CHECK-NEXT:    mls lr, r3, r1, r2
+; CHECK-NEXT:    vmov.s16 r2, q1[4]
+; CHECK-NEXT:    vmov.s16 r3, q0[4]
+; CHECK-NEXT:    sdiv r0, r3, r2
+; CHECK-NEXT:    mls r2, r0, r2, r3
+; CHECK-NEXT:    vmov.s16 r0, q1[5]
+; CHECK-NEXT:    vmov.s16 r3, q0[5]
+; CHECK-NEXT:    sdiv r1, r3, r0
+; CHECK-NEXT:    mls r0, r1, r0, r3
+; CHECK-NEXT:    vmov.s16 r1, q1[2]
+; CHECK-NEXT:    vmov.s16 r3, q0[2]
+; CHECK-NEXT:    sdiv r4, r3, r1
+; CHECK-NEXT:    mls r1, r4, r1, r3
+; CHECK-NEXT:    vmov.s16 r3, q1[3]
+; CHECK-NEXT:    vmov.s16 r4, q0[3]
 ; CHECK-NEXT:    sdiv r5, r4, r3
 ; CHECK-NEXT:    mls r3, r5, r3, r4
-; CHECK-NEXT:    vmov.u16 r4, q0[0]
-; CHECK-NEXT:    sxth r4, r4
-; CHECK-NEXT:    sdiv r5, r4, r8
-; CHECK-NEXT:    mls r4, r5, r8, r4
-; CHECK-NEXT:    vmov.u16 r5, q1[1]
-; CHECK-NEXT:    sxth r5, r5
+; CHECK-NEXT:    vmov.s16 r4, q1[0]
+; CHECK-NEXT:    vmov.s16 r5, q0[0]
+; CHECK-NEXT:    sdiv r6, r5, r4
+; CHECK-NEXT:    mls r4, r6, r4, r5
+; CHECK-NEXT:    vmov.s16 r6, q0[1]
+; CHECK-NEXT:    vmov.s16 r5, q1[1]
 ; CHECK-NEXT:    sdiv r7, r6, r5
 ; CHECK-NEXT:    vmov.16 q0[0], r4
 ; CHECK-NEXT:    mls r5, r7, r5, r6
 ; CHECK-NEXT:    vmov.16 q0[1], r5
-; CHECK-NEXT:    vmov.16 q0[2], r2
+; CHECK-NEXT:    vmov.16 q0[2], r1
 ; CHECK-NEXT:    vmov.16 q0[3], r3
-; CHECK-NEXT:    vmov.16 q0[4], r0
-; CHECK-NEXT:    vmov.16 q0[5], r1
+; CHECK-NEXT:    vmov.16 q0[4], r2
+; CHECK-NEXT:    vmov.16 q0[5], r0
 ; CHECK-NEXT:    vmov.16 q0[6], r12
 ; CHECK-NEXT:    vmov.16 q0[7], lr
-; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 entry:
   %out = srem <8 x i16> %in1, %in2
   ret <8 x i16> %out
 }
 
 
 define arm_aapcs_vfpcc <16 x i8> @udiv_i8(<16 x i8> %in1, <16 x i8> %in2) {
 ; CHECK-LABEL: udiv_i8:

 entry:
   %out = udiv <16 x i8> %in1, %in2
   ret <16 x i8> %out
 }
 
 define arm_aapcs_vfpcc <16 x i8> @sdiv_i8(<16 x i8> %in1, <16 x i8> %in2) {
 ; CHECK-LABEL: sdiv_i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
-; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
-; CHECK-NEXT:    vmov.u8 r0, q1[1]
-; CHECK-NEXT:    vmov.u8 r1, q0[1]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    vmov.u8 r2, q0[0]
-; CHECK-NEXT:    sdiv r0, r1, r0
-; CHECK-NEXT:    vmov.u8 r1, q1[0]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    vmov.u8 r4, q1[3]
+; CHECK-NEXT:    vmov.s8 r0, q1[0]
+; CHECK-NEXT:    vmov.s8 r1, q0[0]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q1[1]
+; CHECK-NEXT:    vmov.s8 r2, q0[1]
+; CHECK-NEXT:    vmov.8 q2[0], r0
 ; CHECK-NEXT:    sdiv r1, r2, r1
-; CHECK-NEXT:    vmov.u8 r5, q0[3]
-; CHECK-NEXT:    vmov.8 q2[0], r1
-; CHECK-NEXT:    vmov.u8 r1, q1[2]
-; CHECK-NEXT:    vmov.8 q2[1], r0
-; CHECK-NEXT:    vmov.u8 r0, q0[2]
-; CHECK-NEXT:    vmov.u8 r2, q1[11]
-; CHECK-NEXT:    vmov.u8 r3, q0[11]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sdiv r0, r0, r1
-; CHECK-NEXT:    sxtb.w r12, r2
-; CHECK-NEXT:    sxtb.w lr, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[4]
-; CHECK-NEXT:    vmov.u8 r3, q0[4]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r0, q1[2]
+; CHECK-NEXT:    vmov.8 q2[1], r1
+; CHECK-NEXT:    vmov.s8 r1, q0[2]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[3]
 ; CHECK-NEXT:    vmov.8 q2[2], r0
-; CHECK-NEXT:    sdiv r0, r5, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q1[3]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[4]
 ; CHECK-NEXT:    vmov.8 q2[3], r0
-; CHECK-NEXT:    sdiv r0, r3, r2
-; CHECK-NEXT:    vmov.u8 r1, q0[10]
+; CHECK-NEXT:    vmov.s8 r0, q1[4]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[5]
 ; CHECK-NEXT:    vmov.8 q2[4], r0
-; CHECK-NEXT:    vmov.u8 r0, q1[10]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sdiv r12, lr, r12
-; CHECK-NEXT:    sdiv lr, r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[9]
-; CHECK-NEXT:    vmov.u8 r1, q0[9]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sdiv r2, r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[8]
-; CHECK-NEXT:    vmov.u8 r1, q0[8]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    vmov.u8 r3, q0[7]
-; CHECK-NEXT:    sdiv r1, r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[7]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sdiv r4, r3, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[6]
-; CHECK-NEXT:    vmov.u8 r3, q0[6]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    vmov.u8 r6, q0[12]
-; CHECK-NEXT:    sdiv r5, r3, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[5]
-; CHECK-NEXT:    vmov.u8 r3, q0[5]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sdiv r0, r3, r0
-; CHECK-NEXT:    vmov.u8 r3, q1[15]
+; CHECK-NEXT:    vmov.s8 r0, q1[5]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[6]
 ; CHECK-NEXT:    vmov.8 q2[5], r0
-; CHECK-NEXT:    sxtb r7, r3
-; CHECK-NEXT:    vmov.8 q2[6], r5
-; CHECK-NEXT:    vmov.u8 r3, q1[12]
-; CHECK-NEXT:    vmov.8 q2[7], r4
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    vmov.8 q2[8], r1
-; CHECK-NEXT:    vmov.u8 r1, q1[13]
-; CHECK-NEXT:    vmov.8 q2[9], r2
-; CHECK-NEXT:    vmov.u8 r2, q0[13]
-; CHECK-NEXT:    vmov.8 q2[10], lr
-; CHECK-NEXT:    vmov.u8 r5, q1[14]
-; CHECK-NEXT:    vmov.u8 r4, q0[14]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    vmov.8 q2[11], r12
-; CHECK-NEXT:    sdiv r3, r6, r3
-; CHECK-NEXT:    vmov.u8 r0, q0[15]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov.8 q2[12], r3
-; CHECK-NEXT:    sdiv r1, r2, r1
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    vmov.8 q2[13], r1
-; CHECK-NEXT:    sdiv r1, r4, r5
-; CHECK-NEXT:    sdiv r0, r0, r7
-; CHECK-NEXT:    vmov.8 q2[14], r1
+; CHECK-NEXT:    vmov.s8 r0, q1[6]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[7]
+; CHECK-NEXT:    vmov.8 q2[6], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[7]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[8]
+; CHECK-NEXT:    vmov.8 q2[7], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[8]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[9]
+; CHECK-NEXT:    vmov.8 q2[8], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[9]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[10]
+; CHECK-NEXT:    vmov.8 q2[9], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[10]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[11]
+; CHECK-NEXT:    vmov.8 q2[10], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[11]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[12]
+; CHECK-NEXT:    vmov.8 q2[11], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[12]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[13]
+; CHECK-NEXT:    vmov.8 q2[12], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[13]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[14]
+; CHECK-NEXT:    vmov.8 q2[13], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[14]
+; CHECK-NEXT:    sdiv r0, r1, r0
+; CHECK-NEXT:    vmov.s8 r1, q0[15]
+; CHECK-NEXT:    vmov.8 q2[14], r0
+; CHECK-NEXT:    vmov.s8 r0, q1[15]
+; CHECK-NEXT:    sdiv r0, r1, r0
 ; CHECK-NEXT:    vmov.8 q2[15], r0
 ; CHECK-NEXT:    vmov q0, q2
-; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
+; CHECK-NEXT:    bx lr
 entry:
   %out = sdiv <16 x i8> %in1, %in2
   ret <16 x i8> %out
 }
 
 define arm_aapcs_vfpcc <16 x i8> @urem_i8(<16 x i8> %in1, <16 x i8> %in2) {
 ; CHECK-LABEL: urem_i8:
 ; CHECK:       @ %bb.0: @ %entry

 entry:
   %out = urem <16 x i8> %in1, %in2
   ret <16 x i8> %out
 }
 
 define arm_aapcs_vfpcc <16 x i8> @srem_i8(<16 x i8> %in1, <16 x i8> %in2) {
 ; CHECK-LABEL: srem_i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT:    vmov.u8 r5, q1[14]
-; CHECK-NEXT:    vmov.u8 r6, q0[14]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sdiv r7, r6, r5
-; CHECK-NEXT:    vmov.u8 r4, q1[15]
-; CHECK-NEXT:    mls r12, r7, r5, r6
-; CHECK-NEXT:    vmov.u8 r7, q0[15]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov.u8 r2, q1[13]
-; CHECK-NEXT:    sxtb r7, r7
-; CHECK-NEXT:    sxtb r3, r2
-; CHECK-NEXT:    sdiv r6, r7, r4
-; CHECK-NEXT:    vmov.u8 r2, q1[12]
-; CHECK-NEXT:    mls lr, r6, r4, r7
-; CHECK-NEXT:    vmov.u8 r4, q0[12]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    vmov.u8 r0, q1[8]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb.w r8, r0
-; CHECK-NEXT:    sdiv r5, r4, r2
-; CHECK-NEXT:    vmov.u8 r0, q1[11]
-; CHECK-NEXT:    mls r9, r5, r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[13]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov.u8 r6, q0[0]
-; CHECK-NEXT:    sdiv r5, r4, r3
-; CHECK-NEXT:    sxtb r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[10]
-; CHECK-NEXT:    mls r3, r5, r3, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[10]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sdiv r5, r4, r0
-; CHECK-NEXT:    mls r0, r5, r0, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[11]
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT:    vmov.s8 r0, q1[14]
+; CHECK-NEXT:    vmov.s8 r1, q0[14]
+; CHECK-NEXT:    sdiv r2, r1, r0
+; CHECK-NEXT:    mls r12, r2, r0, r1
+; CHECK-NEXT:    vmov.s8 r0, q1[15]
+; CHECK-NEXT:    vmov.s8 r1, q0[15]
+; CHECK-NEXT:    sdiv r2, r1, r0
+; CHECK-NEXT:    mls lr, r2, r0, r1
+; CHECK-NEXT:    vmov.s8 r0, q1[12]
+; CHECK-NEXT:    vmov.s8 r1, q0[12]
+; CHECK-NEXT:    sdiv r2, r1, r0
+; CHECK-NEXT:    mls r8, r2, r0, r1
+; CHECK-NEXT:    vmov.s8 r0, q1[13]
+; CHECK-NEXT:    vmov.s8 r1, q0[13]
+; CHECK-NEXT:    sdiv r3, r1, r0
+; CHECK-NEXT:    mls r3, r3, r0, r1
+; CHECK-NEXT:    vmov.s8 r0, q1[10]
+; CHECK-NEXT:    vmov.s8 r1, q0[10]
+; CHECK-NEXT:    sdiv r4, r1, r0
+; CHECK-NEXT:    mls r0, r4, r0, r1
+; CHECK-NEXT:    vmov.s8 r1, q1[11]
+; CHECK-NEXT:    vmov.s8 r4, q0[11]
 ; CHECK-NEXT:    sdiv r5, r4, r1
 ; CHECK-NEXT:    mls r1, r5, r1, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[8]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sdiv r5, r4, r8
-; CHECK-NEXT:    mls r4, r5, r8, r4
-; CHECK-NEXT:    vmov.u8 r5, q1[0]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r4, q1[8]
+; CHECK-NEXT:    vmov.s8 r5, q0[8]
+; CHECK-NEXT:    sdiv r6, r5, r4
+; CHECK-NEXT:    mls r4, r6, r4, r5
+; CHECK-NEXT:    vmov.s8 r5, q1[0]
+; CHECK-NEXT:    vmov.s8 r6, q0[0]
 ; CHECK-NEXT:    sdiv r7, r6, r5
 ; CHECK-NEXT:    mls r5, r7, r5, r6
-; CHECK-NEXT:    vmov.u8 r6, q1[1]
-; CHECK-NEXT:    vmov.u8 r7, q0[1]
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sxtb r7, r7
-; CHECK-NEXT:    vmov.8 q2[0], r5
+; CHECK-NEXT:    vmov.s8 r6, q1[1]
+; CHECK-NEXT:    vmov.s8 r7, q0[1]
 ; CHECK-NEXT:    sdiv r2, r7, r6
-; CHECK-NEXT:    vmov.u8 r5, q0[2]
+; CHECK-NEXT:    vmov.8 q2[0], r5
 ; CHECK-NEXT:    mls r2, r2, r6, r7
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[2]
 ; CHECK-NEXT:    vmov.8 q2[1], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[2]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[2]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[3]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[3]
 ; CHECK-NEXT:    vmov.8 q2[2], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[3]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[3]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[4]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[4]
 ; CHECK-NEXT:    vmov.8 q2[3], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[4]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[4]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[5]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[5]
 ; CHECK-NEXT:    vmov.8 q2[4], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[5]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[5]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[6]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[6]
 ; CHECK-NEXT:    vmov.8 q2[5], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[6]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[6]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[7]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[7]
 ; CHECK-NEXT:    vmov.8 q2[6], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[7]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[7]
 ; CHECK-NEXT:    sdiv r6, r5, r2
 ; CHECK-NEXT:    mls r2, r6, r2, r5
-; CHECK-NEXT:    vmov.u8 r5, q0[9]
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r5, q0[9]
 ; CHECK-NEXT:    vmov.8 q2[7], r2
-; CHECK-NEXT:    vmov.u8 r2, q1[9]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    vmov.8 q2[8], r4
+; CHECK-NEXT:    vmov.s8 r2, q1[9]
 ; CHECK-NEXT:    sdiv r6, r5, r2
+; CHECK-NEXT:    vmov.8 q2[8], r4
 ; CHECK-NEXT:    mls r2, r6, r2, r5
 ; CHECK-NEXT:    vmov.8 q2[9], r2
 ; CHECK-NEXT:    vmov.8 q2[10], r0
 ; CHECK-NEXT:    vmov.8 q2[11], r1
-; CHECK-NEXT:    vmov.8 q2[12], r9
+; CHECK-NEXT:    vmov.8 q2[12], r8
 ; CHECK-NEXT:    vmov.8 q2[13], r3
 ; CHECK-NEXT:    vmov.8 q2[14], r12
 ; CHECK-NEXT:    vmov.8 q2[15], lr
 ; CHECK-NEXT:    vmov q0, q2
-; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, pc}
+; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, pc}
 entry:
   %out = srem <16 x i8> %in1, %in2
   ret <16 x i8> %out
 }
 
 define arm_aapcs_vfpcc <2 x i64> @udiv_i64(<2 x i64> %in1, <2 x i64> %in2) {
 ; CHECK-LABEL: udiv_i64:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/Thumb2/mve-vcvt.ll

 entry:
   %out = fptoui <4 x float> %src to <4 x i32>
   ret <4 x i32> %out
 }
 
 define arm_aapcs_vfpcc <8 x half> @foo_half_int16(<8 x i16> %src) {
 ; CHECK-MVE-LABEL: foo_half_int16:
 ; CHECK-MVE:       @ %bb.0: @ %entry
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[0]
-; CHECK-MVE-NEXT:    vmov.u16 r1, q0[1]
-; CHECK-MVE-NEXT:    sxth r0, r0
-; CHECK-MVE-NEXT:    sxth r1, r1
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[0]
+; CHECK-MVE-NEXT:    vmov.s16 r1, q0[1]
 ; CHECK-MVE-NEXT:    vmov s4, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s4, s4
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov s4, r1
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s4, s4
 ; CHECK-MVE-NEXT:    vmov r1, s4
 ; CHECK-MVE-NEXT:    vmov.16 q1[0], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[2]
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[2]
 ; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
-; CHECK-MVE-NEXT:    sxth r0, r0
 ; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-MVE-NEXT:    sxth r0, r0
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[3]
 ; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[3], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[4]
-; CHECK-MVE-NEXT:    sxth r0, r0
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[4]
 ; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[4], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-MVE-NEXT:    sxth r0, r0
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[5]
 ; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[5], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[6]
-; CHECK-MVE-NEXT:    sxth r0, r0
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[6]
 ; CHECK-MVE-NEXT:    vmov s8, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.16 q1[6], r0
-; CHECK-MVE-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-MVE-NEXT:    sxth r0, r0
+; CHECK-MVE-NEXT:    vmov.s16 r0, q0[7]
 ; CHECK-MVE-NEXT:    vmov s0, r0
 ; CHECK-MVE-NEXT:    vcvt.f16.s32 s0, s0
 ; CHECK-MVE-NEXT:    vmov r0, s0
 ; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
 ; CHECK-MVE-NEXT:    vmov q0, q1
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: foo_half_int16:

llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll

entry:
   %xx = zext <8 x i16> %x to <8 x i64>
   %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
   ret i64 %z
 }
 
 define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x) {
 ; CHECK-LABEL: add_v8i16_v8i64_sext:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.u16 r0, q0[1]
-; CHECK-NEXT:    vmov.u16 r1, q0[0]
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    sxth r1, r1
+; CHECK-NEXT:    vmov.s16 r0, q0[1]
+; CHECK-NEXT:    vmov.s16 r1, q0[0]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r1, r0
 ; CHECK-NEXT:    asrs r2, r0, #31
 ; CHECK-NEXT:    asrs r1, r1, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r1, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r1, s5
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u16 r3, q0[2]
+; CHECK-NEXT:    vmov.s16 r3, q0[2]
 ; CHECK-NEXT:    adc.w r12, r1, r0, asr #31
-; CHECK-NEXT:    vmov.u16 r1, q0[3]
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r1, q0[3]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u16 r3, q0[4]
+; CHECK-NEXT:    vmov.s16 r3, q0[4]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u16 r1, q0[5]
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r1, q0[5]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
+; CHECK-NEXT:    vmov.s16 r3, q0[7]
 ; CHECK-NEXT:    adc.w r0, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u16 r1, q0[6]
-; CHECK-NEXT:    sxth r1, r1
+; CHECK-NEXT:    vmov.s16 r1, q0[6]
 ; CHECK-NEXT:    adds r2, r2, r1
 ; CHECK-NEXT:    adc.w r1, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u16 r0, q0[7]
-; CHECK-NEXT:    sxth r3, r0
 ; CHECK-NEXT:    adds r0, r2, r3
 ; CHECK-NEXT:    adc.w r1, r1, r3, asr #31
 ; CHECK-NEXT:    bx lr
 entry:
   %xx = sext <8 x i16> %x to <8 x i64>
   %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
   ret i64 %z
 }
entry:
   %xx = zext <16 x i8> %x to <16 x i64>
   %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
   ret i64 %z
 }
 
 define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x) {
 ; CHECK-LABEL: add_v16i8_v16i64_sext:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov.u8 r0, q0[1]
-; CHECK-NEXT:    vmov.u8 r1, q0[0]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r0, q0[1]
+; CHECK-NEXT:    vmov.s8 r1, q0[0]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r1, r0
 ; CHECK-NEXT:    asrs r2, r0, #31
 ; CHECK-NEXT:    asrs r1, r1, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r1, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r1, s5
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[2]
+; CHECK-NEXT:    vmov.s8 r3, q0[2]
 ; CHECK-NEXT:    adc.w r12, r1, r0, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[3]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[3]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[4]
+; CHECK-NEXT:    vmov.s8 r3, q0[4]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[5]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[5]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[6]
+; CHECK-NEXT:    vmov.s8 r3, q0[6]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[7]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[7]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[8]
+; CHECK-NEXT:    vmov.s8 r3, q0[8]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[9]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[9]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[10]
+; CHECK-NEXT:    vmov.s8 r3, q0[10]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[11]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[11]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[12]
+; CHECK-NEXT:    vmov.s8 r3, q0[12]
 ; CHECK-NEXT:    adc.w r12, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[13]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r1, q0[13]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r1
 ; CHECK-NEXT:    asrs r0, r1, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r0
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds r2, r2, r3
+; CHECK-NEXT:    vmov.s8 r3, q0[15]
 ; CHECK-NEXT:    adc.w r0, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r1, q0[14]
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r1, q0[14]
 ; CHECK-NEXT:    adds r2, r2, r1
 ; CHECK-NEXT:    adc.w r1, r0, r1, asr #31
-; CHECK-NEXT:    vmov.u8 r0, q0[15]
-; CHECK-NEXT:    sxtb r3, r0
 ; CHECK-NEXT:    adds r0, r2, r3
 ; CHECK-NEXT:    adc.w r1, r1, r3, asr #31
 ; CHECK-NEXT:    bx lr
 entry:
   %xx = sext <16 x i8> %x to <16 x i64>
   %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)
   ret i64 %z
 }
entry:
   ret i64 %r
 }
 
 define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, i64 %a) {
 ; CHECK-LABEL: add_v8i16_v8i64_acc_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    vmov.u16 r2, q0[1]
-; CHECK-NEXT:    vmov.u16 r3, q0[0]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r2, q0[1]
+; CHECK-NEXT:    vmov.s16 r3, q0[0]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r2
 ; CHECK-NEXT:    asr.w r12, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r12
 ; CHECK-NEXT:    vmov lr, s6
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r12, s5
 ; CHECK-NEXT:    adds.w lr, lr, r3
-; CHECK-NEXT:    vmov.u16 r3, q0[2]
+; CHECK-NEXT:    vmov.s16 r3, q0[2]
 ; CHECK-NEXT:    adc.w r12, r12, r2, asr #31
-; CHECK-NEXT:    vmov.u16 r2, q0[3]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r2, q0[3]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r2
 ; CHECK-NEXT:    asrs r4, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r4
 ; CHECK-NEXT:    vmov r4, s4
 ; CHECK-NEXT:    vmov r3, s5
 ; CHECK-NEXT:    adds.w r4, r4, lr
 ; CHECK-NEXT:    adc.w r12, r12, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adds.w lr, r4, r3
-; CHECK-NEXT:    vmov.u16 r4, q0[5]
+; CHECK-NEXT:    vmov.s16 r4, q0[5]
 ; CHECK-NEXT:    adc.w r12, r12, r2, asr #31
-; CHECK-NEXT:    vmov.u16 r2, q0[4]
-; CHECK-NEXT:    sxth r4, r4
-; CHECK-NEXT:    sxth r2, r2
+; CHECK-NEXT:    vmov.s16 r2, q0[4]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    adc.w r3, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u16 r4, q0[6]
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r4, q0[6]
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    adc.w r3, r3, r4, asr #31
-; CHECK-NEXT:    vmov.u16 r4, q0[7]
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r4, q0[7]
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    adc.w r3, r3, r4, asr #31
 ; CHECK-NEXT:    adds r0, r0, r2
 ; CHECK-NEXT:    adcs r1, r3
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
   %xx = sext <8 x i16> %x to <8 x i64>
   %z = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %xx)
entry:
   ret i64 %r
 }
 
 define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext(<16 x i8> %x, i64 %a) {
 ; CHECK-LABEL: add_v16i8_v16i64_acc_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    vmov.u8 r2, q0[1]
-; CHECK-NEXT:    vmov.u8 r3, q0[0]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q0[1]
+; CHECK-NEXT:    vmov.s8 r3, q0[0]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r2
 ; CHECK-NEXT:    asr.w r12, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r12
 ; CHECK-NEXT:    vmov lr, s6
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r12, s5
 ; CHECK-NEXT:    adds.w lr, lr, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[2]
+; CHECK-NEXT:    vmov.s8 r3, q0[2]
 ; CHECK-NEXT:    adc.w r12, r12, r2, asr #31
-; CHECK-NEXT:    vmov.u8 r2, q0[3]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q0[3]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r3, r2
 ; CHECK-NEXT:    asrs r4, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r3, r4
 ; CHECK-NEXT:    vmov r4, s4
 ; CHECK-NEXT:    vmov r3, s5
 ; CHECK-NEXT:    adds.w r4, r4, lr
 ; CHECK-NEXT:    adc.w r12, r12, r3
 ; CHECK-NEXT:    vmov r3, s6
 ; CHECK-NEXT:    adds.w lr, r4, r3
-; CHECK-NEXT:    vmov.u8 r4, q0[5]
+; CHECK-NEXT:    vmov.s8 r4, q0[5]
 ; CHECK-NEXT:    adc.w r12, r12, r2, asr #31
-; CHECK-NEXT:    vmov.u8 r2, q0[4]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q0[4]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds.w lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q0[6]
+; CHECK-NEXT:    vmov.s8 r2, q0[6]
 ; CHECK-NEXT:    adc.w r12, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[7]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r4, q0[7]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds.w lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q0[8]
+; CHECK-NEXT:    vmov.s8 r2, q0[8]
 ; CHECK-NEXT:    adc.w r12, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[9]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r4, q0[9]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds.w lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q0[10]
+; CHECK-NEXT:    vmov.s8 r2, q0[10]
 ; CHECK-NEXT:    adc.w r12, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[11]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r4, q0[11]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds.w lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q0[12]
+; CHECK-NEXT:    vmov.s8 r2, q0[12]
 ; CHECK-NEXT:    adc.w r12, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[13]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r4, q0[13]
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    asrs r3, r4, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r12, r12, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    adds r2, r2, r3
 ; CHECK-NEXT:    adc.w r3, r12, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[14]
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r4, q0[14]
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    adc.w r3, r3, r4, asr #31
-; CHECK-NEXT:    vmov.u8 r4, q0[15]
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r4, q0[15]
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    adc.w r3, r3, r4, asr #31
 ; CHECK-NEXT:    adds r0, r0, r2
 ; CHECK-NEXT:    adcs r1, r3
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
   %xx = sext <16 x i8> %x to <16 x i64>
   %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %xx)

llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r0, p0
 ; CHECK-NEXT:    and r2, r0, #1
 ; CHECK-NEXT:    ubfx r1, r0, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r1, r1, #0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r1
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r1
-; CHECK-NEXT:    vmov.u16 r1, q0[1]
-; CHECK-NEXT:    vmov.u16 r2, q0[0]
-; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    sxth r2, r2
+; CHECK-NEXT:    vmov.s16 r1, q0[1]
+; CHECK-NEXT:    vmov.s16 r2, q0[0]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r2, r1
 ; CHECK-NEXT:    asrs r1, r1, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r2, r1
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r3, s10
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r12, s11
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    adds r1, r1, r3
 ; CHECK-NEXT:    ubfx r3, r0, #12, #1
 ; CHECK-NEXT:    ubfx r0, r0, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r0, r0, #0
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r3
 ; CHECK-NEXT:    vmov q2[3], q2[1], r0, r3
-; CHECK-NEXT:    vmov.u16 r0, q0[3]
-; CHECK-NEXT:    vmov.u16 r3, q0[2]
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r0, q0[3]
+; CHECK-NEXT:    vmov.s16 r3, q0[2]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r3, r0
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    adds r1, r1, r3

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r0, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r0, r0, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q1[2], q1[0], r0, r3
 ; CHECK-NEXT:    vmov q1[3], q1[1], r0, r3
-; CHECK-NEXT:    vmov.u16 r0, q0[5]
-; CHECK-NEXT:    vmov.u16 r3, q0[4]
-; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r0, q0[5]
+; CHECK-NEXT:    vmov.s16 r3, q0[4]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r0
 ; CHECK-NEXT:    vand q1, q2, q1
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds.w r3, r3, r12
 ; CHECK-NEXT:    adc.w r12, r1, r0
 ; CHECK-NEXT:    vmov r0, s6
 ; CHECK-NEXT:    vmov r1, s7
 ; CHECK-NEXT:    adds r0, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
 ; CHECK-NEXT:    adc.w r1, r1, r12
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r3
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
-; CHECK-NEXT:    vmov.u16 r2, q0[7]
-; CHECK-NEXT:    vmov.u16 r3, q0[6]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r3, r3
+; CHECK-NEXT:    vmov.s16 r2, q0[7]
+; CHECK-NEXT:    vmov.s16 r3, q0[6]
 ; CHECK-NEXT:    vmov q0[2], q0[0], r3, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q0[3], q0[1], r3, r2
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    vmov r3, s0
 ; CHECK-NEXT:    vmov r2, s1
 ; CHECK-NEXT:    adds r0, r0, r3

 ; CHECK-NEXT:    vcmp.i32 ne, q5, zr
 ; CHECK-NEXT:    vmrs r0, p0
 ; CHECK-NEXT:    and r2, r0, #1
 ; CHECK-NEXT:    ubfx r1, r0, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r1, r1, #0
 ; CHECK-NEXT:    vmov q5[2], q5[0], r2, r1
 ; CHECK-NEXT:    vmov q5[3], q5[1], r2, r1
-; CHECK-NEXT:    vmov.u8 r1, q0[1]
-; CHECK-NEXT:    vmov.u8 r2, q0[0]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r1, q0[1]
+; CHECK-NEXT:    vmov.s8 r2, q0[0]
 ; CHECK-NEXT:    vmov q6[2], q6[0], r2, r1
 ; CHECK-NEXT:    asrs r1, r1, #31
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    vmov q6[3], q6[1], r2, r1
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r3, s22
 ; CHECK-NEXT:    vmov r1, s20
 ; CHECK-NEXT:    vmov r12, s23
 ; CHECK-NEXT:    vmov r2, s21
 ; CHECK-NEXT:    adds r1, r1, r3
 ; CHECK-NEXT:    ubfx r3, r0, #12, #1
 ; CHECK-NEXT:    ubfx r0, r0, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r0, r0, #0
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    vmov q5[2], q5[0], r0, r3
 ; CHECK-NEXT:    vmov q5[3], q5[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q0[3]
-; CHECK-NEXT:    vmov.u8 r3, q0[2]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q0[3]
+; CHECK-NEXT:    vmov.s8 r3, q0[2]
 ; CHECK-NEXT:    vmov q6[2], q6[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q6[3], q6[1], r3, r0
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r3, s20
 ; CHECK-NEXT:    vmov r0, s21
 ; CHECK-NEXT:    adds r1, r1, r3

 ; CHECK-NEXT:    vcmp.i32 ne, q5, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r0, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r0, r0, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q4[2], q4[0], r0, r3
 ; CHECK-NEXT:    vmov q4[3], q4[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q0[5]
-; CHECK-NEXT:    vmov.u8 r3, q0[4]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q0[5]
+; CHECK-NEXT:    vmov.s8 r3, q0[4]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q5[3], q5[1], r3, r0
 ; CHECK-NEXT:    vand q4, q5, q4
 ; CHECK-NEXT:    vmov r3, s16
 ; CHECK-NEXT:    vmov r0, s17
 ; CHECK-NEXT:    adds.w r3, r3, r12
 ; CHECK-NEXT:    adc.w r12, r1, r0
 ; CHECK-NEXT:    vmov r0, s18
 ; CHECK-NEXT:    vmov r1, s19
 ; CHECK-NEXT:    adds r0, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
 ; CHECK-NEXT:    adc.w r1, r1, r12
 ; CHECK-NEXT:    vmov q4[2], q4[0], r2, r3
 ; CHECK-NEXT:    vmov q4[3], q4[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q0[7]
-; CHECK-NEXT:    vmov.u8 r3, q0[6]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q0[7]
+; CHECK-NEXT:    vmov.s8 r3, q0[6]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r3, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q5[3], q5[1], r3, r2
 ; CHECK-NEXT:    vand q4, q5, q4
 ; CHECK-NEXT:    vmov r3, s16
 ; CHECK-NEXT:    vmov r2, s17
 ; CHECK-NEXT:    adds r0, r0, r3

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r0, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r0, r0, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r3
 ; CHECK-NEXT:    vmov q2[3], q2[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q0[9]
-; CHECK-NEXT:    vmov.u8 r3, q0[8]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q0[9]
+; CHECK-NEXT:    vmov.s8 r3, q0[8]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r3, r0
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    adds.w r3, r3, r12
 ; CHECK-NEXT:    adc.w r12, r1, r0
 ; CHECK-NEXT:    vmov r0, s10
 ; CHECK-NEXT:    vmov r1, s11
 ; CHECK-NEXT:    adds r0, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
 ; CHECK-NEXT:    adc.w r1, r1, r12
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r3
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q0[11]
-; CHECK-NEXT:    vmov.u8 r3, q0[10]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q0[11]
+; CHECK-NEXT:    vmov.s8 r3, q0[10]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r3, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r3, r2
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    adds r0, r0, r3

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r0, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r0, r0, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q1[2], q1[0], r0, r3
 ; CHECK-NEXT:    vmov q1[3], q1[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q0[13]
-; CHECK-NEXT:    vmov.u8 r3, q0[12]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q0[13]
+; CHECK-NEXT:    vmov.s8 r3, q0[12]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r3, r0
 ; CHECK-NEXT:    asrs r0, r0, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r0
 ; CHECK-NEXT:    vand q1, q2, q1
 ; CHECK-NEXT:    vmov r3, s4
 ; CHECK-NEXT:    vmov r0, s5
 ; CHECK-NEXT:    adds.w r3, r3, r12
 ; CHECK-NEXT:    adc.w r12, r1, r0
 ; CHECK-NEXT:    vmov r0, s6
 ; CHECK-NEXT:    vmov r1, s7
 ; CHECK-NEXT:    adds r0, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
 ; CHECK-NEXT:    adc.w r1, r1, r12
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r3
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q0[15]
-; CHECK-NEXT:    vmov.u8 r3, q0[14]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q0[15]
+; CHECK-NEXT:    vmov.s8 r3, q0[14]
 ; CHECK-NEXT:    vmov q0[2], q0[0], r3, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r3, r3, #31
 ; CHECK-NEXT:    vmov q0[3], q0[1], r3, r2
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    vmov r3, s0
 ; CHECK-NEXT:    vmov r2, s1
 ; CHECK-NEXT:    adds r0, r0, r3

 ; CHECK-NEXT:    vcmp.i16 eq, q1, zr
 ; CHECK-NEXT:    vpsel q1, q3, q2
 ; CHECK-NEXT:    vmov.u16 r2, q1[2]
 ; CHECK-NEXT:    vmov.u16 r3, q1[0]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q1[3]
 ; CHECK-NEXT:    vmov.u16 r3, q1[1]
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r2
+; CHECK-NEXT:    vmov.s16 r2, q0[0]
 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
-; CHECK-NEXT:    vmrs r12, p0
-; CHECK-NEXT:    and r2, r12, #1
-; CHECK-NEXT:    ubfx r3, r12, #4, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    vmrs lr, p0
+; CHECK-NEXT:    ubfx r3, lr, #4, #1
+; CHECK-NEXT:    rsb.w r12, r3, #0
+; CHECK-NEXT:    and r3, lr, #1
 ; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    vmov q2[2], q2[0], r2, r3
-; CHECK-NEXT:    vmov q2[3], q2[1], r2, r3
-; CHECK-NEXT:    vmov.u16 r2, q0[1]
-; CHECK-NEXT:    vmov.u16 r3, q0[0]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r3, r3
-; CHECK-NEXT:    vmov q3[2], q3[0], r3, r2
-; CHECK-NEXT:    asrs r2, r2, #31
+; CHECK-NEXT:    vmov q2[2], q2[0], r3, r12
+; CHECK-NEXT:    vmov q2[3], q2[1], r3, r12
+; CHECK-NEXT:    vmov.s16 r3, q0[1]
+; CHECK-NEXT:    vmov q3[2], q3[0], r2, r3
 ; CHECK-NEXT:    asrs r3, r3, #31
-; CHECK-NEXT:    vmov q3[3], q3[1], r3, r2
+; CHECK-NEXT:    asrs r2, r2, #31
+; CHECK-NEXT:    vmov q3[3], q3[1], r2, r3
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    vmov r4, s8
-; CHECK-NEXT:    vmov lr, s11
+; CHECK-NEXT:    vmov r12, s11
 ; CHECK-NEXT:    vmov r3, s9
 ; CHECK-NEXT:    adds r5, r4, r2
-; CHECK-NEXT:    ubfx r4, r12, #12, #1
-; CHECK-NEXT:    ubfx r2, r12, #8, #1
+; CHECK-NEXT:    ubfx r4, lr, #12, #1
+; CHECK-NEXT:    ubfx r2, lr, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
-; CHECK-NEXT:    adc.w r3, r3, lr
+; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r4
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r4
-; CHECK-NEXT:    vmov.u16 r2, q0[3]
-; CHECK-NEXT:    vmov.u16 r4, q0[2]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r2, q0[3]
+; CHECK-NEXT:    vmov.s16 r4, q0[2]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r4, r2
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r4, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    adds r5, r5, r4

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r5, p0
 ; CHECK-NEXT:    and r2, r5, #1
 ; CHECK-NEXT:    ubfx r4, r5, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r4
-; CHECK-NEXT:    vmov.u16 r2, q0[5]
-; CHECK-NEXT:    vmov.u16 r4, q0[4]
-; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r2, q0[5]
+; CHECK-NEXT:    vmov.s16 r4, q0[4]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q2[3], q2[1], r4, r2
 ; CHECK-NEXT:    vand q1, q2, q1
 ; CHECK-NEXT:    vmov r4, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r4, r4, r12
 ; CHECK-NEXT:    adc.w r12, r3, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    vmov r3, s7
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    ubfx r4, r5, #12, #1
 ; CHECK-NEXT:    ubfx r5, r5, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r5, r5, #0
 ; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q1[2], q1[0], r5, r4
 ; CHECK-NEXT:    vmov q1[3], q1[1], r5, r4
-; CHECK-NEXT:    vmov.u16 r5, q0[7]
-; CHECK-NEXT:    vmov.u16 r4, q0[6]
-; CHECK-NEXT:    sxth r5, r5
-; CHECK-NEXT:    sxth r4, r4
+; CHECK-NEXT:    vmov.s16 r5, q0[7]
+; CHECK-NEXT:    vmov.s16 r4, q0[6]
 ; CHECK-NEXT:    vmov q0[2], q0[0], r4, r5
 ; CHECK-NEXT:    asrs r5, r5, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q0[3], q0[1], r4, r5
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    vmov r4, s0
 ; CHECK-NEXT:    vmov r5, s1
 ; CHECK-NEXT:    adds r2, r2, r4

 ; CHECK-NEXT:    vcmp.i16 ne, q4, zr
 ; CHECK-NEXT:    vpsel q4, q2, q1
 ; CHECK-NEXT:    vmov.u16 r2, q4[2]
 ; CHECK-NEXT:    vmov.u16 r3, q4[0]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q4[3]
 ; CHECK-NEXT:    vmov.u16 r3, q4[1]
 ; CHECK-NEXT:    vmov q5[3], q5[1], r3, r2
+; CHECK-NEXT:    vmov.s8 r2, q0[0]
 ; CHECK-NEXT:    vcmp.i32 ne, q5, zr
-; CHECK-NEXT:    vmrs r12, p0
-; CHECK-NEXT:    and r2, r12, #1
-; CHECK-NEXT:    ubfx r3, r12, #4, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    vmrs lr, p0
+; CHECK-NEXT:    ubfx r3, lr, #4, #1
+; CHECK-NEXT:    rsb.w r12, r3, #0
+; CHECK-NEXT:    and r3, lr, #1
 ; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    vmov q5[2], q5[0], r2, r3
-; CHECK-NEXT:    vmov q5[3], q5[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q0[1]
-; CHECK-NEXT:    vmov.u8 r3, q0[0]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    vmov q6[2], q6[0], r3, r2
-; CHECK-NEXT:    asrs r2, r2, #31
+; CHECK-NEXT:    vmov q5[2], q5[0], r3, r12
+; CHECK-NEXT:    vmov q5[3], q5[1], r3, r12
+; CHECK-NEXT:    vmov.s8 r3, q0[1]
+; CHECK-NEXT:    vmov q6[2], q6[0], r2, r3
 ; CHECK-NEXT:    asrs r3, r3, #31
-; CHECK-NEXT:    vmov q6[3], q6[1], r3, r2
+; CHECK-NEXT:    asrs r2, r2, #31
+; CHECK-NEXT:    vmov q6[3], q6[1], r2, r3
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r2, s22
 ; CHECK-NEXT:    vmov r4, s20
-; CHECK-NEXT:    vmov lr, s23
+; CHECK-NEXT:    vmov r12, s23
 ; CHECK-NEXT:    vmov r3, s21
 ; CHECK-NEXT:    adds r5, r4, r2
-; CHECK-NEXT:    ubfx r4, r12, #12, #1
-; CHECK-NEXT:    ubfx r2, r12, #8, #1
+; CHECK-NEXT:    ubfx r4, lr, #12, #1
+; CHECK-NEXT:    ubfx r2, lr, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
-; CHECK-NEXT:    adc.w r3, r3, lr
+; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q5[2], q5[0], r2, r4
 ; CHECK-NEXT:    vmov q5[3], q5[1], r2, r4
-; CHECK-NEXT:    vmov.u8 r2, q0[3]
-; CHECK-NEXT:    vmov.u8 r4, q0[2]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r2, q0[3]
+; CHECK-NEXT:    vmov.s8 r4, q0[2]
 ; CHECK-NEXT:    vmov q6[2], q6[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q6[3], q6[1], r4, r2
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r4, s20
 ; CHECK-NEXT:    vmov r2, s21
 ; CHECK-NEXT:    adds r5, r5, r4

 ; CHECK-NEXT:    vcmp.i32 ne, q5, zr
 ; CHECK-NEXT:    vmrs r5, p0
 ; CHECK-NEXT:    and r2, r5, #1
 ; CHECK-NEXT:    ubfx r4, r5, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    vmov q4[2], q4[0], r2, r4
 ; CHECK-NEXT:    vmov q4[3], q4[1], r2, r4
-; CHECK-NEXT:    vmov.u8 r2, q0[5]
-; CHECK-NEXT:    vmov.u8 r4, q0[4]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r2, q0[5]
+; CHECK-NEXT:    vmov.s8 r4, q0[4]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q5[3], q5[1], r4, r2
 ; CHECK-NEXT:    vand q4, q5, q4
 ; CHECK-NEXT:    vmov r4, s16
 ; CHECK-NEXT:    vmov r2, s17
 ; CHECK-NEXT:    adds.w r4, r4, r12
 ; CHECK-NEXT:    adc.w r12, r3, r2
 ; CHECK-NEXT:    vmov r2, s18
 ; CHECK-NEXT:    vmov r3, s19
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    ubfx r4, r5, #12, #1
 ; CHECK-NEXT:    ubfx r5, r5, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r5, r5, #0
 ; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q4[2], q4[0], r5, r4
 ; CHECK-NEXT:    vmov q4[3], q4[1], r5, r4
-; CHECK-NEXT:    vmov.u8 r5, q0[7]
-; CHECK-NEXT:    vmov.u8 r4, q0[6]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r5, q0[7]
+; CHECK-NEXT:    vmov.s8 r4, q0[6]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r4, r5
 ; CHECK-NEXT:    asrs r5, r5, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q5[3], q5[1], r4, r5
 ; CHECK-NEXT:    vand q4, q5, q4
 ; CHECK-NEXT:    vmov r4, s16
 ; CHECK-NEXT:    vmov r5, s17
 ; CHECK-NEXT:    adds r2, r2, r4

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r5, p0
 ; CHECK-NEXT:    and r2, r5, #1
 ; CHECK-NEXT:    ubfx r4, r5, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r4
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r4
-; CHECK-NEXT:    vmov.u8 r2, q0[9]
-; CHECK-NEXT:    vmov.u8 r4, q0[8]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r2, q0[9]
+; CHECK-NEXT:    vmov.s8 r4, q0[8]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r4, r2
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r4, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    adds.w r4, r4, r12
 ; CHECK-NEXT:    adc.w r12, r3, r2
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    vmov r3, s11
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    ubfx r4, r5, #12, #1
 ; CHECK-NEXT:    ubfx r5, r5, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r5, r5, #0
 ; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q2[2], q2[0], r5, r4
 ; CHECK-NEXT:    vmov q2[3], q2[1], r5, r4
-; CHECK-NEXT:    vmov.u8 r5, q0[11]
-; CHECK-NEXT:    vmov.u8 r4, q0[10]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r5, q0[11]
+; CHECK-NEXT:    vmov.s8 r4, q0[10]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r4, r5
 ; CHECK-NEXT:    asrs r5, r5, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q3[3], q3[1], r4, r5
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r4, s8
 ; CHECK-NEXT:    vmov r5, s9
 ; CHECK-NEXT:    adds r2, r2, r4

 ; CHECK-NEXT:    vcmp.i32 ne, q2, zr
 ; CHECK-NEXT:    vmrs r5, p0
 ; CHECK-NEXT:    and r2, r5, #1
 ; CHECK-NEXT:    ubfx r4, r5, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    vmov q1[2], q1[0], r2, r4
 ; CHECK-NEXT:    vmov q1[3], q1[1], r2, r4
-; CHECK-NEXT:    vmov.u8 r2, q0[13]
-; CHECK-NEXT:    vmov.u8 r4, q0[12]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r2, q0[13]
+; CHECK-NEXT:    vmov.s8 r4, q0[12]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r4, r2
 ; CHECK-NEXT:    asrs r2, r2, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q2[3], q2[1], r4, r2
 ; CHECK-NEXT:    vand q1, q2, q1
 ; CHECK-NEXT:    vmov r4, s4
 ; CHECK-NEXT:    vmov r2, s5
 ; CHECK-NEXT:    adds.w r4, r4, r12
 ; CHECK-NEXT:    adc.w r12, r3, r2
 ; CHECK-NEXT:    vmov r2, s6
 ; CHECK-NEXT:    vmov r3, s7
 ; CHECK-NEXT:    adds r2, r2, r4
 ; CHECK-NEXT:    ubfx r4, r5, #12, #1
 ; CHECK-NEXT:    ubfx r5, r5, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r5, r5, #0
 ; CHECK-NEXT:    adc.w r3, r3, r12
 ; CHECK-NEXT:    vmov q1[2], q1[0], r5, r4
 ; CHECK-NEXT:    vmov q1[3], q1[1], r5, r4
-; CHECK-NEXT:    vmov.u8 r5, q0[15]
-; CHECK-NEXT:    vmov.u8 r4, q0[14]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r5, q0[15]
+; CHECK-NEXT:    vmov.s8 r4, q0[14]
 ; CHECK-NEXT:    vmov q0[2], q0[0], r4, r5
 ; CHECK-NEXT:    asrs r5, r5, #31
 ; CHECK-NEXT:    asrs r4, r4, #31
 ; CHECK-NEXT:    vmov q0[3], q0[1], r4, r5
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    vmov r4, s0
 ; CHECK-NEXT:    vmov r5, s1
 ; CHECK-NEXT:    adds r2, r2, r4

llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll

entry:
   ret i64 %z
 }
 
 define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext(<16 x i8> %x, <16 x i8> %y) {
 ; CHECK-LABEL: add_v16i8_v16i64_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
-; CHECK-NEXT:    vmov.u8 r0, q1[1]
-; CHECK-NEXT:    vmov.u8 r1, q0[1]
-; CHECK-NEXT:    vmov.u8 r2, q1[0]
-; CHECK-NEXT:    vmov.u8 r3, q0[0]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q1[1]
+; CHECK-NEXT:    vmov.s8 r1, q0[1]
+; CHECK-NEXT:    vmov.s8 r2, q1[0]
+; CHECK-NEXT:    vmov.s8 r3, q0[0]
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r0
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r1
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    adds.w lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r3, q0[3]
+; CHECK-NEXT:    vmov.s8 r3, q0[3]
 ; CHECK-NEXT:    adc.w r12, r0, r1
-; CHECK-NEXT:    vmov.u8 r1, q1[3]
-; CHECK-NEXT:    vmov.u8 r0, q1[2]
-; CHECK-NEXT:    vmov.u8 r2, q0[2]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r1, q1[3]
+; CHECK-NEXT:    vmov.s8 r0, q1[2]
+; CHECK-NEXT:    vmov.s8 r2, q0[2]
 ; CHECK-NEXT:    smull r1, r3, r3, r1
 ; CHECK-NEXT:    smull r0, r2, r2, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r1
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds.w lr, r1, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[5]
+; CHECK-NEXT:    vmov.s8 r2, q1[5]
 ; CHECK-NEXT:    adc.w r12, r0, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[5]
-; CHECK-NEXT:    vmov.u8 r0, q1[4]
-; CHECK-NEXT:    vmov.u8 r1, q0[4]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r3, q0[5]
+; CHECK-NEXT:    vmov.s8 r0, q1[4]
+; CHECK-NEXT:    vmov.s8 r1, q0[4]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r1, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds.w lr, r1, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[7]
+; CHECK-NEXT:    vmov.s8 r2, q1[7]
 ; CHECK-NEXT:    adc.w r12, r0, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[7]
-; CHECK-NEXT:    vmov.u8 r0, q1[6]
-; CHECK-NEXT:    vmov.u8 r1, q0[6]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r3, q0[7]
+; CHECK-NEXT:    vmov.s8 r0, q1[6]
+; CHECK-NEXT:    vmov.s8 r1, q0[6]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r1, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds.w lr, r1, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[9]
+; CHECK-NEXT:    vmov.s8 r2, q1[9]
 ; CHECK-NEXT:    adc.w r12, r0, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[9]
-; CHECK-NEXT:    vmov.u8 r0, q1[8]
-; CHECK-NEXT:    vmov.u8 r1, q0[8]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r3, q0[9]
+; CHECK-NEXT:    vmov.s8 r0, q1[8]
+; CHECK-NEXT:    vmov.s8 r1, q0[8]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r1, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds.w lr, r1, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[11]
+; CHECK-NEXT:    vmov.s8 r2, q1[11]
 ; CHECK-NEXT:    adc.w r12, r0, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[11]
-; CHECK-NEXT:    vmov.u8 r0, q1[10]
-; CHECK-NEXT:    vmov.u8 r1, q0[10]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r3, q0[11]
+; CHECK-NEXT:    vmov.s8 r0, q1[10]
+; CHECK-NEXT:    vmov.s8 r1, q0[10]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r1, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r2, s10
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r0, r0, r12
 ; CHECK-NEXT:    adds.w lr, r1, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[13]
+; CHECK-NEXT:    vmov.s8 r2, q1[13]
 ; CHECK-NEXT:    adc.w r12, r0, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[13]
-; CHECK-NEXT:    vmov.u8 r0, q1[12]
-; CHECK-NEXT:    vmov.u8 r1, q0[12]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    vmov.s8 r3, q0[13]
+; CHECK-NEXT:    vmov.s8 r0, q1[12]
+; CHECK-NEXT:    vmov.s8 r1, q0[12]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r0, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r1, r3
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r2, r12, r0
 ; CHECK-NEXT:    vmov r0, s10
 ; CHECK-NEXT:    adds r0, r0, r1
 ; CHECK-NEXT:    adc.w r1, r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[14]
-; CHECK-NEXT:    vmov.u8 r3, q0[14]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[14]
+; CHECK-NEXT:    vmov.s8 r3, q0[14]
 ; CHECK-NEXT:    smlal r0, r1, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[15]
-; CHECK-NEXT:    vmov.u8 r3, q0[15]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[15]
+; CHECK-NEXT:    vmov.s8 r3, q0[15]
 ; CHECK-NEXT:    smlal r0, r1, r3, r2
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %xx = sext <16 x i8> %x to <16 x i64>
   %yy = sext <16 x i8> %y to <16 x i64>
   %m = mul <16 x i64> %xx, %yy
   %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
   ret i64 %z
entry:
   ret i64 %r
 }
 
 define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext(<16 x i8> %x, <16 x i8> %y, i64 %a) {
 ; CHECK-LABEL: add_v16i8_v16i64_acc_sext:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r7, lr}
-; CHECK-NEXT:    vmov.u8 r2, q1[1]
-; CHECK-NEXT:    vmov.u8 r3, q0[1]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[1]
+; CHECK-NEXT:    vmov.s8 r3, q0[1]
 ; CHECK-NEXT:    smull r12, r3, r3, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[0]
-; CHECK-NEXT:    sxtb.w lr, r2
-; CHECK-NEXT:    vmov.u8 r2, q0[0]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    vmov.u8 r4, q1[2]
+; CHECK-NEXT:    vmov.s8 lr, q1[0]
+; CHECK-NEXT:    vmov.s8 r2, q0[0]
+; CHECK-NEXT:    vmov.s8 r4, q1[2]
+; CHECK-NEXT:    vmov.s8 r5, q0[2]
 ; CHECK-NEXT:    smull r2, lr, r2, lr
-; CHECK-NEXT:    vmov.u8 r5, q0[2]
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r5, r5
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r12
 ; CHECK-NEXT:    smull r4, r5, r5, r4
 ; CHECK-NEXT:    vmov q2[3], q2[1], lr, r3
 ; CHECK-NEXT:    vmov lr, s10
 ; CHECK-NEXT:    vmov r2, s8
 ; CHECK-NEXT:    vmov r12, s9
 ; CHECK-NEXT:    adds.w lr, lr, r2
-; CHECK-NEXT:    vmov.u8 r2, q1[3]
+; CHECK-NEXT:    vmov.s8 r2, q1[3]
 ; CHECK-NEXT:    adc.w r12, r12, r3
-; CHECK-NEXT:    vmov.u8 r3, q0[3]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r3, q0[3]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r4, r2
 ; CHECK-NEXT:    vmov q2[3], q2[1], r5, r3
 ; CHECK-NEXT:    vmov r4, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    adds.w r5, lr, r4
 ; CHECK-NEXT:    vmov r4, s10
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds.w lr, r5, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[5]
+; CHECK-NEXT:    vmov.s8 r4, q0[5]
 ; CHECK-NEXT:    adc.w r12, r2, r3
-; CHECK-NEXT:    vmov.u8 r3, q1[5]
-; CHECK-NEXT:    vmov.u8 r2, q1[4]
-; CHECK-NEXT:    vmov.u8 r5, q0[4]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r5, r5
+; CHECK-NEXT:    vmov.s8 r3, q1[5]
+; CHECK-NEXT:    vmov.s8 r2, q1[4]
+; CHECK-NEXT:    vmov.s8 r5, q0[4]
 ; CHECK-NEXT:    smull r3, r4, r4, r3
 ; CHECK-NEXT:    smull r2, r5, r5, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r3
 ; CHECK-NEXT:    vmov q2[3], q2[1], r5, r4
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r5, s10
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds.w lr, r3, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[7]
+; CHECK-NEXT:    vmov.s8 r5, q1[7]
 ; CHECK-NEXT:    adc.w r12, r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[7]
-; CHECK-NEXT:    vmov.u8 r2, q1[6]
-; CHECK-NEXT:    vmov.u8 r3, q0[6]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r4, q0[7]
+; CHECK-NEXT:    vmov.s8 r2, q1[6]
+; CHECK-NEXT:    vmov.s8 r3, q0[6]
 ; CHECK-NEXT:    smull r5, r4, r4, r5
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r5
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r4
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r5, s10
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds.w lr, r3, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[9]
+; CHECK-NEXT:    vmov.s8 r5, q1[9]
 ; CHECK-NEXT:    adc.w r12, r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[9]
-; CHECK-NEXT:    vmov.u8 r2, q1[8]
-; CHECK-NEXT:    vmov.u8 r3, q0[8]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r4, q0[9]
+; CHECK-NEXT:    vmov.s8 r2, q1[8]
+; CHECK-NEXT:    vmov.s8 r3, q0[8]
 ; CHECK-NEXT:    smull r5, r4, r4, r5
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r5
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r4
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r5, s10
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds.w lr, r3, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[11]
+; CHECK-NEXT:    vmov.s8 r5, q1[11]
 ; CHECK-NEXT:    adc.w r12, r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[11]
-; CHECK-NEXT:    vmov.u8 r2, q1[10]
-; CHECK-NEXT:    vmov.u8 r3, q0[10]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r4, q0[11]
+; CHECK-NEXT:    vmov.s8 r2, q1[10]
+; CHECK-NEXT:    vmov.s8 r3, q0[10]
 ; CHECK-NEXT:    smull r5, r4, r4, r5
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r5
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r4
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r5, s10
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds.w lr, r3, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[13]
+; CHECK-NEXT:    vmov.s8 r5, q1[13]
 ; CHECK-NEXT:    adc.w r12, r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[13]
-; CHECK-NEXT:    vmov.u8 r2, q1[12]
-; CHECK-NEXT:    vmov.u8 r3, q0[12]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r4, q0[13]
+; CHECK-NEXT:    vmov.s8 r2, q1[12]
+; CHECK-NEXT:    vmov.s8 r3, q0[12]
 ; CHECK-NEXT:    smull r5, r4, r4, r5
 ; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r5
 ; CHECK-NEXT:    vmov q2[3], q2[1], r3, r4
 ; CHECK-NEXT:    vmov r3, s8
 ; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r5, s10
 ; CHECK-NEXT:    adds.w r3, r3, lr
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds r3, r3, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[14]
+; CHECK-NEXT:    vmov.s8 r5, q1[14]
 ; CHECK-NEXT:    adcs r2, r4
-; CHECK-NEXT:    vmov.u8 r4, q0[14]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r4, q0[14]
 ; CHECK-NEXT:    smlal r3, r2, r4, r5
-; CHECK-NEXT:    vmov.u8 r5, q1[15]
-; CHECK-NEXT:    vmov.u8 r4, q0[15]
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r5, q1[15]
+; CHECK-NEXT:    vmov.s8 r4, q0[15]
 ; CHECK-NEXT:    smlal r3, r2, r4, r5
 ; CHECK-NEXT:    adds r0, r0, r3
 ; CHECK-NEXT:    adcs r1, r2
 ; CHECK-NEXT:    pop {r4, r5, r7, pc}
 entry:
   %xx = sext <16 x i8> %x to <16 x i64>
   %yy = sext <16 x i8> %y to <16 x i64>
   %m = mul <16 x i64> %xx, %yy

llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vcmp.i8 eq, q2, zr
 ; CHECK-NEXT:    vmov.i8 q2, #0x0
 ; CHECK-NEXT:    vmov.i8 q3, #0xff
-; CHECK-NEXT:    vmov.u8 r3, q1[0]
+; CHECK-NEXT:    vmov.s8 r3, q1[0]
 ; CHECK-NEXT:    vpsel q4, q3, q2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r4, q0[4]
 ; CHECK-NEXT:    vmov.u8 r0, q4[0]
-; CHECK-NEXT:    vmov.u8 r4, q0[4]
 ; CHECK-NEXT:    vmov.16 q5[0], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[1]
 ; CHECK-NEXT:    vmov.16 q5[1], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[2]
 ; CHECK-NEXT:    vmov.16 q5[2], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[3]
 ; CHECK-NEXT:    vmov.16 q5[3], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[4]
 ; CHECK-NEXT:    vmov.16 q5[4], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[5]
 ; CHECK-NEXT:    vmov.16 q5[5], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[6]
 ; CHECK-NEXT:    vmov.16 q5[6], r0
 ; CHECK-NEXT:    vmov.u8 r0, q4[7]
 ; CHECK-NEXT:    vmov.16 q5[7], r0
-; CHECK-NEXT:    sxtb r4, r4
 ; CHECK-NEXT:    vcmp.i16 ne, q5, zr
 ; CHECK-NEXT:    vpsel q5, q3, q2
 ; CHECK-NEXT:    vmov.u16 r0, q5[2]
 ; CHECK-NEXT:    vmov.u16 r1, q5[0]
 ; CHECK-NEXT:    vmov q6[2], q6[0], r1, r0
 ; CHECK-NEXT:    vmov.u16 r0, q5[3]
 ; CHECK-NEXT:    vmov.u16 r1, q5[1]
 ; CHECK-NEXT:    vmov q6[3], q6[1], r1, r0
 ; CHECK-NEXT:    vcmp.i32 ne, q6, zr
 ; CHECK-NEXT:    vmrs r0, p0
 ; CHECK-NEXT:    and r2, r0, #1
 ; CHECK-NEXT:    ubfx r1, r0, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r1, r1, #0
 ; CHECK-NEXT:    vmov q6[2], q6[0], r2, r1
 ; CHECK-NEXT:    vmov q6[3], q6[1], r2, r1
-; CHECK-NEXT:    vmov.u8 r1, q1[1]
-; CHECK-NEXT:    vmov.u8 r2, q0[1]
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r1, q1[1]
+; CHECK-NEXT:    vmov.s8 r2, q0[1]
 ; CHECK-NEXT:    smull r1, r12, r2, r1
-; CHECK-NEXT:    vmov.u8 r2, q0[0]
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q0[0]
 ; CHECK-NEXT:    smull r2, r3, r2, r3
 ; CHECK-NEXT:    vmov q7[2], q7[0], r2, r1
 ; CHECK-NEXT:    vmov q7[3], q7[1], r3, r12
 ; CHECK-NEXT:    vand q6, q7, q6
 ; CHECK-NEXT:    vmov r3, s26
 ; CHECK-NEXT:    vmov r1, s24
 ; CHECK-NEXT:    vmov r12, s27
 ; CHECK-NEXT:    vmov r2, s25
 ; CHECK-NEXT:    adds.w lr, r1, r3
 ; CHECK-NEXT:    ubfx r3, r0, #12, #1
 ; CHECK-NEXT:    ubfx r0, r0, #8, #1
 ; CHECK-NEXT:    rsb.w r3, r3, #0
 ; CHECK-NEXT:    rsb.w r0, r0, #0
-; CHECK-NEXT:    vmov.u8 r1, q1[2]
-; CHECK-NEXT:    vmov q6[2], q6[0], r0, r3
 ; CHECK-NEXT:    adc.w r12, r12, r2
+; CHECK-NEXT:    vmov q6[2], q6[0], r0, r3
+; CHECK-NEXT:    vmov.s8 r1, q1[2]
 ; CHECK-NEXT:    vmov q6[3], q6[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q1[3]
-; CHECK-NEXT:    vmov.u8 r3, q0[3]
-; CHECK-NEXT:    vmov.u8 r2, q0[2]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r1, r1
-; CHECK-NEXT:    sxtb r2, r2
+; CHECK-NEXT:    vmov.s8 r2, q0[2]
+; CHECK-NEXT:    vmov.s8 r0, q1[3]
+; CHECK-NEXT:    vmov.s8 r3, q0[3]
 ; CHECK-NEXT:    smull r0, r3, r3, r0
 ; CHECK-NEXT:    smull r1, r2, r2, r1
 ; CHECK-NEXT:    vmov q7[2], q7[0], r1, r0
 ; CHECK-NEXT:    vmov q7[3], q7[1], r2, r3
 ; CHECK-NEXT:    vand q6, q7, q6
 ; CHECK-NEXT:    vmov r1, s24
 ; CHECK-NEXT:    vmov r0, s25
 ; CHECK-NEXT:    vmov r3, s27
 ; CHECK-NEXT:    adds.w r1, r1, lr
 ; CHECK-NEXT:    adc.w r2, r12, r0
 ; CHECK-NEXT:    vmov r0, s26
 ; CHECK-NEXT:    adds.w r12, r1, r0
-; CHECK-NEXT:    vmov.u8 r1, q1[4]
+; CHECK-NEXT:    vmov.s8 r1, q1[4]
 ; CHECK-NEXT:    adc.w lr, r2, r3
 ; CHECK-NEXT:    vmov.u16 r2, q5[6]
 ; CHECK-NEXT:    vmov.u16 r3, q5[4]
-; CHECK-NEXT:    sxtb r1, r1
+; CHECK-NEXT:    smull r1, r4, r4, r1
 ; CHECK-NEXT:    vmov q6[2], q6[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q5[7]
 ; CHECK-NEXT:    vmov.u16 r3, q5[5]
-; CHECK-NEXT:    smull r1, r4, r4, r1
 ; CHECK-NEXT:    vmov q6[3], q6[1], r3, r2
 ; CHECK-NEXT:    vcmp.i32 ne, q6, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r0, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r0, r0, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q5[2], q5[0], r0, r3
 ; CHECK-NEXT:    vmov q5[3], q5[1], r0, r3
-; CHECK-NEXT:    vmov.u8 r0, q1[5]
-; CHECK-NEXT:    vmov.u8 r3, q0[5]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r0, q1[5]
+; CHECK-NEXT:    vmov.s8 r3, q0[5]
 ; CHECK-NEXT:    smull r0, r3, r3, r0
 ; CHECK-NEXT:    vmov q6[2], q6[0], r1, r0
 ; CHECK-NEXT:    vmov q6[3], q6[1], r4, r3
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r1, s20
 ; CHECK-NEXT:    vmov r0, s21
 ; CHECK-NEXT:    vmov r4, s22
 ; CHECK-NEXT:    vmov r3, s23
 ; CHECK-NEXT:    adds.w r1, r1, r12
 ; CHECK-NEXT:    adc.w r0, r0, lr
 ; CHECK-NEXT:    adds r1, r1, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[6]
+; CHECK-NEXT:    vmov.s8 r4, q1[6]
 ; CHECK-NEXT:    adc.w r12, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r0, q0[6]
+; CHECK-NEXT:    vmov.s8 r0, q0[6]
 ; CHECK-NEXT:    vmov q5[2], q5[0], r2, r3
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q5[3], q5[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[7]
-; CHECK-NEXT:    vmov.u8 r3, q0[7]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[7]
+; CHECK-NEXT:    vmov.s8 r3, q0[7]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
-; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q6[2], q6[0], r0, r2
 ; CHECK-NEXT:    vmov q6[3], q6[1], r4, r3
 ; CHECK-NEXT:    vand q5, q6, q5
 ; CHECK-NEXT:    vmov r2, s20
 ; CHECK-NEXT:    vmov r0, s21
 ; CHECK-NEXT:    vmov r3, s23
 ; CHECK-NEXT:    adds r1, r1, r2
 ; CHECK-NEXT:    adc.w r2, r12, r0
 ; CHECK-NEXT:    vmov r0, s22
 ; CHECK-NEXT:    adds.w r12, r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[8]
+; CHECK-NEXT:    vmov.s8 r0, q1[8]
 ; CHECK-NEXT:    adc.w lr, r2, r3
 ; CHECK-NEXT:    vmov.u8 r2, q4[8]
 ; CHECK-NEXT:    vmov.16 q5[0], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[9]
 ; CHECK-NEXT:    vmov.16 q5[1], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[10]
 ; CHECK-NEXT:    vmov.16 q5[2], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[11]
 ; CHECK-NEXT:    vmov.16 q5[3], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[12]
 ; CHECK-NEXT:    vmov.16 q5[4], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[13]
 ; CHECK-NEXT:    vmov.16 q5[5], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[14]
 ; CHECK-NEXT:    vmov.16 q5[6], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[15]
 ; CHECK-NEXT:    vmov.16 q5[7], r2
-; CHECK-NEXT:    vmov.u8 r1, q0[8]
+; CHECK-NEXT:    vmov.s8 r1, q0[8]
 ; CHECK-NEXT:    vcmp.i16 ne, q5, zr
-; CHECK-NEXT:    sxtb r0, r0
+; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vpsel q2, q3, q2
-; CHECK-NEXT:    sxtb r1, r1
 ; CHECK-NEXT:    vmov.u16 r2, q2[2]
 ; CHECK-NEXT:    vmov.u16 r3, q2[0]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q2[3]
 ; CHECK-NEXT:    vmov.u16 r3, q2[1]
-; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q3[3], q3[1], r3, r2
 ; CHECK-NEXT:    vcmp.i32 ne, q3, zr
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r4, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q3[2], q3[0], r4, r3
 ; CHECK-NEXT:    vmov q3[3], q3[1], r4, r3
-; CHECK-NEXT:    vmov.u8 r3, q1[9]
-; CHECK-NEXT:    vmov.u8 r4, q0[9]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r3, q1[9]
+; CHECK-NEXT:    vmov.s8 r4, q0[9]
 ; CHECK-NEXT:    smull r3, r4, r4, r3
 ; CHECK-NEXT:    vmov q4[2], q4[0], r0, r3
 ; CHECK-NEXT:    vmov q4[3], q4[1], r1, r4
 ; CHECK-NEXT:    vand q3, q4, q3
 ; CHECK-NEXT:    vmov r1, s12
 ; CHECK-NEXT:    vmov r0, s13
 ; CHECK-NEXT:    vmov r4, s14
 ; CHECK-NEXT:    vmov r3, s15
 ; CHECK-NEXT:    adds.w r1, r1, r12
 ; CHECK-NEXT:    adc.w r0, r0, lr
 ; CHECK-NEXT:    adds r1, r1, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[10]
+; CHECK-NEXT:    vmov.s8 r4, q1[10]
 ; CHECK-NEXT:    adc.w r12, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r0, q0[10]
+; CHECK-NEXT:    vmov.s8 r0, q0[10]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r2, r3
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q3[3], q3[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[11]
-; CHECK-NEXT:    vmov.u8 r3, q0[11]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[11]
+; CHECK-NEXT:    vmov.s8 r3, q0[11]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
-; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q4[2], q4[0], r0, r2
 ; CHECK-NEXT:    vmov q4[3], q4[1], r4, r3
 ; CHECK-NEXT:    vand q3, q4, q3
 ; CHECK-NEXT:    vmov r2, s12
 ; CHECK-NEXT:    vmov r0, s13
 ; CHECK-NEXT:    vmov r3, s15
 ; CHECK-NEXT:    adds r1, r1, r2
 ; CHECK-NEXT:    adc.w r2, r12, r0
 ; CHECK-NEXT:    vmov r0, s14
 ; CHECK-NEXT:    adds.w r12, r1, r0
-; CHECK-NEXT:    vmov.u8 r0, q1[12]
+; CHECK-NEXT:    vmov.s8 r0, q1[12]
 ; CHECK-NEXT:    adc.w lr, r2, r3
 ; CHECK-NEXT:    vmov.u16 r2, q2[6]
 ; CHECK-NEXT:    vmov.u16 r3, q2[4]
-; CHECK-NEXT:    vmov.u8 r1, q0[12]
+; CHECK-NEXT:    vmov.s8 r1, q0[12]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q2[7]
 ; CHECK-NEXT:    vmov.u16 r3, q2[5]
-; CHECK-NEXT:    sxtb r0, r0
+; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmov q3[3], q3[1], r3, r2
-; CHECK-NEXT:    sxtb r1, r1
 ; CHECK-NEXT:    vcmp.i32 ne, q3, zr
-; CHECK-NEXT:    smull r0, r1, r1, r0
 ; CHECK-NEXT:    vmrs r2, p0
 ; CHECK-NEXT:    and r4, r2, #1
 ; CHECK-NEXT:    ubfx r3, r2, #4, #1
 ; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q2[2], q2[0], r4, r3
 ; CHECK-NEXT:    vmov q2[3], q2[1], r4, r3
-; CHECK-NEXT:    vmov.u8 r3, q1[13]
-; CHECK-NEXT:    vmov.u8 r4, q0[13]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r3, q1[13]
+; CHECK-NEXT:    vmov.s8 r4, q0[13]
 ; CHECK-NEXT:    smull r3, r4, r4, r3
 ; CHECK-NEXT:    vmov q3[2], q3[0], r0, r3
 ; CHECK-NEXT:    vmov q3[3], q3[1], r1, r4
 ; CHECK-NEXT:    vand q2, q3, q2
 ; CHECK-NEXT:    vmov r1, s8
 ; CHECK-NEXT:    vmov r0, s9
 ; CHECK-NEXT:    vmov r4, s10
 ; CHECK-NEXT:    vmov r3, s11
 ; CHECK-NEXT:    adds.w r1, r1, r12
 ; CHECK-NEXT:    adc.w r0, r0, lr
 ; CHECK-NEXT:    adds r1, r1, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[14]
+; CHECK-NEXT:    vmov.s8 r4, q1[14]
 ; CHECK-NEXT:    adc.w r12, r0, r3
 ; CHECK-NEXT:    ubfx r3, r2, #12, #1
 ; CHECK-NEXT:    ubfx r2, r2, #8, #1
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r0, q0[14]
+; CHECK-NEXT:    vmov.s8 r0, q0[14]
 ; CHECK-NEXT:    vmov q2[2], q2[0], r2, r3
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q2[3], q2[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[15]
-; CHECK-NEXT:    vmov.u8 r3, q0[15]
-; CHECK-NEXT:    sxtb r0, r0
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[15]
+; CHECK-NEXT:    vmov.s8 r3, q0[15]
 ; CHECK-NEXT:    smull r2, r3, r3, r2
-; CHECK-NEXT:    smull r0, r4, r0, r4
 ; CHECK-NEXT:    vmov q0[2], q0[0], r0, r2
 ; CHECK-NEXT:    vmov q0[3], q0[1], r4, r3
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    vmov r0, s1
 ; CHECK-NEXT:    vmov r3, s3
 ; CHECK-NEXT:    adds r1, r1, r2
 ; CHECK-NEXT:    adc.w r2, r12, r0

 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, lr}
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vcmp.i8 eq, q2, zr
 ; CHECK-NEXT:    vmov.i8 q2, #0x0
 ; CHECK-NEXT:    vmov.i8 q3, #0xff
-; CHECK-NEXT:    vmov.u8 r4, q0[0]
+; CHECK-NEXT:    vmov.s8 r4, q0[0]
 ; CHECK-NEXT:    vpsel q4, q3, q2
-; CHECK-NEXT:    sxtb r4, r4
+; CHECK-NEXT:    vmov.s8 r5, q0[2]
 ; CHECK-NEXT:    vmov.u8 r2, q4[0]
-; CHECK-NEXT:    vmov.u8 r5, q0[2]
 ; CHECK-NEXT:    vmov.16 q5[0], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[1]
 ; CHECK-NEXT:    vmov.16 q5[1], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[2]
 ; CHECK-NEXT:    vmov.16 q5[2], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[3]
 ; CHECK-NEXT:    vmov.16 q5[3], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[4]
 ; CHECK-NEXT:    vmov.16 q5[4], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[5]
 ; CHECK-NEXT:    vmov.16 q5[5], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[6]
 ; CHECK-NEXT:    vmov.16 q5[6], r2
 ; CHECK-NEXT:    vmov.u8 r2, q4[7]
 ; CHECK-NEXT:    vmov.16 q5[7], r2
-; CHECK-NEXT:    sxtb r5, r5
 ; CHECK-NEXT:    vcmp.i16 ne, q5, zr
 ; CHECK-NEXT:    vpsel q5, q3, q2
 ; CHECK-NEXT:    vmov.u16 r2, q5[2]
 ; CHECK-NEXT:    vmov.u16 r3, q5[0]
 ; CHECK-NEXT:    vmov q6[2], q6[0], r3, r2
 ; CHECK-NEXT:    vmov.u16 r2, q5[3]
 ; CHECK-NEXT:    vmov.u16 r3, q5[1]
 ; CHECK-NEXT:    vmov q6[3], q6[1], r3, r2
 ; CHECK-NEXT:    vcmp.i32 ne, q6, zr
 ; CHECK-NEXT:    vmrs r12, p0
 ; CHECK-NEXT:    and r2, r12, #1
 ; CHECK-NEXT:    ubfx r3, r12, #4, #1
 ; CHECK-NEXT:    rsbs r2, r2, #0
 ; CHECK-NEXT:    rsbs r3, r3, #0
 ; CHECK-NEXT:    vmov q6[2], q6[0], r2, r3
 ; CHECK-NEXT:    vmov q6[3], q6[1], r2, r3
-; CHECK-NEXT:    vmov.u8 r2, q1[1]
-; CHECK-NEXT:    vmov.u8 r3, q0[1]
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r2, q1[1]
+; CHECK-NEXT:    vmov.s8 r3, q0[1]
 ; CHECK-NEXT:    smull r2, lr, r3, r2
-; CHECK-NEXT:    vmov.u8 r3, q1[0]
-; CHECK-NEXT:    sxtb r3, r3
+; CHECK-NEXT:    vmov.s8 r3, q1[0]
 ; CHECK-NEXT:    smull r3, r4, r4, r3
 ; CHECK-NEXT:    vmov q7[2], q7[0], r3, r2
 ; CHECK-NEXT:    vmov q7[3], q7[1], r4, lr
 ; CHECK-NEXT:    vand q6, q7, q6
 ; CHECK-NEXT:    vmov r4, s26
 ; CHECK-NEXT:    vmov r2, s24
 ; CHECK-NEXT:    vmov lr, s27
 ; CHECK-NEXT:    vmov r3, s25
 ; CHECK-NEXT:    adds r6, r2, r4
 ; CHECK-NEXT:    ubfx r4, r12, #12, #1
 ; CHECK-NEXT:    ubfx r2, r12, #8, #1
 ; CHECK-NEXT:    rsb.w r4, r4, #0
 ; CHECK-NEXT:    rsb.w r2, r2, #0
 ; CHECK-NEXT:    adc.w lr, lr, r3
 ; CHECK-NEXT:    vmov q6[2], q6[0], r2, r4
-; CHECK-NEXT:    vmov.u8 r3, q1[2]
+; CHECK-NEXT:    vmov.s8 r3, q1[2]
 ; CHECK-NEXT:    vmov q6[3], q6[1], r2, r4
-; CHECK-NEXT:    vmov.u8 r2, q1[3]
-; CHECK-NEXT:    vmov.u8 r4, q0[3]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    smull r2, r4, r4, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[3]
+; CHECK-NEXT:    vmov.s8 r4, q0[3]
 ; CHECK-NEXT:    smull r3, r5, r5, r3
+; CHECK-NEXT:    smull r2, r4, r4, r2
 ; CHECK-NEXT:    vmov q7[2], q7[0], r3, r2
 ; CHECK-NEXT:    vmov q7[3], q7[1], r5, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[4]
 ; CHECK-NEXT:    vand q6, q7, q6
-; CHECK-NEXT:    sxtb r4, r4
 ; CHECK-NEXT:    vmov r3, s24
 ; CHECK-NEXT:    vmov r2, s25
-; CHECK-NEXT:    vmov r5, s26
+; CHECK-NEXT:    vmov r5, s27
 ; CHECK-NEXT:    adds r3, r3, r6
-; CHECK-NEXT:    vmov r6, s27
-; CHECK-NEXT:    adc.w r2, r2, lr
-; CHECK-NEXT:    adds.w r12, r3, r5
-; CHECK-NEXT:    vmov.u8 r3, q0[4]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    adc.w lr, r2, r6
-; CHECK-NEXT:    vmov.u16 r2, q5[6]
-; CHECK-NEXT:    vmov.u16 r6, q5[4]
-; CHECK-NEXT:    vmov q6[2], q6[0], r6, r2
-; CHECK-NEXT:    vmov.u16 r2, q5[7]
-; CHECK-NEXT:    vmov.u16 r6, q5[5]
-; CHECK-NEXT:    vmov q6[3], q6[1], r6, r2
+; CHECK-NEXT:    adc.w r6, lr, r2
+; CHECK-NEXT:    vmov r2, s26
+; CHECK-NEXT:    adds.w r12, r3, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[4]
+; CHECK-NEXT:    adc.w lr, r6, r5
+; CHECK-NEXT:    vmov.u16 r6, q5[6]
+; CHECK-NEXT:    vmov.u16 r5, q5[4]
+; CHECK-NEXT:    vmov.s8 r3, q0[4]
+; CHECK-NEXT:    vmov q6[2], q6[0], r5, r6
+; CHECK-NEXT:    vmov.u16 r6, q5[7]
+; CHECK-NEXT:    vmov.u16 r5, q5[5]
+; CHECK-NEXT:    smull r2, r3, r3, r2
+; CHECK-NEXT:    vmov q6[3], q6[1], r5, r6
 ; CHECK-NEXT:    vcmp.i32 ne, q6, zr
-; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r5, r2, #1
-; CHECK-NEXT:    ubfx r6, r2, #4, #1
+; CHECK-NEXT:    vmrs r6, p0
+; CHECK-NEXT:    and r4, r6, #1
+; CHECK-NEXT:    ubfx r5, r6, #4, #1
+; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r6, r6, #0
-; CHECK-NEXT:    vmov q5[2], q5[0], r5, r6
-; CHECK-NEXT:    vmov q5[3], q5[1], r5, r6
-; CHECK-NEXT:    vmov.u8 r6, q1[5]
-; CHECK-NEXT:    vmov.u8 r5, q0[5]
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r6, r5, r5, r6
-; CHECK-NEXT:    vmov q6[2], q6[0], r3, r6
-; CHECK-NEXT:    vmov q6[3], q6[1], r4, r5
+; CHECK-NEXT:    vmov q5[2], q5[0], r4, r5
+; CHECK-NEXT:    vmov q5[3], q5[1], r4, r5
+; CHECK-NEXT:    vmov.s8 r5, q1[5]
+; CHECK-NEXT:    vmov.s8 r4, q0[5]
+; CHECK-NEXT:    smull r5, r4, r4, r5
+; CHECK-NEXT:    vmov q6[2], q6[0], r2, r5
+; CHECK-NEXT:    vmov q6[3], q6[1], r3, r4
 ; CHECK-NEXT:    vand q5, q6, q5
-; CHECK-NEXT:    vmov r4, s20
-; CHECK-NEXT:    vmov r3, s21
-; CHECK-NEXT:    vmov r5, s23
-; CHECK-NEXT:    adds.w r6, r12, r4
+; CHECK-NEXT:    vmov r3, s20
+; CHECK-NEXT:    vmov r2, s21
 ; CHECK-NEXT:    vmov r4, s22
-; CHECK-NEXT:    adc.w r3, r3, lr
-; CHECK-NEXT:    adds r6, r6, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[6]
-; CHECK-NEXT:    adc.w r12, r3, r5
-; CHECK-NEXT:    ubfx r5, r2, #12, #1
-; CHECK-NEXT:    ubfx r2, r2, #8, #1
+; CHECK-NEXT:    vmov r5, s23
+; CHECK-NEXT:    adds.w r3, r3, r12
+; CHECK-NEXT:    adc.w r2, r2, lr
+; CHECK-NEXT:    adds r3, r3, r4
+; CHECK-NEXT:    vmov.s8 r4, q1[6]
+; CHECK-NEXT:    adc.w r12, r2, r5
+; CHECK-NEXT:    ubfx r5, r6, #12, #1
+; CHECK-NEXT:    ubfx r6, r6, #8, #1
 ; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r3, q0[6]
-; CHECK-NEXT:    vmov q5[2], q5[0], r2, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov q5[3], q5[1], r2, r5
-; CHECK-NEXT:    vmov.u8 r2, q1[7]
-; CHECK-NEXT:    vmov.u8 r5, q0[7]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r2, r5, r5, r2
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    vmov q6[2], q6[0], r3, r2
+; CHECK-NEXT:    rsbs r6, r6, #0
+; CHECK-NEXT:    vmov.s8 r2, q0[6]
+; CHECK-NEXT:    vmov q5[2], q5[0], r6, r5
+; CHECK-NEXT:    smull r2, r4, r2, r4
+; CHECK-NEXT:    vmov q5[3], q5[1], r6, r5
+; CHECK-NEXT:    vmov.s8 r6, q1[7]
+; CHECK-NEXT:    vmov.s8 r5, q0[7]
+; CHECK-NEXT:    smull r6, r5, r5, r6
+; CHECK-NEXT:    vmov q6[2], q6[0], r2, r6
 ; CHECK-NEXT:    vmov q6[3], q6[1], r4, r5
-; CHECK-NEXT:    vmov.u8 r4, q1[8]
 ; CHECK-NEXT:    vand q5, q6, q5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov r3, s20
+; CHECK-NEXT:    vmov r6, s20
 ; CHECK-NEXT:    vmov r2, s21
-; CHECK-NEXT:    vmov r5, s22
+; CHECK-NEXT:    vmov r5, s23
 ; CHECK-NEXT:    adds r3, r3, r6
-; CHECK-NEXT:    vmov r6, s23
-; CHECK-NEXT:    adc.w r2, r2, r12
-; CHECK-NEXT:    adds.w r12, r3, r5
-; CHECK-NEXT:    vmov.u8 r3, q0[8]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    adc.w lr, r2, r6
-; CHECK-NEXT:    vmov.u8 r2, q4[8]
-; CHECK-NEXT:    vmov.16 q5[0], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[9]
-; CHECK-NEXT:    vmov.16 q5[1], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[10]
-; CHECK-NEXT:    vmov.16 q5[2], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[11]
-; CHECK-NEXT:    vmov.16 q5[3], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[12]
-; CHECK-NEXT:    vmov.16 q5[4], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[13]
-; CHECK-NEXT:    vmov.16 q5[5], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[14]
-; CHECK-NEXT:    vmov.16 q5[6], r2
-; CHECK-NEXT:    vmov.u8 r2, q4[15]
-; CHECK-NEXT:    vmov.16 q5[7], r2
+; CHECK-NEXT:    adc.w r6, r12, r2
+; CHECK-NEXT:    vmov r2, s22
+; CHECK-NEXT:    adds.w r12, r3, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[8]
+; CHECK-NEXT:    adc.w lr, r6, r5
+; CHECK-NEXT:    vmov.u8 r6, q4[8]
+; CHECK-NEXT:    vmov.16 q5[0], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[9]
+; CHECK-NEXT:    vmov.16 q5[1], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[10]
+; CHECK-NEXT:    vmov.16 q5[2], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[11]
+; CHECK-NEXT:    vmov.16 q5[3], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[12]
+; CHECK-NEXT:    vmov.16 q5[4], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[13]
+; CHECK-NEXT:    vmov.16 q5[5], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[14]
+; CHECK-NEXT:    vmov.16 q5[6], r6
+; CHECK-NEXT:    vmov.u8 r6, q4[15]
+; CHECK-NEXT:    vmov.16 q5[7], r6
+; CHECK-NEXT:    vmov.s8 r3, q0[8]
 ; CHECK-NEXT:    vcmp.i16 ne, q5, zr
+; CHECK-NEXT:    smull r2, r3, r3, r2
 ; CHECK-NEXT:    vpsel q2, q3, q2
-; CHECK-NEXT:    vmov.u16 r2, q2[2]
-; CHECK-NEXT:    vmov.u16 r6, q2[0]
-; CHECK-NEXT:    vmov q3[2], q3[0], r6, r2
-; CHECK-NEXT:    vmov.u16 r2, q2[3]
-; CHECK-NEXT:    vmov.u16 r6, q2[1]
-; CHECK-NEXT:    vmov q3[3], q3[1], r6, r2
-; CHECK-NEXT:    vcmp.i32 ne, q3, zr
-; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r5, r2, #1
-; CHECK-NEXT:    ubfx r6, r2, #4, #1
-; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r6, r6, #0
+; CHECK-NEXT:    vmov.u16 r6, q2[2]
+; CHECK-NEXT:    vmov.u16 r5, q2[0]
 ; CHECK-NEXT:    vmov q3[2], q3[0], r5, r6
+; CHECK-NEXT:    vmov.u16 r6, q2[3]
+; CHECK-NEXT:    vmov.u16 r5, q2[1]
 ; CHECK-NEXT:    vmov q3[3], q3[1], r5, r6
-; CHECK-NEXT:    vmov.u8 r6, q1[9]
-; CHECK-NEXT:    vmov.u8 r5, q0[9]
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r6, r5, r5, r6
-; CHECK-NEXT:    vmov q4[2], q4[0], r3, r6
-; CHECK-NEXT:    vmov q4[3], q4[1], r4, r5
+; CHECK-NEXT:    vcmp.i32 ne, q3, zr
+; CHECK-NEXT:    vmrs r6, p0
+; CHECK-NEXT:    and r4, r6, #1
+; CHECK-NEXT:    ubfx r5, r6, #4, #1
+; CHECK-NEXT:    rsbs r4, r4, #0
+; CHECK-NEXT:    rsbs r5, r5, #0
+; CHECK-NEXT:    vmov q3[2], q3[0], r4, r5
+; CHECK-NEXT:    vmov q3[3], q3[1], r4, r5
+; CHECK-NEXT:    vmov.s8 r5, q1[9]
+; CHECK-NEXT:    vmov.s8 r4, q0[9]
+; CHECK-NEXT:    smull r5, r4, r4, r5
+; CHECK-NEXT:    vmov q4[2], q4[0], r2, r5
+; CHECK-NEXT:    vmov q4[3], q4[1], r3, r4
 ; CHECK-NEXT:    vand q3, q4, q3
-; CHECK-NEXT:    vmov r4, s12
-; CHECK-NEXT:    vmov r3, s13
-; CHECK-NEXT:    vmov r5, s15
-; CHECK-NEXT:    adds.w r6, r12, r4
+; CHECK-NEXT:    vmov r3, s12
+; CHECK-NEXT:    vmov r2, s13
 ; CHECK-NEXT:    vmov r4, s14
-; CHECK-NEXT:    adc.w r3, r3, lr
-; CHECK-NEXT:    adds r6, r6, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[10]
-; CHECK-NEXT:    adc.w r12, r3, r5
-; CHECK-NEXT:    ubfx r5, r2, #12, #1
-; CHECK-NEXT:    ubfx r2, r2, #8, #1
+; CHECK-NEXT:    vmov r5, s15
+; CHECK-NEXT:    adds.w r3, r3, r12
+; CHECK-NEXT:    adc.w r2, r2, lr
+; CHECK-NEXT:    adds r3, r3, r4
+; CHECK-NEXT:    vmov.s8 r4, q1[10]
+; CHECK-NEXT:    adc.w r12, r2, r5
+; CHECK-NEXT:    ubfx r5, r6, #12, #1
+; CHECK-NEXT:    ubfx r6, r6, #8, #1
 ; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r3, q0[10]
-; CHECK-NEXT:    vmov q3[2], q3[0], r2, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov q3[3], q3[1], r2, r5
-; CHECK-NEXT:    vmov.u8 r2, q1[11]
-; CHECK-NEXT:    vmov.u8 r5, q0[11]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r2, r5, r5, r2
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    vmov q4[2], q4[0], r3, r2
+; CHECK-NEXT:    rsbs r6, r6, #0
+; CHECK-NEXT:    vmov.s8 r2, q0[10]
+; CHECK-NEXT:    vmov q3[2], q3[0], r6, r5
+; CHECK-NEXT:    smull r2, r4, r2, r4
+; CHECK-NEXT:    vmov q3[3], q3[1], r6, r5
+; CHECK-NEXT:    vmov.s8 r6, q1[11]
+; CHECK-NEXT:    vmov.s8 r5, q0[11]
+; CHECK-NEXT:    smull r6, r5, r5, r6
+; CHECK-NEXT:    vmov q4[2], q4[0], r2, r6
 ; CHECK-NEXT:    vmov q4[3], q4[1], r4, r5
-; CHECK-NEXT:    vmov.u8 r4, q1[12]
 ; CHECK-NEXT:    vand q3, q4, q3
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov r3, s12
+; CHECK-NEXT:    vmov r6, s12
 ; CHECK-NEXT:    vmov r2, s13
-; CHECK-NEXT:    vmov r5, s14
+; CHECK-NEXT:    vmov r5, s15
 ; CHECK-NEXT:    adds r3, r3, r6
-; CHECK-NEXT:    vmov r6, s15
-; CHECK-NEXT:    adc.w r2, r2, r12
-; CHECK-NEXT:    adds.w r12, r3, r5
-; CHECK-NEXT:    vmov.u8 r3, q0[12]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    adc.w lr, r2, r6
-; CHECK-NEXT:    vmov.u16 r2, q2[6]
-; CHECK-NEXT:    vmov.u16 r6, q2[4]
-; CHECK-NEXT:    vmov q3[2], q3[0], r6, r2
-; CHECK-NEXT:    vmov.u16 r2, q2[7]
-; CHECK-NEXT:    vmov.u16 r6, q2[5]
-; CHECK-NEXT:    vmov q3[3], q3[1], r6, r2
+; CHECK-NEXT:    adc.w r6, r12, r2
+; CHECK-NEXT:    vmov r2, s14
+; CHECK-NEXT:    adds.w r12, r3, r2
+; CHECK-NEXT:    vmov.s8 r2, q1[12]
+; CHECK-NEXT:    adc.w lr, r6, r5
+; CHECK-NEXT:    vmov.u16 r6, q2[6]
+; CHECK-NEXT:    vmov.u16 r5, q2[4]
+; CHECK-NEXT:    vmov.s8 r3, q0[12]
+; CHECK-NEXT:    vmov q3[2], q3[0], r5, r6
+; CHECK-NEXT:    vmov.u16 r6, q2[7]
+; CHECK-NEXT:    vmov.u16 r5, q2[5]
+; CHECK-NEXT:    smull r2, r3, r3, r2
+; CHECK-NEXT:    vmov q3[3], q3[1], r5, r6
 ; CHECK-NEXT:    vcmp.i32 ne, q3, zr
-; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r5, r2, #1
-; CHECK-NEXT:    ubfx r6, r2, #4, #1
+; CHECK-NEXT:    vmrs r6, p0
+; CHECK-NEXT:    and r4, r6, #1
+; CHECK-NEXT:    ubfx r5, r6, #4, #1
+; CHECK-NEXT:    rsbs r4, r4, #0
 ; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r6, r6, #0
-; CHECK-NEXT:    vmov q2[2], q2[0], r5, r6
-; CHECK-NEXT:    vmov q2[3], q2[1], r5, r6
-; CHECK-NEXT:    vmov.u8 r6, q1[13]
-; CHECK-NEXT:    vmov.u8 r5, q0[13]
-; CHECK-NEXT:    sxtb r6, r6
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r6, r5, r5, r6
-; CHECK-NEXT:    vmov q3[2], q3[0], r3, r6
-; CHECK-NEXT:    vmov q3[3], q3[1], r4, r5
+; CHECK-NEXT:    vmov q2[2], q2[0], r4, r5
+; CHECK-NEXT:    vmov q2[3], q2[1], r4, r5
+; CHECK-NEXT:    vmov.s8 r5, q1[13]
+; CHECK-NEXT:    vmov.s8 r4, q0[13]
+; CHECK-NEXT:    smull r5, r4, r4, r5
+; CHECK-NEXT:    vmov q3[2], q3[0], r2, r5
+; CHECK-NEXT:    vmov q3[3], q3[1], r3, r4
 ; CHECK-NEXT:    vand q2, q3, q2
-; CHECK-NEXT:    vmov r4, s8
-; CHECK-NEXT:    vmov r3, s9
-; CHECK-NEXT:    vmov r5, s11
-; CHECK-NEXT:    adds.w r6, r12, r4
+; CHECK-NEXT:    vmov r3, s8
+; CHECK-NEXT:    vmov r2, s9
 ; CHECK-NEXT:    vmov r4, s10
-; CHECK-NEXT:    adc.w r3, r3, lr
-; CHECK-NEXT:    adds r6, r6, r4
-; CHECK-NEXT:    vmov.u8 r4, q1[14]
-; CHECK-NEXT:    adc.w r12, r3, r5
-; CHECK-NEXT:    ubfx r5, r2, #12, #1
-; CHECK-NEXT:    ubfx r2, r2, #8, #1
+; CHECK-NEXT:    vmov r5, s11
+; CHECK-NEXT:    adds.w r3, r3, r12
+; CHECK-NEXT:    adc.w r2, r2, lr
+; CHECK-NEXT:    adds r3, r3, r4
+; CHECK-NEXT:    vmov.s8 r4, q1[14]
+; CHECK-NEXT:    adc.w r12, r2, r5
+; CHECK-NEXT:    ubfx r5, r6, #12, #1
+; CHECK-NEXT:    ubfx r6, r6, #8, #1
 ; CHECK-NEXT:    rsbs r5, r5, #0
-; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmov.u8 r3, q0[14]
-; CHECK-NEXT:    vmov q2[2], q2[0], r2, r5
-; CHECK-NEXT:    sxtb r4, r4
-; CHECK-NEXT:    vmov q2[3], q2[1], r2, r5
-; CHECK-NEXT:    vmov.u8 r2, q1[15]
-; CHECK-NEXT:    vmov.u8 r5, q0[15]
-; CHECK-NEXT:    sxtb r3, r3
-; CHECK-NEXT:    sxtb r2, r2
-; CHECK-NEXT:    sxtb r5, r5
-; CHECK-NEXT:    smull r2, r5, r5, r2
-; CHECK-NEXT:    smull r3, r4, r3, r4
-; CHECK-NEXT:    vmov q0[2], q0[0], r3, r2
+; CHECK-NEXT:    rsbs r6, r6, #0
+; CHECK-NEXT:    vmov.s8 r2, q0[14]
+; CHECK-NEXT:    vmov q2[2], q2[0], r6, r5
+; CHECK-NEXT:    smull r2, r4, r2, r4
+; CHECK-NEXT:    vmov q2[3], q2[1], r6, r5
+; CHECK-NEXT:    vmov.s8 r6, q1[15]
+; CHECK-NEXT:    vmov.s8 r5, q0[15]
+; CHECK-NEXT:    smull r6, r5, r5, r6
+; CHECK-NEXT:    vmov q0[2], q0[0], r2, r6
 ; CHECK-NEXT:    vmov q0[3], q0[1], r4, r5
 ; CHECK-NEXT:    vand q0, q0, q2
-; CHECK-NEXT:    vmov r3, s0
+; CHECK-NEXT:    vmov r6, s0
 ; CHECK-NEXT:    vmov r2, s1
 ; CHECK-NEXT:    vmov r5, s2
 ; CHECK-NEXT:    adds r3, r3, r6
 ; CHECK-NEXT:    vmov r6, s3
 ; CHECK-NEXT:    adc.w r2, r2, r12
 ; CHECK-NEXT:    adds r3, r3, r5
 ; CHECK-NEXT:    adcs r2, r6
 ; CHECK-NEXT:    adds r0, r0, r3