[SVE] Add ISel pattern for addvl

[c-rhodes]

Rebased. Committed update_llc_test_checks.py changes separately to reduce the diff (thanks for suggestion @sdesmalen).

[cameron.mcinally]

LGTM

I'm assuming scheduling the new addvls closer to their uses is a register pressure win?

[c-rhodes]

In D94504#2494181, @cameron.mcinally wrote:

LGTM

I'm assuming scheduling the new addvls closer to their uses is a register pressure win?

Thanks for reviewing. I didn't anticipate that reordering but yeah I would think so.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let AddedComplexity = 5 in {
     def : Pat<(vscale (sve_cntw_imm i32:$imm)), (CNTW_XPiI 31, $imm)>;
     def : Pat<(vscale (sve_cntd_imm i32:$imm)), (CNTD_XPiI 31, $imm)>;
 
     def : Pat<(vscale (sve_cnth_imm_neg i32:$imm)), (SUBXrs XZR, (CNTH_XPiI 31, $imm), 0)>;
     def : Pat<(vscale (sve_cntw_imm_neg i32:$imm)), (SUBXrs XZR, (CNTW_XPiI 31, $imm), 0)>;
     def : Pat<(vscale (sve_cntd_imm_neg i32:$imm)), (SUBXrs XZR, (CNTD_XPiI 31, $imm), 0)>;
   }
 
+  def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+            (ADDVL_XXI GPR64:$op, $imm)>;
+
   // FIXME: BigEndian requires an additional REV instruction to satisfy the
   // constraint that none of the bits change when stored to memory as one
   // type, and and reloaded as another type.
   let Predicates = [IsLE] in {
     def : Pat<(nxv16i8 (bitconvert (nxv8i16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
     def : Pat<(nxv16i8 (bitconvert (nxv4i32 ZPR:$src))), (nxv16i8 ZPR:$src)>;
     def : Pat<(nxv16i8 (bitconvert (nxv2i64 ZPR:$src))), (nxv16i8 ZPR:$src)>;
     def : Pat<(nxv16i8 (bitconvert (nxv8f16 ZPR:$src))), (nxv16i8 ZPR:$src)>;

llvm/test/CodeGen/AArch64/split-vector-insert.ll

 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    cmp x8, #0 // =0
 ; CHECK-NEXT:    csel x10, x8, xzr, lo
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    lsl x10, x10, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str q1, [x9, x10]
-; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    mov w9, #2
 ; CHECK-NEXT:    cmp x8, #2 // =2
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    str q2, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    mov w9, #4
 ; CHECK-NEXT:    cmp x8, #4 // =4
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    str q3, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #2, mul vl]
 ; CHECK-NEXT:    mov w9, #6
 ; CHECK-NEXT:    cmp x8, #6 // =6
 ; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    lsl x8, x8, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    str q4, [x10, x8]
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> %a, <8 x i64> %b, i64 0)

 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    cmp x8, #0 // =0
 ; CHECK-NEXT:    csel x10, x8, xzr, lo
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    lsl x10, x10, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str q1, [x9, x10]
-; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    mov w9, #2
 ; CHECK-NEXT:    cmp x8, #2 // =2
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    str q2, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    mov w9, #4
 ; CHECK-NEXT:    cmp x8, #4 // =4
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    str q3, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #2, mul vl]
 ; CHECK-NEXT:    mov w9, #6
 ; CHECK-NEXT:    cmp x8, #6 // =6
 ; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    lsl x8, x8, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    str q4, [x10, x8]
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0)
   ret <vscale x 2 x double> %r
 }

llvm/test/CodeGen/AArch64/sve-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 define <vscale x 2 x i64>* @scalar_of_scalable_1(<vscale x 2 x i64>* %base) {
 ; CHECK-LABEL: scalar_of_scalable_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #4
-; CHECK-NEXT:    add x0, x0, x8
+; CHECK-NEXT:    addvl x0, x0, #4
 ; CHECK-NEXT:    ret
   %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 4
   ret <vscale x 2 x i64>* %d
 }
 
 define <vscale x 2 x i64>* @scalar_of_scalable_2(<vscale x 2 x i64>* %base, i64 %offset) {
 ; CHECK-LABEL: scalar_of_scalable_2:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 ; Range testing for the immediate in the reg+imm(mulvl) addressing
 ; mode is done only for one instruction. The rest of the instrucions
 ; test only one immediate value in bound.
 
 define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %a)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_out_of_lower_bound:
-; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #-9
-; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT:  ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -9
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_lower_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -8
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_inbound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_inbound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_upper_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_out_of_upper_bound:
-; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #8
-; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT:  ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 8
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base_scalar)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_h:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a)
   %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
 }
 
 define <vscale x 8 x i16> @ldnf1b_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_h_inbound:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
   %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base_scalar)
   %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
 }
 
 define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_h:
-; CHECK: ldnf1sb { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a)
   %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
 }
 
 define <vscale x 8 x i16> @ldnf1sb_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_h_inbound:
-; CHECK: ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
   %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %base_scalar)
   %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
 }
 
 define <vscale x 8 x i16> @ldnf1h(<vscale x 8 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16(<vscale x 8 x i1> %pg, i16* %a)
   ret <vscale x 8 x i16> %load
 }
 
 define <vscale x 8 x i16> @ldnf1h_inbound(<vscale x 8 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 8 x i16>*
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x i16>* %base to i16*
   %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16(<vscale x 8 x i1> %pg, i16* %base_scalar)
   ret <vscale x 8 x i16> %load
 }
 
 define <vscale x 8 x half> @ldnf1h_f16(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldnf1h_f16:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16(<vscale x 8 x i1> %pg, half* %a)
   ret <vscale x 8 x half> %load
 }
 
 define <vscale x 8 x bfloat> @ldnf1h_bf16(<vscale x 8 x i1> %pg, bfloat* %a) #0 {
 ; CHECK-LABEL: ldnf1h_bf16:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnf1.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %a)
   ret <vscale x 8 x bfloat> %load
 }
 
 define <vscale x 8 x half> @ldnf1h_f16_inbound(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldnf1h_f16_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast half* %a to <vscale x 8 x half>*
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x half>* %base to half*
   %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16(<vscale x 8 x i1> %pg, half* %base_scalar)
   ret <vscale x 8 x half> %load
 }
 
 define <vscale x 8 x bfloat> @ldnf1h_bf16_inbound(<vscale x 8 x i1> %pg, bfloat* %a) #0 {
 ; CHECK-LABEL: ldnf1h_bf16_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast bfloat* %a to <vscale x 8 x bfloat>*
   %base = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x bfloat>* %base to bfloat*
   %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnf1.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %base_scalar)
   ret <vscale x 8 x bfloat> %load
 }
 
 define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_s:
-; CHECK: ldnf1b { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a)
   %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1b_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_s_inbound:
-; CHECK: ldnf1b { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
   %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base_scalar)
   %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_s:
-; CHECK: ldnf1sb { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a)
   %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1sb_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_s_inbound:
-; CHECK: ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
   %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %base_scalar)
   %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_s:
-; CHECK: ldnf1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a)
   %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1h_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_s_inbound:
-; CHECK: ldnf1h { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
   %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base_scalar)
   %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_s:
-; CHECK: ldnf1sh { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a)
   %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1sh_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_s_inbound:
-; CHECK: ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
   %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %base_scalar)
   %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 4 x i32> @ldnf1w(<vscale x 4 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32(<vscale x 4 x i1> %pg, i32* %a)
   ret <vscale x 4 x i32> %load
 }
 
 define <vscale x 4 x i32> @ldnf1w_inbound(<vscale x 4 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_inbound:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 4 x i32>*
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i32>* %base to i32*
   %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32(<vscale x 4 x i1> %pg, i32* %base_scalar)
   ret <vscale x 4 x i32> %load
 }
 
 define <vscale x 4 x float> @ldnf1w_f32(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldnf1w_f32:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32(<vscale x 4 x i1> %pg, float* %a)
   ret <vscale x 4 x float> %load
 }
 
 define <vscale x 4 x float> @ldnf1w_f32_inbound(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldnf1w_f32_inbound:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast float* %a to <vscale x 4 x float>*
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x float>* %base to float*
   %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32(<vscale x 4 x i1> %pg, float* %base_scalar)
   ret <vscale x 4 x float> %load
 }
 
 define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_d:
-; CHECK: ldnf1b { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a)
   %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1b_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_d_inbound:
-; CHECK: ldnf1b { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
   %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base_scalar)
   %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_d:
-; CHECK: ldnf1sb { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a)
   %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sb_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_d_inbound:
-; CHECK: ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
   %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %base_scalar)
   %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_d:
-; CHECK: ldnf1h { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a)
   %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1h_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_d_inbound:
-; CHECK: ldnf1h { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
   %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base_scalar)
   %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_d:
-; CHECK: ldnf1sh { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a)
   %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sh_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_d_inbound:
-; CHECK: ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
   %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %base_scalar)
   %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_d:
-; CHECK: ldnf1w { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a)
   %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1w_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_d_inbound:
-; CHECK: ldnf1w { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
   %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base_scalar)
   %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1sw_d:
-; CHECK: ldnf1sw { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sw { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a)
   %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1sw_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1sw_d_inbound:
-; CHECK: ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
   %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %base_scalar)
   %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 2 x i64> @ldnf1d(<vscale x 2 x i1> %pg, i64* %a) {
 ; CHECK-LABEL: ldnf1d:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64(<vscale x 2 x i1> %pg, i64* %a)
   ret <vscale x 2 x i64> %load
 }
 
 define <vscale x 2 x i64> @ldnf1d_inbound(<vscale x 2 x i1> %pg, i64* %a) {
 ; CHECK-LABEL: ldnf1d_inbound:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i64* %a to <vscale x 2 x i64>*
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 2 x i64>* %base to i64*
   %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64(<vscale x 2 x i1> %pg, i64* %base_scalar)
   ret <vscale x 2 x i64> %load
 }
 
 define <vscale x 2 x double> @ldnf1d_f64(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldnf1d_f64:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64(<vscale x 2 x i1> %pg, double* %a)
   ret <vscale x 2 x double> %load
 }
 
 define <vscale x 2 x double> @ldnf1d_f64_inbound(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldnf1d_f64_inbound:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast double* %a to <vscale x 2 x double>*
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 2 x double>* %base to double*
   %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64(<vscale x 2 x i1> %pg, double* %base_scalar)
   ret <vscale x 2 x double> %load
 }
 
 declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1>, i8*)

llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll

; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
   %load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ld1b_out_of_upper_bound(<vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: ld1b_out_of_upper_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #8
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #8
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
   %load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ld1b_out_of_lower_bound(<vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: ld1b_out_of_lower_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #-9
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #-9
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
   %load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
   ret <vscale x 16 x i8> %load
 }
 

llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll

-; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 ; Range checks: for all the instruction tested in this file, the
 ; immediate must be within the range [-8, 7] (4-bit immediate). Out of
 ; range values are tested only in one case (following). Valid values
 ; are tested all through the rest of the file.
 
 define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: imm_out_of_range:
-; CHECK-NEXT: rdvl x8, #8
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}]
-; CHECK-NEXT: rdvl x8, #-9
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8
   %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i64> undef)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -9
   call void @llvm.masked.store.nxv2i64(<vscale x 2 x i64> %data,
                                        <vscale x 2 x i64>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 ; 2-lane contiguous load/stores
 
 define void @test_masked_ldst_sv2i8(<vscale x 2 x i8> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1b { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -8
   %data = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 2 x i1> %mask,
                                                           <vscale x 2 x i8> undef)
   %base_store = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8> * %base, i64 -7
   call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %data,
                                       <vscale x 2 x i8>* %base_store,
                                       i32 1,
                                       <vscale x 2 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv2i16(<vscale x 2 x i16> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i16:
-; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 -8
   %data = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i16> undef)
   %base_store = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16> * %base, i64 -7
   call void @llvm.masked.store.nxv2i16(<vscale x 2 x i16> %data,
                                        <vscale x 2 x i16>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 
 define void @test_masked_ldst_sv2i32(<vscale x 2 x i32> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i32:
-; CHECK-NEXT: ld1sw { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sw { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -8
   %data = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i32> undef)
   %base_store = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32> * %base, i64 -7
   call void @llvm.masked.store.nxv2i32(<vscale x 2 x i32> %data,
                                        <vscale x 2 x i32>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i64:
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8
   %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i64> undef)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -7
   call void @llvm.masked.store.nxv2i64(<vscale x 2 x i64> %data,
                                        <vscale x 2 x i64>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv2f16(<vscale x 2 x half> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x half>, <vscale x 2 x half>* %base, i64 -8
   %data = call <vscale x 2 x half> @llvm.masked.load.nxv2f16(<vscale x 2 x half>* %base_load,
                                                              i32 1,
                                                              <vscale x 2 x i1> %mask,
                                                              <vscale x 2 x half> undef)
   %base_store = getelementptr <vscale x 2 x half>, <vscale x 2 x half> * %base, i64 -7
   call void @llvm.masked.store.nxv2f16(<vscale x 2 x half> %data,
                                        <vscale x 2 x half>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 
 define void @test_masked_ldst_sv2f32(<vscale x 2 x float> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x float>, <vscale x 2 x float>* %base, i64 -8
   %data = call <vscale x 2 x float> @llvm.masked.load.nxv2f32(<vscale x 2 x float>* %base_load,
                                                               i32 1,
                                                               <vscale x 2 x i1> %mask,
                                                               <vscale x 2 x float> undef)
   %base_store = getelementptr <vscale x 2 x float>, <vscale x 2 x float> * %base, i64 -7
   call void @llvm.masked.store.nxv2f32(<vscale x 2 x float> %data,
                                        <vscale x 2 x float>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f64:
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl]
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0, #-6, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #-5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6
   %data = call <vscale x 2 x double> @llvm.masked.load.nxv2f64(<vscale x 2 x double>* %base_load,
                                                                i32 1,
                                                                <vscale x 2 x i1> %mask,
                                                                <vscale x 2 x double> undef)
   %base_store = getelementptr <vscale x 2 x double>, <vscale x 2 x double> * %base, i64 -5
   call void @llvm.masked.store.nxv2f64(<vscale x 2 x double> %data,
                                        <vscale x 2 x double>* %base_store,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 ; 2-lane zero/sign extended contiguous loads.
 
 define <vscale x 2 x i64> @masked_zload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i8_to_sv2i64:
-; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.d }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -4
   %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 2 x i1> %mask,
                                                           <vscale x 2 x i8> undef)
   %ext = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 define <vscale x 2 x i64> @masked_sload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i8_to_sv2i64:
-; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.d }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -3
   %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 2 x i1> %mask,
                                                           <vscale x 2 x i8> undef)
   %ext = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 define <vscale x 2 x i64> @masked_zload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i16_to_sv2i64:
-; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 1
   %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i16> undef)
   %ext = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 define <vscale x 2 x i64> @masked_sload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i16_to_sv2i64:
-; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.d }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 2
   %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i16> undef)
   %ext = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 define <vscale x 2 x i64> @masked_zload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i32_to_sv2i64:
-; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, #-2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, #-2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -2
   %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i32> undef)
   %ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 define <vscale x 2 x i64> @masked_sload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i32_to_sv2i64:
-; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sw { z0.d }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -1
   %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
                                                             <vscale x 2 x i1> %mask,
                                                             <vscale x 2 x i32> undef)
   %ext = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %ext
 }
 
 ; 2-lane truncating contiguous stores.
 
 define void @masked_trunc_store_sv2i64_to_sv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i8:
-; CHECK-NEXT: st1b { z0.d }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.d }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 3
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
   call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %trunc,
                                       <vscale x 2 x i8> *%base_load,
                                       i32 1,
                                       <vscale x 2 x i1> %mask)
   ret void
 }
 
 
 define void @masked_trunc_store_sv2i64_to_sv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i16:
-; CHECK-NEXT: st1h { z0.d }, p0, [x0, #4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 4
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
   call void @llvm.masked.store.nxv2i16(<vscale x 2 x i16> %trunc,
                                        <vscale x 2 x i16> *%base_load,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 define void @masked_trunc_store_sv2i64_to_sv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i32:
-; CHECK-NEXT: st1w { z0.d }, p0, [x0, #5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 5
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
   call void @llvm.masked.store.nxv2i32(<vscale x 2 x i32> %trunc,
                                        <vscale x 2 x i32> *%base_load,
                                        i32 1,
                                        <vscale x 2 x i1> %mask)
   ret void
 }
 
 ; 4-lane contiguous load/stores.
 
 define void @test_masked_ldst_sv4i8(<vscale x 4 x i8> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1b { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -1
   %data = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 4 x i1> %mask,
                                                           <vscale x 4 x i8> undef)
   %base_store = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8> * %base, i64 2
   call void @llvm.masked.store.nxv4i8(<vscale x 4 x i8> %data,
                                       <vscale x 4 x i8>* %base_store,
                                       i32 1,
                                       <vscale x 4 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv4i16(<vscale x 4 x i16> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i16:
-; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 -1
   %data = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 4 x i1> %mask,
                                                             <vscale x 4 x i16> undef)
   %base_store = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16> * %base, i64 2
   call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %data,
                                        <vscale x 4 x i16>* %base_store,
                                        i32 1,
                                        <vscale x 4 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6
   %data = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(<vscale x 4 x i32>* %base_load,
                                                             i32 1,
                                                             <vscale x 4 x i1> %mask,
                                                             <vscale x 4 x i32> undef)
   %base_store = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32> * %base, i64 7
   call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %data,
                                        <vscale x 4 x i32>* %base_store,
                                        i32 1,
                                        <vscale x 4 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv4f16(<vscale x 4 x half> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x half>, <vscale x 4 x half>* %base, i64 -1
   %data = call <vscale x 4 x half> @llvm.masked.load.nxv4f16(<vscale x 4 x half>* %base_load,
                                                              i32 1,
                                                              <vscale x 4 x i1> %mask,
                                                              <vscale x 4 x half> undef)
   %base_store = getelementptr <vscale x 4 x half>, <vscale x 4 x half> * %base, i64 2
   call void @llvm.masked.store.nxv4f16(<vscale x 4 x half> %data,
                                        <vscale x 4 x half>* %base_store,
                                        i32 1,
                                        <vscale x 4 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1
   %data = call <vscale x 4 x float> @llvm.masked.load.nxv4f32(<vscale x 4 x float>* %base_load,
                                                               i32 1,
                                                               <vscale x 4 x i1> %mask,
                                                               <vscale x 4 x float> undef)
   %base_store = getelementptr <vscale x 4 x float>, <vscale x 4 x float> * %base, i64 2
   call void @llvm.masked.store.nxv4f32(<vscale x 4 x float> %data,
                                        <vscale x 4 x float>* %base_store,
                                        i32 1,
                                        <vscale x 4 x i1> %mask)
   ret void
 }
 
 ; 4-lane zero/sign extended contiguous loads.
 
 define <vscale x 4 x i32> @masked_zload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv4i8_to_sv4i32:
-; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.s }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -4
   %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 4 x i1> %mask,
                                                           <vscale x 4 x i8> undef)
   %ext = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %ext
 }
 
 define <vscale x 4 x i32> @masked_sload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv4i8_to_sv4i32:
-; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.s }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -3
   %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 4 x i1> %mask,
                                                           <vscale x 4 x i8> undef)
   %ext = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %ext
 }
 
 define <vscale x 4 x i32> @masked_zload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv4i16_to_sv4i32:
-; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 1
   %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 4 x i1> %mask,
                                                             <vscale x 4 x i16> undef)
   %ext = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %ext
 }
 
 define <vscale x 4 x i32> @masked_sload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv4i16_to_sv4i32:
-; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.s }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 2
   %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 4 x i1> %mask,
                                                             <vscale x 4 x i16> undef)
   %ext = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %ext
 }
 
 ; 4-lane truncating contiguous stores.
 
 define void @masked_trunc_store_sv4i32_to_sv4i8(<vscale x 4 x i32> %val, <vscale x 4 x i8> *%base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i8:
-; CHECK-NEXT: st1b { z0.s }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.s }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 3
   %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i8>
   call void @llvm.masked.store.nxv4i8(<vscale x 4 x i8> %trunc,
                                       <vscale x 4 x i8> *%base_load,
                                       i32 1,
                                       <vscale x 4 x i1> %mask)
   ret void
 }
 
 
 define void @masked_trunc_store_sv4i32_to_sv4i16(<vscale x 4 x i32> %val, <vscale x 4 x i16> *%base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i16:
-; CHECK-NEXT: st1h { z0.s }, p0, [x0, #4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 4
   %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i16>
   call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %trunc,
                                        <vscale x 4 x i16> *%base_load,
                                        i32 1,
                                        <vscale x 4 x i1> %mask)
   ret void
 }
 
 ; 8-lane contiguous load/stores.
 
 define void @test_masked_ldst_sv8i8(<vscale x 8 x i8> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1b { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 6
   %data = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 8 x i1> %mask,
                                                           <vscale x 8 x i8> undef)
   %base_store = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8> * %base, i64 7
   call void @llvm.masked.store.nxv8i8(<vscale x 8 x i8> %data,
                                       <vscale x 8 x i8>* %base_store,
                                       i32 1,
                                       <vscale x 8 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6
   %data = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(<vscale x 8 x i16>* %base_load,
                                                             i32 1,
                                                             <vscale x 8 x i1> %mask,
                                                             <vscale x 8 x i16> undef)
   %base_store = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16> * %base, i64 7
   call void @llvm.masked.store.nxv8i16(<vscale x 8 x i16> %data,
                                        <vscale x 8 x i16>* %base_store,
                                        i32 1,
                                        <vscale x 8 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1
   %data = call <vscale x 8 x half> @llvm.masked.load.nxv8f16(<vscale x 8 x half>* %base_load,
                                                              i32 1,
                                                              <vscale x 8 x i1> %mask,
                                                              <vscale x 8 x half> undef)
   %base_store = getelementptr <vscale x 8 x half>, <vscale x 8 x half> * %base, i64 2
   call void @llvm.masked.store.nxv8f16(<vscale x 8 x half> %data,
                                        <vscale x 8 x half>* %base_store,
                                        i32 1,
                                        <vscale x 8 x i1> %mask)
   ret void
 }
 
 define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 {
 ; CHECK-LABEL: test_masked_ldst_sv8bf16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1
   %data = call <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(<vscale x 8 x bfloat>* %base_load,
                                                                 i32 1,
                                                                 <vscale x 8 x i1> %mask,
                                                                 <vscale x 8 x bfloat> undef)
   %base_store = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat> * %base, i64 2
   call void @llvm.masked.store.nxv8bf16(<vscale x 8 x bfloat> %data,
                                         <vscale x 8 x bfloat>* %base_store,
                                         i32 1,
                                         <vscale x 8 x i1> %mask)
   ret void
 }
 
 ; 8-lane zero/sign extended contiguous loads.
 
 define <vscale x 8 x i16> @masked_zload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv8i8_to_sv8i16:
-; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.h }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -4
   %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 8 x i1> %mask,
                                                           <vscale x 8 x i8> undef)
   %ext = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %ext
 }
 
 define <vscale x 8 x i16> @masked_sload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv8i8_to_sv8i16:
-; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.h }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -3
   %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
                                                           <vscale x 8 x i1> %mask,
                                                           <vscale x 8 x i8> undef)
   %ext = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %ext
 }
 
 ; 8-lane truncating contiguous stores.
 
 define void @masked_trunc_store_sv8i16_to_sv8i8(<vscale x 8 x i16> %val, <vscale x 8 x i8> *%base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv8i16_to_sv8i8:
-; CHECK-NEXT: st1b { z0.h }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.h }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 3
   %trunc = trunc <vscale x 8 x i16> %val to <vscale x 8 x i8>
   call void @llvm.masked.store.nxv8i8(<vscale x 8 x i8> %trunc,
                                       <vscale x 8 x i8> *%base_load,
                                       i32 1,
                                       <vscale x 8 x i1> %mask)
   ret void
 }
 
 ; 16-lane contiguous load/stores.
 
 define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv16i8:
-; CHECK-NEXT: ld1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].b }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1b { z0.b }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6
   %data = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(<vscale x 16 x i8>* %base_load,
                                                             i32 1,
                                                             <vscale x 16 x i1> %mask,
                                                             <vscale x 16 x i8> undef)
   %base_store = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8> * %base, i64 7
   call void @llvm.masked.store.nxv16i8(<vscale x 16 x i8> %data,
                                        <vscale x 16 x i8>* %base_store,

llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll

-; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 ; Range checks: for all the instruction tested in this file, the
 ; immediate must be within the range [-8, 7] (4-bit immediate). Out of
 ; range values are tested only in one case (following). Valid values
 ; are tested all through the rest of the file.
 
 define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: imm_out_of_range:
-; CHECK-NEXT: rdvl x8, #8
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}]
-; CHECK-NEXT: rdvl x8, #-9
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x8]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8
   %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
                                                                   i64* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -9
   %base_store_bc = bitcast <vscale x 2 x i64>* %base_store to i64*
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %mask,
                                             i64* %base_store_bc)
   ret void
 }
 
 ; 2-lane non-temporal load/stores
 
 
 define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i64:
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8
   %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
                                                                   i64* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64> * %base, i64 -7
   %base_store_bc = bitcast <vscale x 2 x i64>* %base_store to i64*
   call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
                                             <vscale x 2 x i1> %mask,
                                             i64* %base_store_bc)
   ret void
 }
 
 define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f64:
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl]
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x0, #-6, mul vl]
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x0, #-5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6
   %base_load_bc = bitcast <vscale x 2 x double>* %base_load to double*
   %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
                                                                     double* %base_load_bc)
   %base_store = getelementptr <vscale x 2 x double>, <vscale x 2 x double> * %base, i64 -5
   %base_store_bc = bitcast <vscale x 2 x double>* %base_store to double*
   call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
                                             <vscale x 2 x i1> %mask,
                                             double* %base_store_bc)
   ret void
 }
 
 ; 4-lane non-temporal load/stores.
 
 define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i32:
-; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1w { z0.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1w { z0.s }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6
   %base_load_bc = bitcast <vscale x 4 x i32>* %base_load to i32*
   %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
                                                                   i32* %base_load_bc)
   %base_store = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32> * %base, i64 7
   %base_store_bc = bitcast <vscale x 4 x i32>* %base_store to i32*
   call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
                                             <vscale x 4 x i1> %mask,
                                             i32* %base_store_bc)
   ret void
 }
 
 define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f32:
-; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1w { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1w { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 4 x float>* %base_load to float*
   %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
                                                                     float* %base_load_bc)
   %base_store = getelementptr <vscale x 4 x float>, <vscale x 4 x float> * %base, i64 2
   %base_store_bc = bitcast <vscale x 4 x float>* %base_store to float*
   call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
                                             <vscale x 4 x i1> %mask,
                                             float* %base_store_bc)
   ret void
 }
 
 
 ; 8-lane non-temporal load/stores.
 
 define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6
   %base_load_bc = bitcast <vscale x 8 x i16>* %base_load to i16*
   %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
                                                                   i16* %base_load_bc)
   %base_store = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16> * %base, i64 7
   %base_store_bc = bitcast <vscale x 8 x i16>* %base_store to i16*
   call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
                                             <vscale x 8 x i1> %mask,
                                             i16* %base_store_bc)
   ret void
 }
 
 define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8f16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 8 x half>* %base_load to half*
   %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
                                                                    half* %base_load_bc)
   %base_store = getelementptr <vscale x 8 x half>, <vscale x 8 x half> * %base, i64 2
   %base_store_bc = bitcast <vscale x 8 x half>* %base_store to half*
   call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
                                             <vscale x 8 x i1> %mask,
                                             half* %base_store_bc)
   ret void
 }
 
 define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 {
 ; CHECK-LABEL: test_masked_ldst_sv8bf16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 8 x bfloat>* %base_load to bfloat*
   %data = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1> %mask,
                                                                       bfloat* %base_load_bc)
   %base_store = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat> * %base, i64 2
   %base_store_bc = bitcast <vscale x 8 x bfloat>* %base_store to bfloat*
   call void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat> %data,
                                              <vscale x 8 x i1> %mask,
                                              bfloat* %base_store_bc)
   ret void
 }
 
 ; 16-lane non-temporal load/stores.
 
 define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv16i8:
-; CHECK-NEXT: ldnt1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1b { z0.b }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1b { z0.b }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6
   %base_load_bc = bitcast <vscale x 16 x i8>* %base_load to i8*
   %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
                                                                   i8* %base_load_bc)
   %base_store = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8> * %base, i64 7
   %base_store_bc = bitcast <vscale x 16 x i8>* %base_store to i8*
   call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
                                             <vscale x 16 x i1> %mask,

llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
   store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
   ret void
 }
 
 define void @st1b_out_of_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: st1b_out_of_upper_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #8
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #8
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
   store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
   ret void
 }
 
 define void @st1b_out_of_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: st1b_out_of_lower_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #-9
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #-9
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
   store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
   ret void
 }