[PowerPC] [NFC] Add AIX triple to some regression tests

[qiucf]

Summary

As part of the effort to improve AIX support, regression test coverage misses quite a lot for AIX subtarget. This patch adds AIX triple to those don't need extra change, and we can cover more cases in following commits.

[steven.zhang]

It surprises to me that you didn't see the difference between LE and AIX, which doesn't make sense to me. Please double confirm to see if there is any conflict when update the test with the script.

[qiucf]

Rebase after rG6175fcf01f17e0bd1155aaaba977b9baa88ee61d and rG7200d2cf0891ef56607fd0336029b33bd4097eed

[qiucf]

In D94159#2483878, @steven.zhang wrote:

It surprises to me that you didn't see the difference between LE and AIX, which doesn't make sense to me. Please double confirm to see if there is any conflict when update the test with the script.

I pre-committed a change updating tests marked auto-generated (except those have extra combining/scheduling log check) and rebased this patch. So these cases won't change again after running the script. I plan this patch as first step to improve AIX test coverage, so this includes only cases which don't need extra prefix. And I'll add others in following commits.

[steven.zhang]

Thank you for doing this. LGTM now.

llvm/test/CodeGen/PowerPC/and-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
 ; mask 0xFFFFFFFE
 define i32 @test1(i32 %a) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 0, 30
 ; CHECK-NEXT:    blr
   %and = and i32 %a, -2

llvm/test/CodeGen/PowerPC/bool-math.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -verify-machineinstrs | FileCheck %s
 
 define i32 @sub_zext_cmp_mask_same_size_result(i32 %x) {
 ; CHECK-LABEL: sub_zext_cmp_mask_same_size_result:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrldi 3, 3, 63
 ; CHECK-NEXT:    ori 3, 3, 65508
 ; CHECK-NEXT:    oris 3, 3, 65535
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/bswap64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:   -mcpu=pwr9 -vec-extabi | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=NO-ALTIVEC
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:   -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=NO-ALTIVEC
 
 declare i64 @llvm.bswap.i64(i64)
 
 define i64 @bswap64(i64 %x) {
 ; CHECK-LABEL: bswap64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mtvsrdd 34, 3, 3
 ; CHECK-NEXT:    xxbrd 0, 34

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 | FileCheck %s
 
 define i64 @raw() {
 ; CHECK-LABEL: raw:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    darn 3, 2
 ; CHECK-NEXT:    blr
 entry:
   %0 = call i64 @llvm.ppc.darnraw()

llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
-target datalayout = "E-m:e-p:32:32-i64:64-n32"
-target triple = "powerpc-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -mtriple powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 -vec-extabi < %s | FileCheck %s
 
 ; Function Attrs: nounwind readnone
 define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpb 3, 4, 3
 ; CHECK-NEXT:    clrlwi 3, 3, 16
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/cmpb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mcpu pwr7 < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu pwr7 -vec-extabi < %s | FileCheck %s
 
 ; Function Attrs: nounwind readnone
 define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpb 3, 4, 3
 ; CHECK-NEXT:    clrldi 3, 3, 48
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/constant-combines.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu   -o - %s | FileCheck --check-prefix=BE %s
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -o - %s | FileCheck --check-prefix=BE %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - %s | FileCheck --check-prefix=LE %s
 
 define void @fold_constant_stores_loaddr(i8* %i8_ptr) {
 ; BE-LABEL: fold_constant_stores_loaddr:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    li 4, 0
 ; BE-NEXT:    std 4, 0(3)
 ; BE-NEXT:    li 4, -86

llvm/test/CodeGen/PowerPC/constants-i64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=ppc64 < %s | FileCheck %s
 
 ; Function Attrs: nounwind readnone
 define i64 @cn1() #0 {
 ; CHECK-LABEL: cn1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -1
 ; CHECK-NEXT:    rldic 3, 3, 0, 16
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/fdiv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi | FileCheck %s
 
 define dso_local float @foo_nosw(float %0, float %1) local_unnamed_addr {
 ; CHECK-LABEL: foo_nosw:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsdivsp 1, 1, 2
 ; CHECK-NEXT:    blr
   %3 = fdiv reassoc arcp nsz float %0, %1
   ret float %3

llvm/test/CodeGen/PowerPC/fma-assoc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast \
 ; RUN:   -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -fp-contract=fast \
+; RUN:   -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \
 ; RUN:   -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:   -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \
+; RUN:   -mcpu=pwr7 -vec-extabi | FileCheck -check-prefix=CHECK-VSX %s
 
 define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
 ; CHECK-LABEL: test_FMADD_ASSOC1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul 0, 3, 4
 ; CHECK-NEXT:    fmadd 0, 1, 2, 0
 ; CHECK-NEXT:    fadd 1, 0, 5
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/ftrunc-vec.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -verify-machineinstrs < %s | FileCheck %s
 
 define <4 x float> @truncf32(<4 x float> %a) #0 {
 ; CHECK-LABEL: truncf32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xvrspiz 34, 34
 ; CHECK-NEXT:    blr
   %t0 = fptosi <4 x float> %a to <4 x i32>
   %t1 = sitofp <4 x i32> %t0 to <4 x float>

llvm/test/CodeGen/PowerPC/hoist-logic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
 
 ; This is good - eliminate an op by hoisting logic.
 
 define i32 @lshr_or(i32 %x, i32 %y, i32 %z, i32* %p1, i32* %p2) {
 ; CHECK-LABEL: lshr_or:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    srw 3, 3, 5

llvm/test/CodeGen/PowerPC/inc-of-add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=ppc32-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC32
 ; RUN: llc < %s -mtriple=powerpc64-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
+; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64LE
 
 ; These two forms are equivalent:
 ;   sub %y, (xor %x, -1)
 ;   add (add %x, 1), %y
 ; Some targets may prefer one to the other.
 
 define i8 @scalar_i8(i8 %x, i8 %y) nounwind {

llvm/test/CodeGen/PowerPC/maddld.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefix=CHECK-P8
 
 define signext i64 @maddld64(i64 signext %a, i64 signext %b) {
 ; CHECK-P9-LABEL: maddld64:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    maddld 3, 4, 3, 3
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: maddld64:

llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
 ; RUN: | FileCheck --check-prefix=CHECK-LE %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mattr=+vsx < %s \
 ; RUN: | FileCheck --check-prefix=CHECK-BE %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mattr=+vsx \
+; RUN: -vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s \
 ; RUN: | FileCheck --check-prefix=CHECK-P9LE %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mcpu=pwr9 < %s \
 ; RUN: | FileCheck --check-prefix=CHECK-P9BE %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 \
+; RUN: -vec-extabi < %s | FileCheck --check-prefix=CHECK-BE %s
 
 define double @splat_swap(<2 x double> %x, <2 x double> %y) nounwind  {
 ; CHECK-LE-LABEL: splat_swap:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    xvadddp 0, 34, 35
 ; CHECK-LE-NEXT:    xvrdpic 0, 0
 ; CHECK-LE-NEXT:    xxswapd 1, 0
 ; CHECK-LE-NEXT:    xssubdp 1, 1, 0

llvm/test/CodeGen/PowerPC/mulli.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s
 
 define i64 @test1(i64 %x) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mulli 3, 3, 625
 ; CHECK-NEXT:    sldi 3, 3, 36
 ; CHECK-NEXT:    blr
   %y = mul i64 %x, 42949672960000

llvm/test/CodeGen/PowerPC/ori_imm32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
 
 define i64 @ori_test_a(i64 %a) {
 ; CHECK-LABEL: ori_test_a:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori 3, 3, 65535
 ; CHECK-NEXT:    oris 3, 3, 65535
 ; CHECK-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/ori_imm64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
 
 define i64 @ori_test_1(i64 %a) {
 ; CHECK-LABEL: ori_test_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -1
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %a, 18446744073709551615 ; 0xffffffffffffffff

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+popcntd < %s      | FileCheck %s --check-prefix=FAST
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+slow-popcntd < %s | FileCheck %s --check-prefix=SLOW
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mattr=+popcntd < %s      | FileCheck %s --check-prefix=FAST
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mattr=+slow-popcntd < %s | FileCheck %s --check-prefix=SLOW
 
 define i16 @zpop_i8_i16(i8 %x) {
 ; FAST-LABEL: zpop_i8_i16:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 56
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    blr
 ;

llvm/test/CodeGen/PowerPC/pr33093.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi < %s | FileCheck %s
 
 define zeroext i32 @ReverseBits(i32 zeroext %n) {
 ; CHECK-LABEL: ReverseBits:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    slwi 6, 3, 1
 ; CHECK-NEXT:    srwi 3, 3, 1

llvm/test/CodeGen/PowerPC/pr39478.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=CHECKLE
 ; RUN: llc < %s -mtriple=powerpc64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=CHECKBE
+; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -verify-machineinstrs | FileCheck %s --check-prefix=CHECKBE
 
 define void @pr39478(i64* %p64, i32* %p32) {
 ; CHECKLE-LABEL: pr39478:
 ; CHECKLE:       # %bb.0: # %entry
 ; CHECKLE-NEXT:    lbz 3, 4(3)
 ; CHECKLE-NEXT:    stb 3, 0(4)
 ; CHECKLE-NEXT:    blr
 ;

llvm/test/CodeGen/PowerPC/rotl-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
 
 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
 ; CHECK-LABEL: rotl32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlw 3, 3, 4
 ; CHECK-NEXT:    blr
   %shift.upgrd.1 = zext i8 %Amt to i32    ; <i32> [#uses=1]
   %B = shl i32 %A, %shift.upgrd.1   ; <i32> [#uses=1]

llvm/test/CodeGen/PowerPC/setcc-to-sub.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: < %s -vec-extabi | FileCheck %s
 
 %class.PB2 = type { [1 x i32], %class.PB1* }
 %class.PB1 = type { [1 x i32], i64, i64, i32 }
 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry

llvm/test/CodeGen/PowerPC/shift-cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s | FileCheck %s
-target datalayout = "e-m:e-i64:64-n32:64"
-target triple = "powerpc64le-unknown-linux-gnu"
+; RUN: llc -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
 
 define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp_variable_power_of_two:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srw 3, 3, 4
 ; CHECK-NEXT:    blr
   %shl = shl i32 1, %y
   %and = and i32 %x, %shl

llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -mtriple powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs -vec-extabi < %s | FileCheck %s
 
 define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
 ; CHECK-LABEL: test_l_v16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, 15
 ; CHECK-NEXT:    lvsl 3, 0, 3
 ; CHECK-NEXT:    lvx 2, 3, 4
 ; CHECK-NEXT:    lvx 4, 0, 3

llvm/test/CodeGen/PowerPC/vec_clz.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Check the vctlz* instructions that were added in P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
 
 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone
 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone
 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone
 
 define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone {
 ; CHECK-LABEL: test_v16i8:

llvm/test/CodeGen/PowerPC/vec_constants.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE
 
 define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
 ; BE-LABEL: test1:
 ; BE:       # %bb.0:
 ; BE-NEXT:    lxvw4x 0, 0, 3
 ; BE-NEXT:    vspltisb 2, -1
 ; BE-NEXT:    vslw 2, 2, 2

llvm/test/CodeGen/PowerPC/vec_revb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
 
 define <8 x i16> @testXXBRH(<8 x i16> %a) {
 ; CHECK-LABEL: testXXBRH:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxbrh 34, 34
 ; CHECK-NEXT:    blr
 

llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mattr=+power8-vector < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck -check-prefix=CHECK-PWR7 %s
 
 define void @VPKUDUM_unary(<2 x i64>* %A) {
 ; CHECK-LABEL: VPKUDUM_unary:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvw4x 34, 0, 3
 ; CHECK-NEXT:    vpkudum 2, 2, 2
 ; CHECK-NEXT:    stxvw4x 34, 0, 3
 ; CHECK-NEXT:    blr

llvm/test/CodeGen/PowerPC/vmladduhm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s
 define <8 x i16> @mul(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-LABEL: mul:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vxor 4, 4, 4
 ; CHECK-NEXT:    vmladduhm 2, 2, 3, 4
 ; CHECK-NEXT:    blr
 entry:
   %0 = mul <8 x i16> %m, %n