[RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instructions. Remove InstAliases that duplicate the asm strings in the pseudos.

[craig.topper]

Summary

The Pseudo class sets isCodeGenOnly=1 which causes the asm strings
in the pseudos to be ignored. I think this is why the aliases are
needed at all.

[frasercrmck]

Sorry, haven't felt able to review this as I don't get the original problem well enough. Because it looks to me like the aliases permitted matches, e.g. vmsgeu.vx $vd, $va, $rs1 which wasn't matching because it was unmasked? It's just that the comment says the "alias .. prevents matching" which throws me off as that's the opposite of what I thought they were for.

[craig.topper]

In D94024#2483898, @frasercrmck wrote:

Sorry, haven't felt able to review this as I don't get the original problem well enough. Because it looks to me like the aliases permitted matches, e.g. vmsgeu.vx $vd, $va, $rs1 which wasn't matching because it was unmasked? It's just that the comment says the "alias .. prevents matching" which throws me off as that's the opposite of what I thought they were for.

I think the comment referred specifically to the first two aliases. The VMaskOp on the other patterns is allowed to match as either or ", v0.t" as we normally use the same instruction for masked and unmasked. But in this case we only want VMaskOp to match ", v0.t" so we need an explicit match to another instruction for the no mask case to "prevent" the VMaskOp pattern from matching it.

This patch doesn't change how that works. We're just using the strings from the instructions now instead of aliases.

[frasercrmck]

Thanks for clarifying. LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def : InstAlias<"vmslt.vi $vd, $va, $imm$vm",
                  VMaskOp:$vm), 0>;
 def : InstAlias<"vmsgeu.vi $vd, $va, $imm$vm",
                 (VMSGTU_VI VR:$vd, VR:$va, simm5_plus1:$imm,
                  VMaskOp:$vm), 0>;
 def : InstAlias<"vmsge.vi $vd, $va, $imm$vm",
                 (VMSGT_VI VR:$vd, VR:$va, simm5_plus1:$imm,
                  VMaskOp:$vm), 0>;
 
-let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0 in {
 def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd),
                              (ins VR:$vs2, GPR:$rs1),
                              [], "vmsgeu.vx", "$vd, $vs2, $rs1">;
 def PseudoVMSGE_VX : Pseudo<(outs VR:$vd),
                             (ins VR:$vs2, GPR:$rs1),
                             [], "vmsge.vx", "$vd, $vs2, $rs1">;
 def PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd),
                                (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
                                [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">;
 def PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd),
                               (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
                               [], "vmsge.vx", "$vd, $vs2, $rs1$vm">;
 def PseudoVMSGEU_VX_M_T : Pseudo<(outs VMV0:$vd, VR:$scratch),
                                  (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
                                  [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
 def PseudoVMSGE_VX_M_T : Pseudo<(outs VMV0:$vd, VR:$scratch),
                                 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
                                 [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
 }
 
-// This apparently unnecessary alias prevents matching `vmsge{u}.vx vd, vs2, vs1` as if
-// it were an unmasked (i.e. $vm = RISCV::NoRegister) PseudoVMSGE{U}_VX_M.
-def : InstAlias<"vmsgeu.vx $vd, $va, $rs1",
-                (PseudoVMSGEU_VX VR:$vd, VR:$va, GPR:$rs1), 0>;
-def : InstAlias<"vmsge.vx $vd, $va, $rs1",
-                (PseudoVMSGE_VX VR:$vd, VR:$va, GPR:$rs1), 0>;
-def : InstAlias<"vmsgeu.vx v0, $va, $rs1, $vm, $vt",
-                (PseudoVMSGEU_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1,
-                                     VMaskOp:$vm), 0>;
-def : InstAlias<"vmsge.vx v0, $va, $rs1, $vm, $vt",
-                (PseudoVMSGE_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1,
-                                    VMaskOp:$vm), 0>;
-def : InstAlias<"vmsgeu.vx $vd, $va, $rs1, $vm",
-                (PseudoVMSGEU_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1,
-                                   VMaskOp:$vm), 0>;
-def : InstAlias<"vmsge.vx $vd, $va, $rs1, $vm",
-                (PseudoVMSGE_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1,
-                                  VMaskOp:$vm), 0>;
-
 // Vector Integer Min/Max Instructions
 defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>;
 defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>;
 defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>;
 defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>;
 
 // Vector Single-Width Integer Multiply Instructions
 defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>;