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Differential D93867

[RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions
ClosedPublic

Authored by craig.topper on Dec 28 2020, 11:44 AM.

Details

Reviewers
khchen
HsiangKai
evandro
arcbbb
monkchiang
frasercrmck
Commits
rG2ae760e27e6a: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m…
Summary

The spec for these instructions include this note. "The destination register
cannot overlap either the source register or the mask register ('v0') if the
instruction is masked." So we need earlyclobber to enforce this constraint.

I've regenerated the tests with update_llc_test_checks.py to show the
effects of the earlyclobber.

Diff Detail

Event Timeline

craig.topper created this revision.Dec 28 2020, 11:44 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 27 others. · View Herald TranscriptDec 28 2020, 11:44 AM
craig.topper requested review of this revision.Dec 28 2020, 11:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 28 2020, 11:44 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added reviewers: evandro, arcbbb, monkchiang.Dec 28 2020, 11:46 AM
Harbormaster completed remote builds in B83596: Diff 313879.Dec 28 2020, 12:34 PM
khchen added a comment.Dec 28 2020, 8:36 PM

LGTM, thanks for fixup!

khchen accepted this revision.Dec 28 2020, 8:36 PM
This revision is now accepted and ready to land.Dec 28 2020, 8:36 PM
frasercrmck accepted this revision.Dec 29 2020, 3:47 AM

LGTM

Closed by commit rG2ae760e27e6a: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m… (authored by craig.topper). · Explain WhyDec 29 2020, 10:11 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG2ae760e27e6a: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
5 lines
test/
CodeGen/
RISCV/
rvv/
141 lines
141 lines
141 lines
141 lines
141 lines
141 lines

Diff 313979

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 814 Lines • ▼ Show 20 Lines foreach mti = AllMasks in
let VLMul = mti.LMul.value in { let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>; def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>;
def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask; def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask;
} }
} }
} }
multiclass VPseudoUnaryM_M { multiclass VPseudoUnaryM_M {
defvar constraint = "@earlyclobber $rd";
foreach mti = AllMasks in foreach mti = AllMasks in
{ {
let VLMul = mti.LMul.value in { let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR>; def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>;
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR>; def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>;
} }
} }
} }
multiclass VPseudoMaskNullaryV { multiclass VPseudoMaskNullaryV {
foreach m = MxList.m in { foreach m = MxList.m in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>; def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>;
▲ Show 20 Lines • Show All 2,241 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsbf.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsbf.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsif.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsif.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i32 %1) i32 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s ; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1
; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1
; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1
; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1
; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1
; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1
; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmsof.m v25, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
i64 %1) i64 %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vmsof.m v25, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1
; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu
; CHECK: vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
i64 %3) i64 %3)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }