[AIX][XCOFF] emit vector info of traceback table.

[DiggerLin]

Summary

emit vector info of traceback table.

[jasonliu]

llvm/lib/BinaryFormat/XCOFF.cpp

142

Something is wrong if Value != 0u, but I think it's normal when we have more parameters than the uint32 type could encode. And in those situation, as Hubert suggested, we could print ... to represent any values that we could not decode. Please have a test case for this case as well.
Same for parseParmsTypeWithVecInfo function.

llvm/lib/Object/XCOFFObjectFile.cpp

852

This Error as an parameter in the constructor is too easy to get ignored. If we need to do this, we would do the whole set which includes making this constructor private, and have a Create function to return an error or the object, which is described here: https://llvm.org/docs/ProgrammersManual.html#fallible-constructors

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2054

This .get() won't work if you are compiling in a non-assert mode.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

70

Please fix all clang-tidy warnings.

70

Instead of traversing this array for 3 times (getFixedParmsNum, getFloatingPointParmsNum, getVectorParmsNum), why not just still increment the corresponding data member in appendParameterType()?

73

You could pull this out of the every case, and put it just before the switch statement. As you are doing it for every case.

76

You could pull this out of the every case, and put it just after the switch statement. As you are doing it for every case.

97

An assert here would be good.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

70

I think we only use here for getFloatingPointParmsNum, getVectorParmsNum once.
I can increment corresponding data member , but it need three new data member here.

73

it can not pull out, for there are other parameter type (for example FixedType), we do not need deal with in the function.

97

I can not add assert here for there are other parameter type (for example FixedType).

[jasonliu]

llvm/lib/BinaryFormat/XCOFF.cpp

229–230

minor style nit.

255

default assert here?

llvm/lib/Object/XCOFFObjectFile.cpp

923–924

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1968

Only checking error in assert won't work in non-assertion build.

2017

I think we are only supposed to set this bit when the special register VRSAVE is saved on stack.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

70

It's possible these functions got called later for other purposes and we don't know.
If we need new data members then we could just add it, I don't think the memory consumption of three unsigned types are too bad (comparing to three suboptimal traverse).

75

[jasonliu]

llvm/include/llvm/Object/XCOFFObjectFile.h

398–399

Let's remove this "friend" so that no one could call the constructor directly.

llvm/lib/Object/XCOFFObjectFile.cpp

960

I thought we only need to do this ErrorAsOutParameter once at the beginning of the function. Why do we need to do it 3 times at here and 981 and 992?

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2030

There is also a VSCR register, do we need to check that? Or are we inferring checking V0 to V31 would be enough to find out if any vmx instruction is used? If so, a comment would be desired.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

69

What if we don't have parameters that are vectors, but we use vectors inside of the function? I thought we should set HasVectorInfo in those situation as well.

183

Address the Lint comment.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

57

Is it possible to have tests for these fields?

[DiggerLin]

llvm/include/llvm/Object/XCOFFObjectFile.h

398–399

thanks

llvm/lib/BinaryFormat/XCOFF.cpp

255

there 4 cases for 2 bits, I do not think we need default here.

llvm/lib/Object/XCOFFObjectFile.cpp

923–924

thanks

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1968

thanks

2017

Hubert point out that XL sets the bit (at least when there are other vector registers saved) , maybe we need double confirm with hubert @hubert.reinterpretcast

2030

I do not think we need to check the VSCR. for "Special instructions
(mfvscr and mtvscr) are provided to move the VSCR from and to a vector register"
when operated on the vscr, there must be Vector register , we can check register PPC::V0 ~PPC::V31 .

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

69

thanks for point out.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

57

I can not add a test case for it. There is error as " error in backend: variadic arguments for vector types are unimplemented for AIX"

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2017

You're both right. XL sets the bit (I don't think it was supposed to). The funny thing is that setting the bit prevents a possible misinterpretation of the traceback table by the XL C++ runtime because of a confluence of errors.

[jasonliu]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1870

I have concerns about writing our own version of this function.
I think it's important to understand why the MRI version doesn't work. Is it a bug or work as intended? If writing our own version is really necessary, I would avoid naming them the same as it's going to cause confusion for people on when to use which version.

2016

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

57

Sure. I saw you add a test case to test the error for HasVarArgs, which is good.
But what about NumOfVRsSaved = 0, -IsVRSavedOnStack? I don't think that get affected by the error.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll

6

I don't think we want to use include in the lit test. You could write the declaration yourself. And you probably don't even need to call vec_abs if you just want to check if HasVarArgs bit is set?

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2008

To coordinate with D96351, the number of vector registers saved should be zero in the default ABI.

[DiggerLin]

address comment.

[DiggerLin]

rebased on the latest source code

[jasonliu]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

852

If this is necessary, could we add a test case for it? Right now, even setting the third parameter to always be false, I don't see any lit failing.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

123

Do you need to store this info?
For hasVectorParms() function, could you do return VectorParmsNum; instead? Or you could also get rid of that function and use getVectorParmsNum() != 0.

[DiggerLin]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

852

I do not think we need to new test case ,
in the function MachineRegisterInfo::isPhysRegUsed , we change the

if (UsedPhysRegMask.test(PhysReg))

return true;

--->

if (!SkipTestUsedPhysRegMask && UsedPhysRegMask.test(PhysReg))

return true;

and the the default value of SkipTestUsedPhysRegMask is false, it means , all the behaviors not change.

the behaviors only changes when SkipTestUsedPhysRegMask =true;

and we have invoked
MRI.isPhysRegModified(Reg, false, true) in several place in the function PPCAIXAsmPrinter::emitTracebackTable.
I think we have test SkipTestUsedPhysRegMask =true too.

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

123

yes, I can delete the variable .

[DiggerLin]

address comment

[jasonliu]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

852

Discussed offline, we need to add a test if the extra parameter is needed.

856–860

Please change accordingly for the isPhysRegModified above as well.

llvm/lib/BinaryFormat/XCOFF.cpp

146–147

nit

151

Nit: Remove else.

269

nit: Remove else

llvm/lib/CodeGen/MachineRegisterInfo.cpp

603

I think this parameter name is too verbose. Suggest:
SkipTestUsedPhysRegMask -> SkipRegMaskTest

llvm/lib/Object/XCOFFObjectFile.cpp

968

nit

982

Is llvm-objdump capable of decoding the traceback table? Do we want to have a test case using llvm-objdump? Or are we thinking to put it on another patch?

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

1889

Could we add a comment saying that we would only treat instructions uses vector register as vector instructions?

1889

For the places that we use raw boolean value, could we have a comment beside to state what that value is for?
i.e.
if (MRI.isPhysRegUsed(Reg, /* SkipRegMaskTest */ true)) {

2039–2044

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

84

Could we use a switch statement here instead instead of ifs? Also report_fatal_error if the Type is something we don't know.

[jasonliu]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

140–143

Could we combine the above two if statement?

[jasonliu]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

132

Does this store the parameter types when the parameter is on stack? Right now, it doesn't look like so. And this sounds like we are trying to store all paramters including the one on stack.
Could we add a test case for testing parameters on stack?

[DiggerLin]

llvm/lib/Object/XCOFFObjectFile.cpp

982

we have patch which can decode traceback table of object file. https://reviews.llvm.org/D89049

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

140–143

can not combine it, for Elt == FixedType && !hasVectorParms() , it only need one bit, so when Bits ==31, we can still put one bit of FixedType which do not have hasVectorParms().

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

132

we do not store the parameter types when the parameter is on stack.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

132

in the llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll , there are some parameter are stored on stack.

[DiggerLin]

address comment

[jasonliu]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

856–859

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

132

Consider this test case:

int foo(int a, int b, int c, float d, int e, int f, int g, int h, int i,  float j, int k) {
  return k;
}

The print out I get is:

.vbyte  4, 0x10400000                   # Parameter type = i, i, i, f, i, i, i, i, f

However, I'm expecting this if it supports parameter saved on stack correctly:

1. Parameter type = i, i, i, f, i, i, i, i, i, f, i

Notice the two i are missing around the last f.

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

105

Could we add a comment here for this padding as well?

[DiggerLin]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

856–859

thanks

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

132

we only care about the parameter which are passed in register for Parameter type.
there are only 8 GPR for parameter saved. i, i, i, f(occupied on a FPR and burned a GPR), i, i, i, i, already 8 GPR.

[DiggerLin]

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

105

thanks

[DiggerLin]

added a padding comment for the vector info

[jasonliu]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

140–143

So what would not work for the suggestions I made?

[jasonliu]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

122–123

125–126

128–135

132

Could you modify the above comment: /// ParamTypes - Store all the paramters type.
to be /// ParamtersType - Store all the parameter's type that are saved on registers.

[DiggerLin]

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

140–143

change as suggestion, thanks

[DiggerLin]

rebased code

[jasonliu]

LGTM; Thanks!

llvm/include/llvm/BinaryFormat/XCOFF.h

 #define LLVM_BINARYFORMAT_XCOFF_H
 
 #include <stddef.h>
 #include <stdint.h>
 
 namespace llvm {
 class StringRef;
 template <unsigned> class SmallString;
+template <typename T> class Expected;
 
 namespace XCOFF {
 
 // Constants used in the XCOFF definition.
 
 constexpr size_t FileNamePadSize = 6;
 constexpr size_t NameSize = 8;
 constexpr size_t SymbolTableEntrySize = 18;

 enum CFileCpuId : uint8_t {
   TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
   TCPU_COM = 3,   ///< POWER and PowerPC architecture common.
   TCPU_970 = 19   ///< PPC970 - PowerPC 64-bit architecture.
 };
 
 StringRef getMappingClassString(XCOFF::StorageMappingClass SMC);
 StringRef getRelocationTypeString(XCOFF::RelocationType Type);
-SmallString<32> parseParmsType(uint32_t Value, unsigned ParmsNum);
+Expected<SmallString<32>> parseParmsType(uint32_t Value, unsigned FixedParmsNum,
+                                         unsigned FloatingParmsNum);
+Expected<SmallString<32>> parseParmsTypeWithVecInfo(uint32_t Value,
+                                                    unsigned FixedParmsNum,
+                                                    unsigned FloatingParmsNum,
+                                                    unsigned VectorParmsNum);
+Expected<SmallString<32>> parseVectorParmsType(uint32_t Value,
+                                               unsigned ParmsNum);
 
 struct TracebackTable {
   enum LanguageID : uint8_t {
     C,
     Fortran,
     Pascal,
     Ada,
     PL1,
struct TracebackTable {
   static constexpr uint16_t NumberOfVectorParmsMask = 0x00FE;
   static constexpr uint16_t HasVMXInstructionMask = 0x0001;
   static constexpr uint8_t NumberOfVectorParmsShift = 1;
 
   static constexpr uint32_t ParmTypeIsVectorCharBit = 0x0000'0000;
   static constexpr uint32_t ParmTypeIsVectorShortBit = 0x4000'0000;
   static constexpr uint32_t ParmTypeIsVectorIntBit = 0x8000'0000;
   static constexpr uint32_t ParmTypeIsVectorFloatBit = 0xC000'0000;
+
+  static constexpr uint8_t WidthOfParamType = 2;
 };
 
 // Extended Traceback table flags.
 enum ExtendedTBTableFlag : uint8_t {
   TB_OS1 = 0x80,         ///< Reserved for OS use.
   TB_RESERVED = 0x40,    ///< Reserved for compiler.
   TB_SSP_CANARY = 0x20,  ///< stack smasher canary present on stack.
   TB_OS2 = 0x10,         ///< Reserved for OS use.

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

for (MachineInstr *MI : Users) {
       MI->getOperand(0).setReg(Reg);
     }
   }
 
   /// Return true if the specified register is modified in this function.
   /// This checks that no defining machine operands exist for the register or
   /// any of its aliases. Definitions found on functions marked noreturn are
   /// ignored, to consider them pass 'true' for optional parameter
-  /// SkipNoReturnDef. The register is also considered modified when it is set
-  /// in the UsedPhysRegMask.
-  bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
+  /// SkipNoReturnDef. if SkipTestUsedPhysRegMask is false, The register is also
+  /// considered modified when it is set in the UsedPhysRegMask.
+  bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false,
+                         bool SkipTestUsedPhysRegMask = false) const;
 
   /// Return true if the specified register is modified or read in this
   /// function. This checks that no machine operands exist for the register or
-  /// any of its aliases. The register is also considered used when it is set
-  /// in the UsedPhysRegMask.
-  bool isPhysRegUsed(MCRegister PhysReg) const;
+  /// any of its aliases. if SkipTestUsedPhysRegMask is false, The register is
+  /// also considered used when it is set in the UsedPhysRegMask.
+  bool isPhysRegUsed(MCRegister PhysReg,
+                     bool SkipTestUsedPhysRegMask = false) const;
 
   /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
   /// This corresponds to the bit mask attached to register mask operands.
   void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
     UsedPhysRegMask.setBitsNotInMask(RegMask);
   }
 
   const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
 

llvm/include/llvm/Object/XCOFFObjectFile.h

public:
   const XCOFFCsectAuxEnt32 *getXCOFFCsectAuxEnt32() const;
   uint16_t getType() const;
   int16_t getSectionNumber() const;
 
   bool hasCsectAuxEnt() const;
   bool isFunction() const;
 };
 
 class TBVectorExt {
-  friend class XCOFFTracebackTable;
-
   uint16_t Data;
-  uint32_t VecParmsInfo;
+  SmallString<32> VecParmsInfo;
 
-  TBVectorExt(StringRef TBvectorStrRef);
+  TBVectorExt(StringRef TBvectorStrRef, Error &Err);
 
 public:
+  static Expected<TBVectorExt> create(StringRef TBvectorStrRef);
   uint8_t getNumberOfVRSaved() const;
   bool isVRSavedOnStack() const;
   bool hasVarArgs() const;
   uint8_t getNumberOfVectorParms() const;
   bool hasVMXInstruction() const;
-  SmallString<32> getVectorParmsInfoString() const;
+  SmallString<32> getVectorParmsInfo() const { return VecParmsInfo; };
 };
 
 /// This class provides methods to extract traceback table data from a buffer.
 /// The various accessors may reference the buffer provided via the constructor.
 
 class XCOFFTracebackTable {
   const uint8_t *const TBPtr;
   Optional<SmallString<32>> ParmsType;

llvm/lib/BinaryFormat/XCOFF.cpp

 //===-- llvm/BinaryFormat/XCOFF.cpp - The XCOFF file format -----*- C++/-*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/BinaryFormat/XCOFF.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Support/Errc.h"
+#include "llvm/Support/Error.h"
 
 using namespace llvm;
 
 #define SMC_CASE(A)                                                            \
   case XCOFF::XMC_##A:                                                         \
     return #A;
 StringRef XCOFF::getMappingClassString(XCOFF::StorageMappingClass SMC) {
   switch (SMC) {
switch (Type) {
     RELOC_CASE(R_TLS_LE)
     RELOC_CASE(R_TLSM)
     RELOC_CASE(R_TLSML)
     RELOC_CASE(R_TOCU)
     RELOC_CASE(R_TOCL)
   }
   return "Unknown";
 }
+#undef RELOC_CASE
 
 #define LANG_CASE(A)                                                           \
   case XCOFF::TracebackTable::A:                                               \
     return #A;
 
 StringRef XCOFF::getNameForTracebackTableLanguageId(
     XCOFF::TracebackTable::LanguageID LangId) {
   switch (LangId) {
switch (LangId) {
     LANG_CASE(Java)
     LANG_CASE(ObjectiveC)
     LANG_CASE(CPlusPlus)
   }
   return "Unknown";
 }
 #undef LANG_CASE
 
-SmallString<32> XCOFF::parseParmsType(uint32_t Value, unsigned ParmsNum) {
+Expected<SmallString<32>> XCOFF::parseParmsType(uint32_t Value,
+                                                unsigned FixedParmsNum,
+                                                unsigned FloatingParmsNum) {
   SmallString<32> ParmsType;
-  for (unsigned I = 0; I < ParmsNum; ++I) {
-    if (I != 0)
+  int Bits = 0;
+  unsigned ParsedFixedNum = 0;
+  unsigned ParsedFloatingNum = 0;
+  unsigned ParsedNum = 0;
+  unsigned ParmsNum = FixedParmsNum + FloatingParmsNum;
+
+  while (Bits < 32 && ParsedNum < ParmsNum) {
+    if (++ParsedNum > 1)
       ParmsType += ", ";
     if ((Value & TracebackTable::ParmTypeIsFloatingBit) == 0) {
       // Fixed parameter type.
       ParmsType += "i";
+      ++ParsedFixedNum;
       Value <<= 1;
+      ++Bits;
     } else {
       if ((Value & TracebackTable::ParmTypeFloatingIsDoubleBit) == 0)
         // Float parameter type.
         ParmsType += "f";
       else
         // Double parameter type.
         ParmsType += "d";
-
+      ++ParsedFloatingNum;
       Value <<= 2;
+      Bits += 2;
     }
   }
-  assert(Value == 0u && "ParmsType encodes more than ParmsNum parameters.");
+
+  // We have more parameters than the 32 Bits could encode.
+  if (ParsedNum < ParmsNum)
+    ParmsType += ", ...";
+
+  if (Value != 0u || (ParsedFixedNum > FixedParmsNum) ||
+      (ParsedFloatingNum > FloatingParmsNum))
+    return createStringError(errc::invalid_argument,
+                             "ParmsType encodes can not map to ParmsNum "
+                             "parameters in parseParmsType.");
+  else
     return ParmsType;
 }
 
 SmallString<32> XCOFF::getExtendedTBTableFlagString(uint8_t Flag) {
   SmallString<32> Res;
 
   if (Flag & ExtendedTBTableFlag::TB_OS1)
     Res += "TB_OS1 ";
   if (Flag & ExtendedTBTableFlag::TB_RESERVED)
SmallString<32> XCOFF::getExtendedTBTableFlagString(uint8_t Flag) {
   if (Flag & 0x06)
     Res += "Unknown ";
 
   // Pop the last space.
   Res.pop_back();
   return Res;
 }
 
-#undef RELOC_CASE
+Expected<SmallString<32>>
+XCOFF::parseParmsTypeWithVecInfo(uint32_t Value, unsigned FixedParmsNum,
+                                 unsigned FloatingParmsNum,
+                                 unsigned VectorParmsNum) {
+  SmallString<32> ParmsType;
+
+  unsigned ParsedFixedNum = 0;
+  unsigned ParsedFloatingNum = 0;
+  unsigned ParsedVectorNum = 0;
+  unsigned ParsedNum = 0;
+  unsigned ParmsNum = FixedParmsNum + FloatingParmsNum + VectorParmsNum;
+
+  for (int Bits = 0; Bits < 32 && ParsedNum < ParmsNum; Bits += 2) {
+    if (++ParsedNum > 1)
+      ParmsType += ", ";
+
+    switch (Value & TracebackTable::ParmTypeMask) {
+    case TracebackTable::ParmTypeIsFixedBits:
+      ParmsType += "i";
+      ++ParsedFixedNum;
+      break;
+    case TracebackTable::ParmTypeIsVectorBits:
+      ParmsType += "v";
+      ++ParsedVectorNum;
+      break;
+    case TracebackTable::ParmTypeIsFloatingBits:
+      ParmsType += "f";
+      ++ParsedFloatingNum;
+      break;
+    case TracebackTable::ParmTypeIsDoubleBits:
+      ParmsType += "d";
+      ++ParsedFloatingNum;
+      break;
+    default:
+      assert(false && "Unrecognized bits in ParmsType.");
+    }
+    Value <<= 2;
+  }
+
+  // We have more parameters than the 32 Bits could encode.
+  if (ParsedNum < ParmsNum)
+    ParmsType += ", ...";
+
+  if (Value != 0u || ParsedFixedNum > FixedParmsNum ||
+      ParsedFloatingNum > FloatingParmsNum || ParsedVectorNum > VectorParmsNum)
+    return createStringError(
+        errc::invalid_argument,
+        "ParmsType encodes can not map to ParmsNum parameters "
+        "in parseParmsTypeWithVecInfo.");
+
+  return ParmsType;
+}
+
+Expected<SmallString<32>> XCOFF::parseVectorParmsType(uint32_t Value,
+                                                      unsigned ParmsNum) {
+  SmallString<32> ParmsType;
+  unsigned ParsedNum = 0;
+  for (int Bits = 0; ParsedNum < ParmsNum && Bits < 32; Bits += 2) {
+    if (++ParsedNum > 1)
+      ParmsType += ", ";
+    switch (Value & TracebackTable::ParmTypeMask) {
+    case TracebackTable::ParmTypeIsVectorCharBit:
+      ParmsType += "vc";
+      break;
+
+    case TracebackTable::ParmTypeIsVectorShortBit:
+      ParmsType += "vs";
+      break;
+
+    case TracebackTable::ParmTypeIsVectorIntBit:
+      ParmsType += "vi";
+      break;
+
+    case TracebackTable::ParmTypeIsVectorFloatBit:
+      ParmsType += "vf";
+      break;
+    }
+
+    Value <<= 2;
+  }
+
+  // We have more parameters than the 32 Bits could encode.
+  if (ParsedNum < ParmsNum)
+    ParmsType += ", ...";
+
+  if (Value != 0u)
+    return createStringError(errc::invalid_argument,
+                             "ParmsType encodes more than ParmsNum parameters "
+                             "in parseVectorParmsType.");
+  else
+    return ParmsType;
+}

llvm/lib/CodeGen/MachineRegisterInfo.cpp

static bool isNoReturnDef(const MachineOperand &MO) {
   // not return, since the runtime may need it.
   if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
     return false;
   const Function *Called = getCalledFunction(MI);
   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
            !Called->hasFnAttribute(Attribute::NoUnwind));
 }
 
-bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
-                                            bool SkipNoReturnDef) const {
-  if (UsedPhysRegMask.test(PhysReg))
+bool MachineRegisterInfo::isPhysRegModified(
+    MCRegister PhysReg, bool SkipNoReturnDef,
+    bool SkipTestUsedPhysRegMask) const {
+  if (!SkipTestUsedPhysRegMask && UsedPhysRegMask.test(PhysReg))
     return true;
   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
       if (!SkipNoReturnDef && isNoReturnDef(MO))
         continue;
       return true;
     }
   }
   return false;
 }
 
-bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {
-  if (UsedPhysRegMask.test(PhysReg))
+bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
+                                        bool SkipTestUsedPhysRegMask) const {
+  if (!SkipTestUsedPhysRegMask && UsedPhysRegMask.test(PhysReg))
     return true;
   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
        ++AliasReg) {
     if (!reg_nodbg_empty(*AliasReg))
       return true;
   }
   return false;

llvm/lib/Object/XCOFFObjectFile.cpp

 
 bool doesXCOFFTracebackTableBegin(ArrayRef<uint8_t> Bytes) {
   if (Bytes.size() < 4)
     return false;
 
   return support::endian::read32be(Bytes.data()) == 0;
 }
 
-TBVectorExt::TBVectorExt(StringRef TBvectorStrRef) {
+#define GETVALUEWITHMASK(X) (Data & (TracebackTable::X))
+#define GETVALUEWITHMASKSHIFT(X, S)                                            \
+  ((Data & (TracebackTable::X)) >> (TracebackTable::S))
+
+Expected<TBVectorExt> TBVectorExt::create(StringRef TBvectorStrRef) {
+  Error Err = Error::success();
+  TBVectorExt TBTVecExt(TBvectorStrRef, Err);
+  if (Err)
+    return std::move(Err);
+  return TBTVecExt;
+}
+
+TBVectorExt::TBVectorExt(StringRef TBvectorStrRef, Error &Err) {
   const uint8_t *Ptr = reinterpret_cast<const uint8_t *>(TBvectorStrRef.data());
   Data = support::endian::read16be(Ptr);
-  VecParmsInfo = support::endian::read32be(Ptr + 2);
+  uint32_t VecParmsTypeValue = support::endian::read32be(Ptr + 2);
+  unsigned ParmsNum =
+      GETVALUEWITHMASKSHIFT(NumberOfVectorParmsMask, NumberOfVectorParmsShift);
+
+  ErrorAsOutParameter EAO(&Err);
+  Expected<SmallString<32>> VecParmsTypeOrError =
+      parseVectorParmsType(VecParmsTypeValue, ParmsNum);
+  if (!VecParmsTypeOrError)
+    Err = VecParmsTypeOrError.takeError();
+  else
+    VecParmsInfo = VecParmsTypeOrError.get();
 }
 
-#define GETVALUEWITHMASK(X) (Data & (TracebackTable::X))
-#define GETVALUEWITHMASKSHIFT(X, S)                                            \
-  ((Data & (TracebackTable::X)) >> (TracebackTable::S))
 uint8_t TBVectorExt::getNumberOfVRSaved() const {
   return GETVALUEWITHMASKSHIFT(NumberOfVRSavedMask, NumberOfVRSavedShift);
 }
 
 bool TBVectorExt::isVRSavedOnStack() const {
   return GETVALUEWITHMASK(IsVRSavedOnStackMask);
 }
 
 bool TBVectorExt::hasVarArgs() const {
   return GETVALUEWITHMASK(HasVarArgsMask);
 }
+
 uint8_t TBVectorExt::getNumberOfVectorParms() const {
   return GETVALUEWITHMASKSHIFT(NumberOfVectorParmsMask,
                                NumberOfVectorParmsShift);
 }
 
 bool TBVectorExt::hasVMXInstruction() const {
   return GETVALUEWITHMASK(HasVMXInstructionMask);
 }
 #undef GETVALUEWITHMASK
 #undef GETVALUEWITHMASKSHIFT
 
-SmallString<32> TBVectorExt::getVectorParmsInfoString() const {
-  SmallString<32> ParmsType;
-  uint32_t Value = VecParmsInfo;
-  for (uint8_t I = 0; I < getNumberOfVectorParms(); ++I) {
-    if (I != 0)
-      ParmsType += ", ";
-    switch (Value & TracebackTable::ParmTypeMask) {
-    case TracebackTable::ParmTypeIsVectorCharBit:
-      ParmsType += "vc";
-      break;
-
-    case TracebackTable::ParmTypeIsVectorShortBit:
-      ParmsType += "vs";
-      break;
-
-    case TracebackTable::ParmTypeIsVectorIntBit:
-      ParmsType += "vi";
-      break;
-
-    case TracebackTable::ParmTypeIsVectorFloatBit:
-      ParmsType += "vf";
-      break;
-    }
-    Value <<= 2;
-  }
-  return ParmsType;
-}
-
-static SmallString<32> parseParmsTypeWithVecInfo(uint32_t Value,
-                                                 unsigned int ParmsNum) {
-  SmallString<32> ParmsType;
-  unsigned I = 0;
-  bool Begin = false;
-  while (I < ParmsNum || Value) {
-    if (Begin)
-      ParmsType += ", ";
-    else
-      Begin = true;
-
-    switch (Value & TracebackTable::ParmTypeMask) {
-    case TracebackTable::ParmTypeIsFixedBits:
-      ParmsType += "i";
-      ++I;
-      break;
-    case TracebackTable::ParmTypeIsVectorBits:
-      ParmsType += "v";
-      break;
-    case TracebackTable::ParmTypeIsFloatingBits:
-      ParmsType += "f";
-      ++I;
-      break;
-    case TracebackTable::ParmTypeIsDoubleBits:
-      ParmsType += "d";
-      ++I;
-      break;
-    default:
-      assert(false && "Unrecognized bits in ParmsType.");
-    }
-    Value <<= 2;
-  }
-  assert(I == ParmsNum &&
-         "The total parameters number of fixed-point or floating-point "
-         "parameters not equal to the number in the parameter type!");
-  return ParmsType;
-}
-
 Expected<XCOFFTracebackTable> XCOFFTracebackTable::create(const uint8_t *Ptr,
                                                           uint64_t &Size) {
   Error Err = Error::success();
   XCOFFTracebackTable TBT(Ptr, Size, Err);
   if (Err)
     return std::move(Err);
   return TBT;
 }
 
 XCOFFTracebackTable::XCOFFTracebackTable(const uint8_t *Ptr, uint64_t &Size,
                                          Error &Err)
     : TBPtr(Ptr) {
   ErrorAsOutParameter EAO(&Err);
   DataExtractor DE(ArrayRef<uint8_t>(Ptr, Size), /*IsLittleEndian=*/false,
                    /*AddressSize=*/0);
   DataExtractor::Cursor Cur(/*Offset=*/0);
 
   // Skip 8 bytes of mandatory fields.
   DE.getU64(Cur);
 
-  // Begin to parse optional fields.
-  if (Cur) {
-    unsigned ParmNum = getNumberOfFixedParms() + getNumberOfFPParms();
+  unsigned FixedParmsNum = getNumberOfFixedParms();
+  unsigned FloatingParmsNum = getNumberOfFPParms();
+  uint32_t ParamsTypeValue = 0;
 
-    // As long as there are no "fixed-point" or floating-point parameters, this
-    // field remains not present even when hasVectorInfo gives true and
-    // indicates the presence of vector parameters.
-    if (ParmNum > 0) {
-      uint32_t ParamsTypeValue = DE.getU32(Cur);
-      if (Cur)
-        ParmsType = hasVectorInfo()
-                        ? parseParmsTypeWithVecInfo(ParamsTypeValue, ParmNum)
-                        : parseParmsType(ParamsTypeValue, ParmNum);
-    }
-  }
+  // Begin to parse optional fields.
+  if (Cur && (FixedParmsNum + FloatingParmsNum) > 0)
+    ParamsTypeValue = DE.getU32(Cur);
 
   if (Cur && hasTraceBackTableOffset())
     TraceBackTableOffset = DE.getU32(Cur);
 
   if (Cur && isInterruptHandler())
     HandlerMask = DE.getU32(Cur);
 
   if (Cur && hasControlledStorage()) {
if (Cur && isFuncNamePresent()) {
     uint16_t FunctionNameLen = DE.getU16(Cur);
     if (Cur)
       FunctionName = DE.getBytes(Cur, FunctionNameLen);
   }
 
   if (Cur && isAllocaUsed())
     AllocaRegister = DE.getU8(Cur);
 
+  unsigned VectorParmsNum = 0;
   if (Cur && hasVectorInfo()) {
     StringRef VectorExtRef = DE.getBytes(Cur, 6);
-    if (Cur)
-      VecExt = TBVectorExt(VectorExtRef);
+    if (Cur) {
+      Expected<TBVectorExt> TBVecExtOrErr = TBVectorExt::create(VectorExtRef);
+      if (!TBVecExtOrErr) {
+        Err = TBVecExtOrErr.takeError();
+        return;
+      }
+      VecExt = TBVecExtOrErr.get();
+      VectorParmsNum = VecExt.getValue().getNumberOfVectorParms();
+    }
+  }
+
+  // As long as there are no "fixed-point" or floating-point parameters, this
+  // field remains not present even when hasVectorInfo gives true and
+  // indicates the presence of vector parameters.
+  if (Cur && (FixedParmsNum + FloatingParmsNum) > 0) {
+    Expected<SmallString<32>> ParmsTypeOrError =
+        hasVectorInfo()
+            ? parseParmsTypeWithVecInfo(ParamsTypeValue, FixedParmsNum,
+                                        FloatingParmsNum, VectorParmsNum)
+            : parseParmsType(ParamsTypeValue, FixedParmsNum, FloatingParmsNum);
+
+    if (!ParmsTypeOrError) {
+      Err = ParmsTypeOrError.takeError();
+      return;
+    }
+    ParmsType = ParmsTypeOrError.get();
   }
 
   if (Cur && hasExtensionTable())
     ExtensionTable = DE.getU8(Cur);
 
   if (!Cur)
     Err = Cur.takeError();
+
   Size = Cur.tell();
 }
 
 #define GETBITWITHMASK(P, X)                                                   \
   (support::endian::read32be(TBPtr + (P)) & (TracebackTable::X))
 #define GETBITWITHMASKSHIFT(P, X, S)                                           \
   ((support::endian::read32be(TBPtr + (P)) & (TracebackTable::X)) >>           \
    (TracebackTable::S))

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCSymbolELF.h"
 #include "llvm/MC/MCSymbolXCOFF.h"
 #include "llvm/MC/SectionKind.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Error.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Process.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Transforms/Utils/ModuleUtils.h"
 #include <algorithm>
 #include <cassert>
void PPCAIXAsmPrinter::emitTracebackTable() {
   // We always set traceback offset bit to true.
   FirstHalfOfMandatoryField |= TracebackTable::HasTraceBackTableOffsetMask;
 
   const PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
 
   // Check the function uses floating-point processor instructions or not
   for (unsigned Reg = PPC::F0; Reg <= PPC::F31; ++Reg) {
-    if (MRI.isPhysRegUsed(Reg)) {
+    if (MRI.isPhysRegUsed(Reg, true)) {
       FirstHalfOfMandatoryField |= TracebackTable::IsFloatingPointPresentMask;
       break;
     }
   }
 
 #define GENBOOLCOMMENT(Prefix, V, Field)                                       \
   CommentOS << (Prefix) << ((V) & (TracebackTable::Field##Mask) ? "+" : "-")   \
             << #Field
#define GENVALUECOMMENT(PrefixAndName, V, Field)                               \
 
   OutStreamer->emitIntValueInHexWithPadding(
       (FirstHalfOfMandatoryField & 0x0000ff00) >> 8, 1);
 
   // Set the 4th byte of the mandatory field.
   FirstHalfOfMandatoryField |= TracebackTable::IsFunctionNamePresentMask;
 
   static_assert(XCOFF::AllocRegNo == 31, "Unexpected register usage!");
-  if (MRI.isPhysRegUsed(Subtarget->isPPC64() ? PPC::X31 : PPC::R31))
+  if (MRI.isPhysRegUsed(Subtarget->isPPC64() ? PPC::X31 : PPC::R31, true))
     FirstHalfOfMandatoryField |= TracebackTable::IsAllocaUsedMask;
 
   const SmallVectorImpl<Register> &MustSaveCRs = FI->getMustSaveCRs();
   if (!MustSaveCRs.empty())
     FirstHalfOfMandatoryField |= TracebackTable::IsCRSavedMask;
 
   if (FI->mustSaveLR())
     FirstHalfOfMandatoryField |= TracebackTable::IsLRSavedMask;
#define GENVALUECOMMENT(PrefixAndName, V, Field)                               \
   // Set the 5th byte of mandatory field.
   uint32_t SecondHalfOfMandatoryField = 0;
 
   // Always store back chain.
   SecondHalfOfMandatoryField |= TracebackTable::IsBackChainStoredMask;
 
   uint32_t FPRSaved = 0;
   for (unsigned Reg = PPC::F14; Reg <= PPC::F31; ++Reg) {
-    if (MRI.isPhysRegModified(Reg)) {
+    if (MRI.isPhysRegModified(Reg, false, true)) {
       FPRSaved = PPC::F31 - Reg + 1;
       break;
     }
   }
   SecondHalfOfMandatoryField |= (FPRSaved << TracebackTable::FPRSavedShift) &
                                 TracebackTable::FPRSavedMask;
   GENBOOLCOMMENT("", SecondHalfOfMandatoryField, IsBackChainStored);
   GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, IsFixup);
   GENVALUECOMMENT(", NumOfFPRsSaved", SecondHalfOfMandatoryField, FPRSaved);
   EmitComment();
   OutStreamer->emitIntValueInHexWithPadding(
       (SecondHalfOfMandatoryField & 0xff000000) >> 24, 1);
 
   // Set the 6th byte of mandatory field.
+
+  // Check whether has Vector Instruction
+  bool HasVectorInst = false;
+  for (unsigned Reg = PPC::V0; Reg <= PPC::V31; ++Reg)
+    if (MRI.isPhysRegUsed(Reg, true)) {
+      // Has VMX instruction.
+      HasVectorInst = true;
+      break;
+    }
+
+  if (FI->hasVectorParms() || HasVectorInst)
+    SecondHalfOfMandatoryField |= TracebackTable::HasVectorInfoMask;
+
   bool ShouldEmitEHBlock = TargetLoweringObjectFileXCOFF::ShouldEmitEHBlock(MF);
   if (ShouldEmitEHBlock)
     SecondHalfOfMandatoryField |= TracebackTable::HasExtensionTableMask;
 
   uint32_t GPRSaved = 0;
 
   // X13 is reserved under 64-bit environment.
   unsigned GPRBegin = Subtarget->isPPC64() ? PPC::X14 : PPC::R13;
   unsigned GPREnd = Subtarget->isPPC64() ? PPC::X31 : PPC::R31;
 
   for (unsigned Reg = GPRBegin; Reg <= GPREnd; ++Reg) {
-    if (MRI.isPhysRegModified(Reg)) {
+    if (MRI.isPhysRegModified(Reg, false, true)) {
       GPRSaved = GPREnd - Reg + 1;
       break;
     }
   }
 
   SecondHalfOfMandatoryField |= (GPRSaved << TracebackTable::GPRSavedShift) &
                                 TracebackTable::GPRSavedMask;
 
   GENBOOLCOMMENT("", SecondHalfOfMandatoryField, HasVectorInfo);
   GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, HasExtensionTable);
   GENVALUECOMMENT(", NumOfGPRsSaved", SecondHalfOfMandatoryField, GPRSaved);
   EmitComment();
   OutStreamer->emitIntValueInHexWithPadding(
       (SecondHalfOfMandatoryField & 0x00ff0000) >> 16, 1);
 
   // Set the 7th byte of mandatory field.
-  uint32_t NumberOfFixedPara = FI->getFixedParamNum();
+  uint32_t NumberOfFixedParms = FI->getFixedParmsNum();
   SecondHalfOfMandatoryField |=
-      (NumberOfFixedPara << TracebackTable::NumberOfFixedParmsShift) &
+      (NumberOfFixedParms << TracebackTable::NumberOfFixedParmsShift) &
       TracebackTable::NumberOfFixedParmsMask;
   GENVALUECOMMENT("NumberOfFixedParms", SecondHalfOfMandatoryField,
                   NumberOfFixedParms);
   EmitComment();
   OutStreamer->emitIntValueInHexWithPadding(
       (SecondHalfOfMandatoryField & 0x0000ff00) >> 8, 1);
 
   // Set the 8th byte of mandatory field.
 
   // Always set parameter on stack.
   SecondHalfOfMandatoryField |= TracebackTable::HasParmsOnStackMask;
 
-  uint32_t NumberOfFPPara = FI->getFloatingPointParamNum();
+  uint32_t NumberOfFPParms = FI->getFloatingPointParmsNum();
   SecondHalfOfMandatoryField |=
-      (NumberOfFPPara << TracebackTable::NumberOfFloatingPointParmsShift) &
+      (NumberOfFPParms << TracebackTable::NumberOfFloatingPointParmsShift) &
       TracebackTable::NumberOfFloatingPointParmsMask;
 
   GENVALUECOMMENT("NumberOfFPParms", SecondHalfOfMandatoryField,
                   NumberOfFloatingPointParms);
   GENBOOLCOMMENT(", ", SecondHalfOfMandatoryField, HasParmsOnStack);
   EmitComment();
   OutStreamer->emitIntValueInHexWithPadding(SecondHalfOfMandatoryField & 0xff,
                                             1);
 
   // Generate the optional fields of traceback table.
 
   // Parameter type.
-  if (NumberOfFixedPara || NumberOfFPPara) {
-    assert((SecondHalfOfMandatoryField & TracebackTable::HasVectorInfoMask) ==
-               0 &&
-           "VectorInfo has not been implemented.");
-    uint32_t ParaType = FI->getParameterType();
-    CommentOS << "Parameter type = "
-              << XCOFF::parseParmsType(ParaType,
-                                       NumberOfFixedPara + NumberOfFPPara);
+  if (NumberOfFixedParms || NumberOfFPParms) {
+    uint32_t ParmsTypeValue = FI->getParmsType();
+
+    Expected<SmallString<32>> ParmsType =
+        FI->hasVectorParms()
+            ? XCOFF::parseParmsTypeWithVecInfo(
+                  ParmsTypeValue, NumberOfFixedParms, NumberOfFPParms,
+                  FI->getVectorParmsNum())
+            : XCOFF::parseParmsType(ParmsTypeValue, NumberOfFixedParms,
+                                    NumberOfFPParms);
+
+    assert(ParmsType && toString(ParmsType.takeError()).c_str());
+    if (ParmsType) {
+      CommentOS << "Parameter type = " << ParmsType.get();
       EmitComment();
-    OutStreamer->emitIntValueInHexWithPadding(ParaType, sizeof(ParaType));
     }
-
+    OutStreamer->emitIntValueInHexWithPadding(ParmsTypeValue,
+                                              sizeof(ParmsTypeValue));
+  }
   // Traceback table offset.
   OutStreamer->AddComment("Function size");
   if (FirstHalfOfMandatoryField & TracebackTable::HasTraceBackTableOffsetMask) {
     MCSymbol *FuncSectSym = getObjFileLowering().getFunctionEntryPointSymbol(
         &(MF->getFunction()), TM);
     OutStreamer->emitAbsoluteSymbolDiff(FuncEnd, FuncSectSym, 4);
   }
 
#define GENVALUECOMMENT(PrefixAndName, V, Field)                               \
   }
 
   if (FirstHalfOfMandatoryField & TracebackTable::IsAllocaUsedMask) {
     uint8_t AllocReg = XCOFF::AllocRegNo;
     OutStreamer->AddComment("AllocaUsed");
     OutStreamer->emitIntValueInHex(AllocReg, sizeof(AllocReg));
   }
 
+  if (SecondHalfOfMandatoryField & TracebackTable::HasVectorInfoMask) {
+    uint16_t VRData = 0;
+    // Calculate the number of VRs be saved.
+    for (unsigned Reg = PPC::V20; Reg <= PPC::V31; ++Reg)
+      if (MRI.isPhysRegModified(Reg, false, true)) {
+        // Number of VRs saved.
+        VRData |=
+            ((PPC::V31 - Reg + 1) << TracebackTable::NumberOfVRSavedShift) &
+            TracebackTable::NumberOfVRSavedMask;
+        // This bit is supposed to set only when the special register
+        // VRSAVE is saved on stack.
+        // However, IBM XL compiler sets the bit when any vector registers
+        // are saved on the stack. We will follow XL's behavior on AIX
+        // so that we don't get surprise behavior change for C code.
+        VRData |= TracebackTable::IsVRSavedOnStackMask;
+        break;
+      }
+
+    // Set has_varargs.
+    if (FI->getVarArgsStackOffset())
+      VRData |= TracebackTable::HasVarArgsMask;
+
+    // Vector parameters number.
+    unsigned VectorParmsNum = FI->getVectorParmsNum();
+    VRData |= (VectorParmsNum << TracebackTable::NumberOfVectorParmsShift) &
+              TracebackTable::NumberOfVectorParmsMask;
+
+    for (unsigned Reg = PPC::V0; Reg <= PPC::V31; ++Reg)
+      if (!MRI.reg_nodbg_empty(Reg)) {
+        // Has VMX instruction.
+        VRData |= TracebackTable::HasVMXInstructionMask;
+        break;
+      }
+
+    GENVALUECOMMENT("NumOfVRsSaved", VRData, NumberOfVRSaved);
+    GENBOOLCOMMENT(", ", VRData, IsVRSavedOnStack);
+    GENBOOLCOMMENT(", ", VRData, HasVarArgs);
+    EmitComment();
+    OutStreamer->emitIntValueInHexWithPadding((VRData & 0xff00) >> 8, 1);
+
+    GENVALUECOMMENT("NumOfVectorParams", VRData, NumberOfVectorParms);
+    GENBOOLCOMMENT(", ", VRData, HasVMXInstruction);
+    EmitComment();
+    OutStreamer->emitIntValueInHexWithPadding(VRData & 0x00ff, 1);
+
+    uint32_t VecParmTypeValue = FI->getVecExtParmsType();
+
+    Expected<SmallString<32>> VecParmsType =
+        XCOFF::parseVectorParmsType(VecParmTypeValue, VectorParmsNum);
+    assert(VecParmsType && toString(VecParmsType.takeError()).c_str());
+    if (VecParmsType) {
+      CommentOS << "Vector Parameter type = " << VecParmsType.get();
+      EmitComment();
+    }
+    OutStreamer->emitIntValueInHexWithPadding(VecParmTypeValue,
+                                              sizeof(VecParmTypeValue));
+  }
+
   uint8_t ExtensionTableFlag = 0;
   if (SecondHalfOfMandatoryField & TracebackTable::HasExtensionTableMask) {
     if (ShouldEmitEHBlock)
       ExtensionTableFlag |= ExtendedTBTableFlag::TB_EH_INFO;
 
     CommentOS << "ExtensionTableFlag = "
               << getExtendedTBTableFlagString(ExtensionTableFlag);
     EmitCommentAndValue(ExtensionTableFlag, sizeof(ExtensionTableFlag));
const MCExpr *Exp =
         MCBinaryExpr::createSub(MCSymbolRefExpr::create(TOCEntry, Ctx),
                                 MCSymbolRefExpr::create(TOCBaseSym, Ctx), Ctx);
 
     const DataLayout &DL = getDataLayout();
     OutStreamer->emitValueToAlignment(4);
     OutStreamer->AddComment("EHInfo Table");
     OutStreamer->emitValue(Exp, DL.getPointerSize());
   }
-
 #undef GENBOOLCOMMENT
 #undef GENVALUECOMMENT
 }
 
 void PPCAIXAsmPrinter::ValidateGV(const GlobalVariable *GV) {
   // Early error checking limiting what is supported.
   if (GV->isThreadLocal())
     report_fatal_error("Thread local not yet supported on AIX.");

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

for (size_t I = 0, End = ArgLocs.size(); I != End; /* No increment here */) {
     // The memloc is dismissed here because the argument is retrieved from
     // the register.
     if (VA.isMemLoc() && VA.needsCustom())
       continue;
 
     if (VA.isRegLoc()) {
       if (VA.getValVT().isScalarInteger())
         FuncInfo->appendParameterType(PPCFunctionInfo::FixedType);
-      else if (VA.getValVT().isFloatingPoint() && !VA.getValVT().isVector())
-        FuncInfo->appendParameterType(VA.getValVT().SimpleTy == MVT::f32
-                                          ? PPCFunctionInfo::ShortFloatPoint
-                                          : PPCFunctionInfo::LongFloatPoint);
+      else if (VA.getValVT().isFloatingPoint() && !VA.getValVT().isVector()) {
+        switch (VA.getValVT().SimpleTy) {
+        default:
+          report_fatal_error("Unhandled value type for argument.");
+        case MVT::f32:
+          FuncInfo->appendParameterType(PPCFunctionInfo::ShortFloatingPoint);
+          break;
+        case MVT::f64:
+          FuncInfo->appendParameterType(PPCFunctionInfo::LongFloatingPoint);
+          break;
+        }
+      } else if (VA.getValVT().isVector()) {
+        switch (VA.getValVT().SimpleTy) {
+        default:
+          report_fatal_error("Unhandled value type for argument.");
+        case MVT::v16i8:
+          FuncInfo->appendParameterType(PPCFunctionInfo::VectorChar);
+          break;
+        case MVT::v8i16:
+          FuncInfo->appendParameterType(PPCFunctionInfo::VectorShort);
+          break;
+        case MVT::v4i32:
+        case MVT::v2i64:
+        case MVT::v1i128:
+          FuncInfo->appendParameterType(PPCFunctionInfo::VectorInt);
+          break;
+        case MVT::v4f32:
+        case MVT::v2f64:
+          FuncInfo->appendParameterType(PPCFunctionInfo::VectorFloat);
+          break;
+        }
+      }
     }
 
     if (Flags.isByVal() && VA.isMemLoc()) {
       const unsigned Size =
           alignTo(Flags.getByValSize() ? Flags.getByValSize() : PtrByteSize,
                   PtrByteSize);
       const int FI = MF.getFrameInfo().CreateFixedObject(
           Size, VA.getLocMemOffset(), /* IsImmutable */ false,

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

 #include "llvm/CodeGen/TargetCallingConv.h"
 
 namespace llvm {
 
 /// PPCFunctionInfo - This class is derived from MachineFunction private
 /// PowerPC target-specific information for each MachineFunction.
 class PPCFunctionInfo : public MachineFunctionInfo {
 public:
-  // The value in the ParamType are used to indicate the bitstrings used in the
-  // encoding format.
   enum ParamType {
-    FixedType = 0x0,
-    ShortFloatPoint = 0x2,
-    LongFloatPoint = 0x3
+    FixedType,
+    ShortFloatingPoint,
+    LongFloatingPoint,
+    VectorChar,
+    VectorShort,
+    VectorInt,
+    VectorFloat
   };
 
 private:
   virtual void anchor();
 
   /// FramePointerSaveIndex - Frame index of where the old frame pointer is
   /// stored.  Also used as an anchor for instructions that need to be altered
   /// when using frame pointers (dyna_add, dyna_sub.)
private:
   /// VarArgsNumGPR - Index of the first unused integer
   /// register for parameter passing.
   unsigned VarArgsNumGPR = 0;
 
   /// VarArgsNumFPR - Index of the first unused double
   /// register for parameter passing.
   unsigned VarArgsNumFPR = 0;
 
-  /// FixedParamNum - Number of fixed parameter.
-  unsigned FixedParamNum = 0;
+  /// HasVectorParms - True if ther are vector parameters
+  bool HasVectorParms = false;
 
-  /// FloatingParamNum - Number of floating point parameter.
-  unsigned FloatingPointParamNum = 0;
+  /// FixedParmsNum - The number of fixed parameters
+  unsigned FixedParmsNum = 0;
 
-  /// ParamType - Encode type for every parameter
-  /// in the order of parameters passing in.
-  /// Bitstring starts from the most significant (leftmost) bit.
-  /// '0'b => fixed parameter.
-  /// '10'b => floating point short parameter.
-  /// '11'b => floating point long parameter.
-  uint32_t ParameterType = 0;
+  /// FloatingParmsNum - The number of floating parameters
+  unsigned FloatingParmsNum = 0;
+
+  /// VectorParmsNum - The number of vector parameters
+  unsigned VectorParmsNum = 0;
+
+  /// ParamTypes - Store all the paramters type.
+  SmallVector<ParamType, 32> ParamtersType;
 
   /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
   int CRSpillFrameIndex = 0;
 
   /// If any of CR[2-4] need to be saved in the prologue and restored in the
   /// epilogue then they are added to this array. This is used for the
   /// 64-bit SVR4 ABI.
   SmallVector<Register, 3> MustSaveCRs;
public:
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 
   int getVarArgsStackOffset() const { return VarArgsStackOffset; }
   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
 
   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
 
-  unsigned getFixedParamNum() const { return FixedParamNum; }
+  unsigned getFixedParmsNum() const { return FixedParmsNum; }
+  unsigned getFloatingPointParmsNum() const { return FloatingParmsNum; }
+  unsigned getVectorParmsNum() const { return VectorParmsNum; }
+  bool hasVectorParms() const { return HasVectorParms; }
+
+  uint32_t getParmsType() const;
 
-  unsigned getFloatingPointParamNum() const { return FloatingPointParamNum; }
+  uint32_t getVecExtParmsType() const;
 
-  uint32_t getParameterType() const { return ParameterType; }
   void appendParameterType(ParamType Type);
 
   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
 
   /// This function associates attributes for each live-in virtual register.
   void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) {
     LiveInAttrs.push_back(std::make_pair(VReg, Flags));

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const {
   for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
     if (LiveIn.first == VReg)
       return LiveIn.second.isZExt();
   return false;
 }
 
 void PPCFunctionInfo::appendParameterType(ParamType Type) {
-  uint32_t CopyParamType = ParameterType;
-  int Bits = 0;
+  if (!HasVectorParms && (Type >= VectorChar && Type <= VectorFloat))
+    HasVectorParms = true;
+
+  ParamtersType.push_back(Type);
+  if (Type >= ShortFloatingPoint && Type <= LongFloatingPoint) {
+    ++FloatingParmsNum;
+    return;
+  }
 
-  // If it is fixed type, we only need to increase the FixedParamNum, for
-  // the bit encode of fixed type is bit of zero, we do not need to change the
-  // ParamType.
   if (Type == FixedType) {
-    ++FixedParamNum;
+    ++FixedParmsNum;
     return;
   }
 
-  ++FloatingPointParamNum;
+  if (Type >= VectorChar && Type <= VectorFloat)
+    ++VectorParmsNum;
+}
 
-  for (int I = 0;
-       I < static_cast<int>(FloatingPointParamNum + FixedParamNum - 1); ++I) {
-    if (CopyParamType & XCOFF::TracebackTable::ParmTypeIsFloatingBit) {
-      // '10'b => floating point short parameter.
-      // '11'b => floating point long parameter.
-      CopyParamType <<= 2;
-      Bits += 2;
+uint32_t PPCFunctionInfo::getVecExtParmsType() const {
+
+  uint32_t VectExtParamInfo = 0;
+  unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType;
+  int Bits = 0;
+
+  if (!HasVectorParms)
+    return 0;
+
+  for (const auto &Elt : ParamtersType) {
+    switch (Elt) {
+    case VectorChar:
+      VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      VectExtParamInfo |=
+          XCOFF::TracebackTable::ParmTypeIsVectorCharBit >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    case VectorShort:
+      VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      VectExtParamInfo |=
+          XCOFF::TracebackTable::ParmTypeIsVectorShortBit >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    case VectorInt:
+      VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      VectExtParamInfo |=
+          XCOFF::TracebackTable::ParmTypeIsVectorIntBit >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    case VectorFloat:
+      VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      VectExtParamInfo |=
+          XCOFF::TracebackTable::ParmTypeIsVectorFloatBit >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    default:
+      break;
+    }
+
+    // There are only 32bits in the VectExtParamInfo.
+    if (Bits >= 32)
+      break;
+  }
+  return Bits < 32 ? VectExtParamInfo << (32 - Bits) : VectExtParamInfo;
+}
+
+uint32_t PPCFunctionInfo::getParmsType() const {
+  uint32_t ParamsTypeInfo = 0;
+  unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType;
+
+  int Bits = 0;
+  for (const auto &Elt : ParamtersType) {
+
+    if (Elt == FixedType && !HasVectorParms && Bits > 31)
+      break;
+    if ((Elt != FixedType || HasVectorParms) && Bits > 30)
+      break;
+
+    switch (Elt) {
+    case FixedType:
+      if (HasVectorParms) {
+        //'00'  ==> fixed parameter if HasVectorParms is true.
+        ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+        ParamsTypeInfo |=
+            XCOFF::TracebackTable::ParmTypeIsFixedBits >> ShiftBits;
+        Bits += XCOFF::TracebackTable::WidthOfParamType;
       } else {
-      // '0'b => fixed parameter.
-      CopyParamType <<= 1;
+        //'0'  ==> fixed parameter if HasVectorParms is false.
+        ParamsTypeInfo <<= 1;
         ++Bits;
       }
+      break;
+    case ShortFloatingPoint:
+      // '10'b => floating point short parameter.
+      ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      ParamsTypeInfo |=
+          XCOFF::TracebackTable::ParmTypeIsFloatingBits >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    case LongFloatingPoint:
+      // '11'b => floating point long parameter.
+      ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      ParamsTypeInfo |=
+          XCOFF::TracebackTable::ParmTypeIsDoubleBits >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    case VectorChar:
+    case VectorShort:
+    case VectorInt:
+    case VectorFloat:
+      //  '01' ==> vector parameter
+      ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
+      ParamsTypeInfo |=
+          XCOFF::TracebackTable::ParmTypeIsVectorBits >> ShiftBits;
+      Bits += XCOFF::TracebackTable::WidthOfParamType;
+      break;
+    }
   }
 
-  assert(Type != FixedType && "FixedType should already be handled.");
-  if (Bits < 31)
-    ParameterType |= Type << (30 - Bits);
+  return Bits < 32 ? ParamsTypeInfo << (32 - Bits) : ParamsTypeInfo;
 }

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll

 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN:     -mattr=-altivec -xcoff-traceback-table=true < %s | \
+; RUN:     -mattr=+altivec -vec-extabi -xcoff-traceback-table=true < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK-ASM,COMMON %s
 
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \
-; RUN:     -mcpu=pwr4 -mattr=-altivec < %s | \
+; RUN:     -mcpu=pwr4 -mattr=+altivec -vec-extabi  < %s | \
 ; RUN:   FileCheck --check-prefixes=CHECK-FUNC,COMMON %s
 
 define float @bar() #0 {
 entry:
   %fvalue = alloca float, align 4
   %taken = alloca i32, align 4
   %data = alloca i32, align 4
   store float 1.000000e+00, float* %fvalue, align 4
   %0 = load float, float* %fvalue, align 4
   %1 = call float asm "fneg $0,$1\0A\09", "=b,b,~{f31},~{f30},~{f29},~{f28},~{f27}"(float %0)
   store float %1, float* %fvalue, align 4
   store i32 123, i32* %data, align 4
   %2 = load i32, i32* %data, align 4
   %3 = call i32 asm "cntlzw $0, $1\0A\09", "=b,b,~{r31},~{r30},~{r29},~{r28}"(i32 %2)
   store i32 %3, i32* %taken, align 4
   %4 = load i32, i32* %taken, align 4
   %conv = sitofp i32 %4 to float
   %5 = load float, float* %fvalue, align 4
   %add = fadd float %conv, %5
   ret float %add
 }
 
+define <4 x i32> @foov() #0 {
+entry:
+  %taken = alloca <4 x i32>, align 16
+  %data = alloca <4 x i32>, align 16
+  store <4 x i32> <i32 123, i32 0, i32 0, i32 0>, <4 x i32>* %data, align 16
+  call void asm sideeffect "", "~{v31},~{v30},~{v29},~{v28}"() 
+  %0 = load <4 x i32>, <4 x i32>* %taken, align 16
+  ret <4 x i32> %0
+}
+
 ; COMMON:       .vbyte  4, 0x00000000                   # Traceback table begin
 ; COMMON-NEXT:  .byte   0x00                            # Version = 0
 ; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
 ; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
 ; COMMON-NEXT:                                        # +HasTraceBackTableOffset, -IsInternalProcedure
 ; COMMON-NEXT:                                        # -HasControlledStorage, -IsTOCless
 ; COMMON-NEXT:                                        # +IsFloatingPointPresent
 ; COMMON-NEXT:                                        # -IsFloatingPointOperationLogOrAbortEnabled
 ; COMMON-NEXT:  .byte   0x60                            # -IsInterruptHandler, +IsFunctionNamePresent, +IsAllocaUsed
 ; COMMON-NEXT:                                        # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
 ; COMMON-NEXT:  .byte   0x85                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 5
 ; COMMON-NEXT:  .byte   0x04                            # -HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 4
 ; COMMON-NEXT:  .byte   0x00                            # NumberOfFixedParms = 0
 ; COMMON-NEXT:  .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
 ; CHECK-ASM-NEXT:   .vbyte  4, L..bar0-.bar                 # Function size
 ; CHECK-FUNC-NEXT:  .vbyte  4, L..bar0-.bar[PR]             # Function size
 ; COMMON-NEXT:  .vbyte  2, 0x0003                       # Function name len = 3
 ; COMMON-NEXT:  .byte   'b,'a,'r                        # Function Name
 ; COMMON-NEXT:  .byte   0x1f                            # AllocaUsed
 ; COMMON-NEXT:                                        # -- End function
+
+; COMMON:     L..foov0:
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x20                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                         # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                         # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                         # -IsFloatingPointPresent
+; COMMON-NEXT:                                         # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x40                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                         # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x80                            # +HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x00                            # NumberOfFixedParms = 0
+; COMMON-NEXT:  .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
+; CHECK-ASM-NEXT:   .vbyte  4, L..foov0-.foov               # Function size
+; CHECK-FUNC-NEXT:  .vbyte  4, L..foov0-.foov[PR]           # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0004                       # Function name len = 4
+; COMMON-NEXT:  .byte   'f,'o,'o,'v                     # Function Name
+; COMMON-NEXT:  .byte   0x12                            # NumOfVRsSaved = 4, +IsVRSavedOnStack, -HasVarArgs
+; COMMON-NEXT:  .byte   0x01                            # NumOfVectorParams = 0, +HasVMXInstruction
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Vector Parameter type =
+; COMMON-NEXT:                                         # -- End function

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN:     -mattr=+altivec  -vec-extabi -xcoff-traceback-table=true < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-ASM,COMMON %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -function-sections \
+; RUN:     -mcpu=pwr7 -mattr=+altivec -vec-extabi < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-FUNC,COMMON %s
+
+;; #include <altivec.h>
+;; vector float f(vector int vi1, int i1, int i2, float f1, vector float vf,double d1, vector char vc1) {
+;;   return vec_abs(vf);
+;; }
+;; vector float fin(int x) {
+;;  vector float vf ={1.0,1.0,1.0,1.0};
+;;  if (x) return vf;
+;;  return vec_abs(vf);
+;; }
+
+define dso_local <4 x float> @f(<4 x i32> %vi1, i32 signext %i1, i32 signext %i2, float %f1, <4 x float> %vf, double %d1, <16 x i8> %vc1) #0 {
+entry:
+  %__a.addr.i = alloca <4 x float>, align 16
+  %vi1.addr = alloca <4 x i32>, align 16
+  %i1.addr = alloca i32, align 4
+  %i2.addr = alloca i32, align 4
+  %f1.addr = alloca float, align 4
+  %vf.addr = alloca <4 x float>, align 16
+  %d1.addr = alloca double, align 8
+  %vc1.addr = alloca <16 x i8>, align 16
+  store <4 x i32> %vi1, <4 x i32>* %vi1.addr, align 16
+  store i32 %i1, i32* %i1.addr, align 4
+  store i32 %i2, i32* %i2.addr, align 4
+  store float %f1, float* %f1.addr, align 4
+  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
+  store double %d1, double* %d1.addr, align 8
+  store <16 x i8> %vc1, <16 x i8>* %vc1.addr, align 16
+  %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
+  store <4 x float> %0, <4 x float>* %__a.addr.i, align 16
+  %1 = load <4 x float>, <4 x float>* %__a.addr.i, align 16
+  %2 = load <4 x float>, <4 x float>* %__a.addr.i, align 16
+  %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) #2
+  ret <4 x float> %3
+}
+
+define <4 x float> @fin(i32 %x) #0 {
+entry:
+  %__a.addr.i = alloca <4 x float>, align 16
+  %__res.i = alloca <4 x i32>, align 16
+  %retval = alloca <4 x float>, align 16
+  %x.addr = alloca i32, align 4
+  %vf = alloca <4 x float>, align 16
+  store i32 %x, i32* %x.addr, align 4
+  store <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float>* %vf, align 16
+  %0 = load i32, i32* %x.addr, align 4
+  %tobool = icmp ne i32 %0, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %1 = load <4 x float>, <4 x float>* %vf, align 16
+  store <4 x float> %1, <4 x float>* %retval, align 16
+  br label %return
+
+if.end:                                           ; preds = %entry
+  %2 = load <4 x float>, <4 x float>* %vf, align 16
+  store <4 x float> %2, <4 x float>* %__a.addr.i, align 16
+  %3 = load <4 x float>, <4 x float>* %__a.addr.i, align 16
+  %4 = bitcast <4 x float> %3 to <4 x i32>
+  %and.i = and <4 x i32> %4, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+  store <4 x i32> %and.i, <4 x i32>* %__res.i, align 16
+  %5 = load <4 x i32>, <4 x i32>* %__res.i, align 16
+  %6 = bitcast <4 x i32> %5 to <4 x float>
+  store <4 x float> %6, <4 x float>* %retval, align 16
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %7 = load <4 x float>, <4 x float>* %retval, align 16
+  ret <4 x float> %7
+}
+
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
+
+; COMMON:      L..f0:
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                         # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                         # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                         # +IsFloatingPointPresent
+; COMMON-NEXT:                                         # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x40                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                         # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x80                            # +HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x02                            # NumberOfFixedParms = 2
+; COMMON-NEXT:  .byte   0x05                            # NumberOfFPParms = 2, +HasParmsOnStack
+; COMMON-NEXT:  .vbyte  4, 0x42740000                   # Parameter type = v, i, i, f, v, d, v
+; CHECK-ASM-NEXT:  .vbyte  4, L..f0-.f                     # Function size
+; CHECK-FUNC-NEXT: .vbyte  4, L..f0-.f[PR]                 # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0001                       # Function name len = 1
+; COMMON-NEXT:  .byte   102                             # Function Name
+; COMMON-NEXT:  .byte   0x00                            # NumOfVRsSaved = 0, -IsVRSavedOnStack, -HasVarArgs
+; COMMON-NEXT:  .byte   0x07                            # NumOfVectorParams = 3, +HasVMXInstruction
+; COMMON-NEXT:  .vbyte  4, 0xb0000000                   # Vector Parameter type = vi, vf, vc
+
+; COMMON:     L..fin0:
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Traceback table begin
+; COMMON-NEXT:  .byte   0x00                            # Version = 0
+; COMMON-NEXT:  .byte   0x09                            # Language = CPlusPlus
+; COMMON-NEXT:  .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; COMMON-NEXT:                                         # +HasTraceBackTableOffset, -IsInternalProcedure
+; COMMON-NEXT:                                         # -HasControlledStorage, -IsTOCless
+; COMMON-NEXT:                                         # +IsFloatingPointPresent
+; COMMON-NEXT:                                         # -IsFloatingPointOperationLogOrAbortEnabled
+; COMMON-NEXT:  .byte   0x40                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
+; COMMON-NEXT:                                         # OnConditionDirective = 0, -IsCRSaved, -IsLRSaved
+; COMMON-NEXT:  .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
+; COMMON-NEXT:  .byte   0x80                            # +HasVectorInfo, -HasExtensionTable, NumOfGPRsSaved = 0
+; COMMON-NEXT:  .byte   0x01                            # NumberOfFixedParms = 1
+; COMMON-NEXT:  .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Parameter type = i
+; CHECK-ASM-NEXT:       .vbyte  4, L..fin0-.fin                 # Function size
+; CHECK-FUNC-NEXT:      .vbyte  4, L..fin0-.fin[PR]             # Function size
+; COMMON-NEXT:  .vbyte  2, 0x0003                       # Function name len = 3
+; COMMON-NEXT:  .byte   'f,'i,'n                        # Function Name
+; COMMON-NEXT:  .byte   0x00                            # NumOfVRsSaved = 0, -IsVRSavedOnStack, -HasVarArgs
+; COMMON-NEXT:  .byte   0x01                            # NumOfVectorParams = 0, +HasVMXInstruction
+; COMMON-NEXT:  .vbyte  4, 0x00000000                   # Vector Parameter type =

llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll

+;; The purpose of the test case is to test the varargs bit field "has_varargs" of vector info in
+;; traceback table. but since we do not support "variadic arguments for vector types" in backend,
+;; we can not  test the "has_varargs" bit field of the vector info, when the "variadic arguments
+;; for vector types" is supported, the test case need to be changed to test the "has_varargs"
+;;  of vector info.
+
+; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN:     -mattr=+altivec  -vec-extabi -xcoff-traceback-table=true 2>&1 < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK-ASM,COMMON %s 
+
+;; void f(vector float vf, ...) {
+;;}
+
+define void @f(<4 x float> %vf, ...) #0 {
+entry:
+  %vf.addr = alloca <4 x float>, align 16
+  store <4 x float> %vf, <4 x float>* %vf.addr, align 16
+  ret void
+}
+; CHECK-ASM: LLVM ERROR: variadic arguments for vector types are unimplemented for AIX

llvm/test/CodeGen/PowerPC/aix-exception.ll

 ; ASM:    bl .__cxa_end_catch[PR]
 ; ASM:    nop
 ; ASM:    b L..BB1_2
 
 ; ASM:  L.._Z9catchFuncv0:
 ; ASM:    .vbyte  4, 0x00000000                   # Traceback table begin
 ; ASM:    .byte   0x00                            # Version = 0
 ; ASM:    .byte   0x09                            # Language = CPlusPlus
-; ASM:    .byte   0x22                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
+; ASM:    .byte   0x20                            # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
 ; ASM:                                    # +HasTraceBackTableOffset, -IsInternalProcedure
 ; ASM:                                    # -HasControlledStorage, -IsTOCless
-; ASM:                                    # +IsFloatingPointPresent
+; ASM:                                    # -IsFloatingPointPresent
 ; ASM:                                    # -IsFloatingPointOperationLogOrAbortEnabled
 ; ASM:    .byte   0x41                            # -IsInterruptHandler, +IsFunctionNamePresent, -IsAllocaUsed
 ; ASM:                                    # OnConditionDirective = 0, -IsCRSaved, +IsLRSaved
 ; ASM:    .byte   0x80                            # +IsBackChainStored, -IsFixup, NumOfFPRsSaved = 0
 ; ASM:    .byte   0x40                            # -HasVectorInfo, +HasExtensionTable, NumOfGPRsSaved = 0
 ; ASM:    .byte   0x00                            # NumberOfFixedParms = 0
 ; ASM:    .byte   0x01                            # NumberOfFPParms = 0, +HasParmsOnStack
 ; ASM:    .vbyte  4, L.._Z9catchFuncv0-._Z9catchFuncv # Function size

llvm/unittests/Object/XCOFFObjectFileTest.cpp

TEST(XCOFFObjectFileTest, XCOFFTracebackTableAPIParmsType) {
 
   V[6] = 0x01;
   Size = sizeof(V);
   Expected<XCOFFTracebackTable> TTOrErr3 = XCOFFTracebackTable::create(V, Size);
   ASSERT_THAT_EXPECTED(TTOrErr3, Succeeded());
   XCOFFTracebackTable TT3 = *TTOrErr3;
   ASSERT_TRUE(TT3.getParmsType());
   EXPECT_EQ(TT3.getParmsType().getValue(), "d, i, f, f");
+
+  V[6] = 0x04;
+  V[7] = 0x1E;
+  V[8] = 0xAC;
+  V[9] = 0xAA;
+  V[10] = 0xAA;
+  V[11] = 0xAA;
+  Size = sizeof(V);
+  Expected<XCOFFTracebackTable> TTOrErr4 = XCOFFTracebackTable::create(V, Size);
+  ASSERT_THAT_EXPECTED(TTOrErr4, Succeeded());
+  XCOFFTracebackTable TT4 = *TTOrErr4;
+  ASSERT_TRUE(TT4.getParmsType());
+  EXPECT_EQ(TT4.getParmsType().getValue(),
+            "f, f, d, i, i, f, f, f, f, f, f, f, f, f, f, f, f, ...");
 }
 
 const uint8_t TBTableData[] = {
     0x00, 0x00, 0x2A, 0x60, 0x80, 0xc0, 0x03, 0x05, 0x48, 0xc4, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x02, 0x05, 0x05, 0x00, 0x00,
     0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x61, 0x64, 0x64, 0x5f, 0x61, 0x6c,
     0x6c, 0x1f, 0x02, 0x05, 0xf0, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00};
 
TEST(XCOFFObjectFileTest, XCOFFTracebackTableAPIHasVectorInfo) {
 
   EXPECT_EQ(VecExt.getNumberOfVRSaved(), 0);
   EXPECT_TRUE(VecExt.isVRSavedOnStack());
   EXPECT_FALSE(VecExt.hasVarArgs());
 
   EXPECT_EQ(VecExt.getNumberOfVectorParms(), 2u);
   EXPECT_TRUE(VecExt.hasVMXInstruction());
 
-  EXPECT_EQ(VecExt.getVectorParmsInfoString(), "vf, vf");
+  EXPECT_EQ(VecExt.getVectorParmsInfo(), "vf, vf");
 
   ASSERT_TRUE(TT.getExtensionTable());
   EXPECT_EQ(TT.getExtensionTable().getValue(),
             ExtendedTBTableFlag::TB_SSP_CANARY);
 
   EXPECT_EQ(Size, 45u);
 }
 
 TEST(XCOFFObjectFileTest, XCOFFTracebackTableAPIHasVectorInfo1) {
   const uint8_t TBTableData[] = {
-      0x00, 0x00, 0x2A, 0x40, 0x80, 0xc0, 0x03, 0x05, 0x48, 0xc0, 0x00, 0x00,
+      0x00, 0x00, 0x2A, 0x40, 0x80, 0xc0, 0x03, 0x05, 0x48, 0xc5, 0x00, 0x00,
       0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x02, 0x05, 0x05, 0x00, 0x00,
       0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x61, 0x64, 0x64, 0x5f, 0x61, 0x6c,
       0x6c, 0x11, 0x07, 0x90, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00};
   uint64_t Size = sizeof(TBTableData);
   Expected<XCOFFTracebackTable> TTOrErr =
       XCOFFTracebackTable::create(TBTableData, Size);
   ASSERT_THAT_EXPECTED(TTOrErr, Succeeded());
   XCOFFTracebackTable TT = *TTOrErr;
 
   ASSERT_TRUE(TT.getParmsType());
-  EXPECT_EQ(TT.getParmsType().getValue(), "v, i, f, i, d, i");
+  EXPECT_EQ(TT.getParmsType().getValue(), "v, i, f, i, d, i, v, v");
 
   ASSERT_TRUE(TT.getVectorExt());
   TBVectorExt VecExt = TT.getVectorExt().getValue();
 
   EXPECT_EQ(VecExt.getNumberOfVRSaved(), 4);
   EXPECT_FALSE(VecExt.isVRSavedOnStack());
   EXPECT_TRUE(VecExt.hasVarArgs());
 
   EXPECT_EQ(VecExt.getNumberOfVectorParms(), 3u);
   EXPECT_TRUE(VecExt.hasVMXInstruction());
 
-  EXPECT_EQ(VecExt.getVectorParmsInfoString(), "vi, vs, vc");
+  EXPECT_EQ(VecExt.getVectorParmsInfo(), "vi, vs, vc");
 
   ASSERT_TRUE(TT.getExtensionTable());
   EXPECT_EQ(TT.getExtensionTable().getValue(),
             ExtendedTBTableFlag::TB_SSP_CANARY);
 
   EXPECT_EQ(Size, 44u);
 }
 
Expected<XCOFFTracebackTable> TTOrErr =
       XCOFFTracebackTable::create(TBTableData, Size);
 
   EXPECT_THAT_ERROR(
       TTOrErr.takeError(),
       FailedWithMessage(
           "unexpected end of data at offset 0x2c while reading [0x2c, 0x2d)"));
   EXPECT_EQ(Size, 44u);
 }
+
+TEST(XCOFFObjectFileTest, XCOFFTracebackTableErrorAtParameterType) {
+  const uint8_t TBTableData[] = {0x00, 0x00, 0x22, 0x40, 0x80, 0x00, 0x01,
+                                 0x05, 0x58, 0x00, 0x10, 0x00, 0x00, 0x00,
+                                 0x00, 0x40, 0x00, 0x07, 0x61, 0x64, 0x64,
+                                 0x5f, 0x61, 0x6c, 0x6c, 0x00, 0x00, 0x00};
+  uint64_t Size = 28;
+  Expected<XCOFFTracebackTable> TTOrErr =
+      XCOFFTracebackTable::create(TBTableData, Size);
+
+  EXPECT_THAT_ERROR(
+      TTOrErr.takeError(),
+      FailedWithMessage("ParmsType encodes can not map to ParmsNum parameters "
+                        "in parseParmsType."));
+}
+
+TEST(XCOFFObjectFileTest, XCOFFTracebackTableErrorAtParameterTypeWithVecInfo) {
+  const uint8_t TBTableData[] = {
+      0x00, 0x00, 0x2A, 0x40, 0x80, 0xc0, 0x03, 0x05, 0x48, 0xc0, 0x00, 0x10,
+      0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x02, 0x05, 0x05, 0x00, 0x00,
+      0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x61, 0x64, 0x64, 0x5f, 0x61, 0x6c,
+      0x6c, 0x11, 0x07, 0x90, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00};
+  uint64_t Size = 44;
+  Expected<XCOFFTracebackTable> TTOrErr =
+      XCOFFTracebackTable::create(TBTableData, Size);
+
+  EXPECT_THAT_ERROR(
+      TTOrErr.takeError(),
+      FailedWithMessage("ParmsType encodes can not map to ParmsNum parameters "
+                        "in parseParmsTypeWithVecInfo."));
+}
+
+TEST(XCOFFObjectFileTest, XCOFFTracebackTableErrorAtVecParameterType) {
+  const uint8_t TBTableData[] = {
+      0x00, 0x00, 0x2A, 0x40, 0x80, 0xc0, 0x03, 0x05, 0x48, 0xc0, 0x00, 0x00,
+      0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x02, 0x05, 0x05, 0x00, 0x00,
+      0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x61, 0x64, 0x64, 0x5f, 0x61, 0x6c,
+      0x6c, 0x11, 0x07, 0x90, 0x00, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00};
+  uint64_t Size = 44;
+  Expected<XCOFFTracebackTable> TTOrErr =
+      XCOFFTracebackTable::create(TBTableData, Size);
+
+  EXPECT_THAT_ERROR(TTOrErr.takeError(),
+                    FailedWithMessage("ParmsType encodes more than ParmsNum "
+                                      "parameters in parseVectorParmsType."));
+}