[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output

[craig.topper]

Summary

This moves the vtype decoding and printing to RISCVBaseInfo. This keeps all of the decoding code in the same area as the encoding code. This will make it easier to change the decoding for the 1.0 spec in the future.

We're now sharing the printing with the debug output for operands in the assembler. This also fixes that debug output to include the tail and mask agnostic bits. Since the printing code works on the vtype immediate value, we now encode the immediate during parsing and store just the immediate in the operand.

[frasercrmck]

LGTM other than nits.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

754

nit: are these parens needed?

1578

nit: can't remember the llvm style but should these parens be here?

[craig.topper]

Fixed by 045304701bc60620c0c0f79126f7c36d883b63ff. I missed the Differential Revision tag

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

struct SysRegOp {
     const char *Data;
     unsigned Length;
     unsigned Encoding;
     // FIXME: Add the Encoding parsed fields as needed for checks,
     // e.g.: read/write or user/supervisor/machine privileges.
   };
 
   struct VTypeOp {
-    RISCVVSEW Sew;
-    RISCVVLMUL Lmul;
-    bool TailAgnostic;
-    bool MaskAgnostic;
+    unsigned Val;
   };
 
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
     ImmOp Imm;
     struct SysRegOp SysReg;
public:
   bool isRV64() const { return IsRV64; }
 
   unsigned getReg() const override {
     assert(Kind == KindTy::Register && "Invalid type access!");
     return Reg.RegNum.id();
   }
 
   StringRef getSysReg() const {
-    assert(Kind == KindTy::SystemRegister && "Invalid access!");
+    assert(Kind == KindTy::SystemRegister && "Invalid type access!");
     return StringRef(SysReg.Data, SysReg.Length);
   }
 
   const MCExpr *getImm() const {
     assert(Kind == KindTy::Immediate && "Invalid type access!");
     return Imm.Val;
   }
 
   StringRef getToken() const {
     assert(Kind == KindTy::Token && "Invalid type access!");
     return Tok;
   }
 
-  static StringRef getSEWStr(RISCVVSEW Sew) {
-    switch (Sew) {
-    case RISCVVSEW::SEW_8:
-      return "e8";
-    case RISCVVSEW::SEW_16:
-      return "e16";
-    case RISCVVSEW::SEW_32:
-      return "e32";
-    case RISCVVSEW::SEW_64:
-      return "e64";
-    case RISCVVSEW::SEW_128:
-      return "e128";
-    case RISCVVSEW::SEW_256:
-      return "e256";
-    case RISCVVSEW::SEW_512:
-      return "e512";
-    case RISCVVSEW::SEW_1024:
-      return "e1024";
-    }
-    llvm_unreachable("Unknown SEW.");
-  }
-
-  static StringRef getLMULStr(RISCVVLMUL Lmul) {
-    switch (Lmul) {
-    case RISCVVLMUL::LMUL_1:
-      return "m1";
-    case RISCVVLMUL::LMUL_2:
-      return "m2";
-    case RISCVVLMUL::LMUL_4:
-      return "m4";
-    case RISCVVLMUL::LMUL_8:
-      return "m8";
-    case RISCVVLMUL::LMUL_F2:
-      return "mf2";
-    case RISCVVLMUL::LMUL_F4:
-      return "mf4";
-    case RISCVVLMUL::LMUL_F8:
-      return "mf8";
-    }
-    llvm_unreachable("Unknown LMUL.");
-  }
-
-  StringRef getVType(SmallString<32> &Buf) const {
-    assert(Kind == KindTy::VType && "Invalid access!");
-    Buf.append(getSEWStr(VType.Sew));
-    Buf.append(",");
-    Buf.append(getLMULStr(VType.Lmul));
-
-    return Buf.str();
+  unsigned getVType() const {
+    assert(Kind == KindTy::VType && "Invalid type access!");
+    return VType.Val;
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case KindTy::Immediate:
       OS << *getImm();
       break;
     case KindTy::Register:
       OS << "<register x";
       OS << getReg() << ">";
       break;
     case KindTy::Token:
       OS << "'" << getToken() << "'";
       break;
     case KindTy::SystemRegister:
       OS << "<sysreg: " << getSysReg() << '>';
       break;
-    case KindTy::VType:
-      SmallString<32> VTypeBuf;
-      OS << "<vtype: " << getVType(VTypeBuf) << '>';
+    case KindTy::VType: {
+      OS << "<vtype: ";
+      RISCVVType::printVType(getVType(), OS);
+      OS << '>';
       break;
     }
     }
+  }
 
   static std::unique_ptr<RISCVOperand> createToken(StringRef Str, SMLoc S,
                                                    bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::Token);
     Op->Tok = Str;
     Op->StartLoc = S;
     Op->EndLoc = S;
     Op->IsRV64 = IsRV64;
createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) {
     Op->SysReg.Data = Str.data();
     Op->SysReg.Length = Str.size();
     Op->SysReg.Encoding = Encoding;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
-  static std::unique_ptr<RISCVOperand>
-  createVType(unsigned Sew, unsigned Lmul, bool Fractional, bool TailAgnostic,
-              bool MaskAgnostic, SMLoc S, bool IsRV64) {
+  static std::unique_ptr<RISCVOperand> createVType(unsigned VTypeI, SMLoc S,
+                                                   bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
-    unsigned SewLog2 = Log2_32(Sew / 8);
-    unsigned LmulLog2 = Log2_32(Lmul);
-    Op->VType.Sew = static_cast<RISCVVSEW>(SewLog2);
-    if (Fractional) {
-      unsigned Flmul = 8 - LmulLog2;
-      Op->VType.Lmul = static_cast<RISCVVLMUL>(Flmul);
-    } else {
-      Op->VType.Lmul = static_cast<RISCVVLMUL>(LmulLog2);
-    }
-    Op->VType.TailAgnostic = TailAgnostic;
-    Op->VType.MaskAgnostic = MaskAgnostic;
+    Op->VType.Val = VTypeI;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     assert(Expr && "Expr shouldn't be null!");
     int64_t Imm = 0;
public:
 
   void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(SysReg.Encoding));
   }
 
   void addVTypeIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    unsigned VTypeI = RISCVVType::encodeVTYPE(
-        VType.Lmul, VType.Sew, VType.TailAgnostic, VType.MaskAgnostic);
-    Inst.addOperand(MCOperand::createImm(VTypeI));
+    Inst.addOperand(MCOperand::createImm(getVType()));
   }
 
   // Returns the rounding mode represented by this RISCVOperand. Should only
   // be called after checking isFRMArg.
   RISCVFPRndMode::RoundingMode getRoundingMode() const {
     // isFRMArg has validated the operand, meaning this cast is safe.
     auto SE = cast<MCSymbolRefExpr>(getImm());
     RISCVFPRndMode::RoundingMode FRM =
else if (Name == "mu")
     MaskAgnostic = false;
   else
     return MatchOperand_NoMatch;
   getLexer().Lex();
 
   if (getLexer().getKind() != AsmToken::EndOfStatement)
     return MatchOperand_NoMatch;
 
-  Operands.push_back(RISCVOperand::createVType(
-      Sew, Lmul, Fractional, TailAgnostic, MaskAgnostic, S, isRV64()));
+  unsigned SewLog2 = Log2_32(Sew / 8);
+  unsigned LmulLog2 = Log2_32(Lmul);
+  RISCVVSEW VSEW = static_cast<RISCVVSEW>(SewLog2);
+  RISCVVLMUL VLMUL;
+  if (Fractional) {
+    unsigned Flmul = 8 - LmulLog2;
+    VLMUL = static_cast<RISCVVLMUL>(Flmul);
+  } else {
+    VLMUL = static_cast<RISCVVLMUL>(LmulLog2);
+  }
+
+  unsigned VTypeI =
+      RISCVVType::encodeVTYPE(VLMUL, VSEW, TailAgnostic, MaskAgnostic);
+  Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64()));
 
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
   printRegName(O, MO.getReg());
   O << ")";
   return;
 }
 
 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
-  unsigned Sew = (Imm >> 2) & 0x7;
-  unsigned Lmul = Imm & 0x3;
-  bool Fractional = (Imm >> 5) & 0x1;
-
-  Sew = 0x1 << (Sew + 3);
-  O << "e" << Sew;
-  if (Fractional) {
-    Lmul = 4 - Lmul;
-    Lmul = 0x1 << Lmul;
-    O << ",mf" << Lmul;
-  } else {
-    Lmul = 0x1 << Lmul;
-    O << ",m" << Lmul;
-  }
-  bool TailAgnostic = Imm & 0x40;
-  bool MaskedoffAgnostic = Imm & 0x80;
-  if (TailAgnostic)
-    O << ",ta";
-  else
-    O << ",tu";
-  if (MaskedoffAgnostic)
-    O << ",ma";
-  else
-    O << ",mu";
+  RISCVVType::printVType(Imm, O);
 }
 
 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNo);
 
   assert(MO.isReg() && "printVMaskReg can only print register operands");

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

unsigned VTypeI =
       ((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
   if (TailAgnostic)
     VTypeI |= 0x40;
   if (MaskAgnostic)
     VTypeI |= 0x80;
 
   return VTypeI;
 }
+
+// TODO: This format will change for the V extensions spec v1.0.
+inline static RISCVVLMUL getVLMUL(unsigned VType) {
+  unsigned VLMUL = (VType & 0x3) | ((VType & 0x20) >> 3);
+  return static_cast<RISCVVLMUL>(VLMUL);
+}
+
+inline static RISCVVSEW getVSEW(unsigned VType) {
+  unsigned VSEW = (VType >> 2) & 0x7;
+  return static_cast<RISCVVSEW>(VSEW);
+}
+
+inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
+
+inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
+
+void printVType(unsigned VType, raw_ostream &OS);
+
 } // namespace RISCVVType
 
 namespace RISCVVPseudosTable {
 
 struct PseudoInfo {
   unsigned int Pseudo;
   unsigned int BaseInstr;
   uint8_t VLIndex;

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

 
 namespace RISCVVPseudosTable {
 
 #define GET_RISCVVPseudosTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 
 } // namespace RISCVVPseudosTable
 
+void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
+  RISCVVSEW VSEW = getVSEW(VType);
+  RISCVVLMUL VLMUL = getVLMUL(VType);
+
+  unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3);
+  OS << "e" << Sew;
+
+  switch (VLMUL) {
+  case RISCVVLMUL::LMUL_1:
+  case RISCVVLMUL::LMUL_2:
+  case RISCVVLMUL::LMUL_4:
+  case RISCVVLMUL::LMUL_8: {
+    unsigned LMul = 1 << static_cast<unsigned>(VLMUL);
+    OS << ",m" << LMul;
+    break;
+  }
+  case RISCVVLMUL::LMUL_F2:
+  case RISCVVLMUL::LMUL_F4:
+  case RISCVVLMUL::LMUL_F8: {
+    unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL));
+    OS << ",mf" << LMul;
+    break;
+  }
+  }
+
+  if (isTailAgnostic(VType))
+    OS << ",ta";
+  else
+    OS << ",tu";
+
+  if (isMaskAgnostic(VType))
+    OS << ",ma";
+  else
+    OS << ",mu";
+}
+
 } // namespace llvm