[RegisterClassInfo] Return non-zero for RC without allocatable reg

[jsji]

Summary

In some case, the RC may have 0 allocatable reg.
eg: VRSAVERC in PowerPC, which has only 1 reg, but it is also reserved.

The curreent implementation will keep calling the computePSetLimit because
getRegPressureSetLimit assume computePSetLimit will return a non-zero value.

The fix simply early return the value from TableGen for such special case.

[jsji]

Gentle ping...

[jsji]

Gentle ping...

[RKSimon]

llvm/lib/CodeGen/RegisterClassInfo.cpp

190–191

Pull out the repeated getNumAllocatableRegs and getRegPressureSetLimit calls.

[jsji]

Address comments. Thanks Simon.

[RKSimon]

LGTM with one minor

llvm/lib/CodeGen/RegisterClassInfo.cpp

193

Please can you add a comment explaining the early-out?

[jsji]

Add comments.

[jsji]

Update comments.

llvm/lib/CodeGen/RegisterClassInfo.cpp

for (const TargetRegisterClass *C : TRI->regclasses()) {
     // For efficiency, only compute the set order for the largest set.
     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
     if (!RC || NUnits > NumRCUnits) {
       RC = C;
       NumRCUnits = NUnits;
     }
   }
   assert(RC && "Failed to find register class");
   compute(RC);
-  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
-  return TRI->getRegPressureSetLimit(*MF, Idx) -
-         TRI->getRegClassWeight(RC).RegWeight * NReserved;
+  unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
+  unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
+  // If all the regs are reserved, return raw RegPressureSetLimit.
+  // One example is VRSAVERC in PowerPC.
+  // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
+  // return non-zero value.
+  if (NAllocatableRegs == 0)
+    return RegPressureSetLimit;
+  unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
+  return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
 }

llvm/test/CodeGen/PowerPC/compute-regpressure.ll

 ; REQUIRES: asserts
 ; RUN: llc -debug-only=regalloc < %s 2>&1 |FileCheck %s --check-prefix=DEBUG
 
-; DEBUG-COUNT-3:         AllocationOrder(VRSAVERC) = [ ]
+; DEBUG-COUNT-1:         AllocationOrder(VRSAVERC) = [ ]
 
 target triple = "powerpc64le-unknown-linux-gnu"
 
 define hidden fastcc void @test() {
 freescalar:
   %0 = load i32, i32* undef, align 4
   br label %if.end420