[RISCV] Preserve Assembler Source Locations

[lenary]

Summary

We weren't using the IDLoc available everywhere in the RISCVAsmParser. This
means we were losing potential source code location information.

This commit adds a way of providing the location (only once) to MCInstBuilder,
and uses that interface within the RISCVAsmParser, so location information isn't
lost.

I *think* (but I'm not 100% sure) this would manifest as a lack of location
information for e.g. call and li instructions when assembled into object
files.

[craig.topper]

Aren't MCInst locations only used for diagnostics? I don't think they affect object files.

[lenary]

I was weirded out by seeing debug info left as unused arguments, but I went looking in AsmParser.cpp and it does something completely different for emitting debug info, which I wasn't expecting.

llvm/include/llvm/MC/MCInstBuilder.h

 // MCInsts.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCINSTBUILDER_H
 #define LLVM_MC_MCINSTBUILDER_H
 
 #include "llvm/MC/MCInst.h"
+#include "llvm/Support/SMLoc.h"
 
 namespace llvm {
 
 class MCInstBuilder {
   MCInst Inst;
 
 public:
   /// Create a new MCInstBuilder for an MCInst with a specific opcode.
   MCInstBuilder(unsigned Opcode) {
     Inst.setOpcode(Opcode);
   }
 
+  MCInstBuilder(unsigned Opcode, SMLoc Loc) {
+    Inst.setOpcode(Opcode);
+    Inst.setLoc(Loc);
+  }
+
   /// Add a new register operand.
   MCInstBuilder &addReg(unsigned Reg) {
     Inst.addOperand(MCOperand::createReg(Reg));
     return *this;
   }
 
   /// Add a new integer immediate operand.
   MCInstBuilder &addImm(int64_t Val) {

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

class RISCVAsmParser : public MCTargetAsmParser {
   bool ParseDirective(AsmToken DirectiveID) override;
 
   // Helper to actually emit an instruction to the MCStreamer. Also, when
   // possible, compression of the instruction is performed.
   void emitToStreamer(MCStreamer &S, const MCInst &Inst);
 
   // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that
   // synthesize the desired immedate value into the destination register.
-  void emitLoadImm(MCRegister DestReg, int64_t Value, MCStreamer &Out);
+  void emitLoadImm(MCRegister DestReg, int64_t Value, SMLoc IDLoc,
+                   MCStreamer &Out);
 
   // Helper to emit a combination of AUIPC and SecondOpcode. Used to implement
   // helpers such as emitLoadLocalAddress and emitLoadAddress.
   void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
                          const MCExpr *Symbol, RISCVMCExpr::VariantKind VKHi,
                          unsigned SecondOpcode, SMLoc IDLoc, MCStreamer &Out);
 
   // Helper to emit pseudo instruction "lla" used in PC-rel addressing.

 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
 }
 
-void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
+void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value, SMLoc IDLoc,
                                  MCStreamer &Out) {
   RISCVMatInt::InstSeq Seq;
   RISCVMatInt::generateInstSeq(Value, isRV64(), Seq);
 
   MCRegister SrcReg = RISCV::X0;
   for (RISCVMatInt::Inst &Inst : Seq) {
     if (Inst.Opc == RISCV::LUI) {
       emitToStreamer(
-          Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
+          Out,
+          MCInstBuilder(RISCV::LUI, IDLoc).addReg(DestReg).addImm(Inst.Imm));
     } else {
-      emitToStreamer(
-          Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
-                   Inst.Imm));
+      emitToStreamer(Out, MCInstBuilder(Inst.Opc, IDLoc)
+                              .addReg(DestReg)
+                              .addReg(SrcReg)
+                              .addImm(Inst.Imm));
     }
 
     // Only the first instruction has X0 as its source.
     SrcReg = DestReg;
   }
 }
 
 void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
                                        const MCExpr *Symbol,
                                        RISCVMCExpr::VariantKind VKHi,
                                        unsigned SecondOpcode, SMLoc IDLoc,
                                        MCStreamer &Out) {
   // A pair of instructions for PC-relative addressing; expands to
   //   TmpLabel: AUIPC TmpReg, VKHi(symbol)
   //             OP DestReg, TmpReg, %pcrel_lo(TmpLabel)
   MCContext &Ctx = getContext();
 
   MCSymbol *TmpLabel = Ctx.createTempSymbol(
       "pcrel_hi", /* AlwaysAddSuffix */ true, /* CanBeUnnamed */ false);
   Out.emitLabel(TmpLabel);
 
   const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx);
   emitToStreamer(
-      Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi));
+      Out,
+      MCInstBuilder(RISCV::AUIPC, IDLoc).addOperand(TmpReg).addExpr(SymbolHi));
 
   const MCExpr *RefToLinkTmpLabel =
       RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx),
                           RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx);
 
-  emitToStreamer(Out, MCInstBuilder(SecondOpcode)
+  emitToStreamer(Out, MCInstBuilder(SecondOpcode, IDLoc)
                           .addOperand(DestReg)
                           .addOperand(TmpReg)
                           .addExpr(RefToLinkTmpLabel));
 }
 
 void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out) {
   // The load local address pseudo-instruction "lla" is used in PC-relative
bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
   default:
     break;
   case RISCV::PseudoLI: {
     MCRegister Reg = Inst.getOperand(0).getReg();
     const MCOperand &Op1 = Inst.getOperand(1);
     if (Op1.isExpr()) {
       // We must have li reg, %lo(sym) or li reg, %pcrel_lo(sym) or similar.
       // Just convert to an addi. This allows compatibility with gas.
-      emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
+      emitToStreamer(Out, MCInstBuilder(RISCV::ADDI, IDLoc)
                               .addReg(Reg)
                               .addReg(RISCV::X0)
                               .addExpr(Op1.getExpr()));
       return false;
     }
     int64_t Imm = Inst.getOperand(1).getImm();
     // On RV32 the immediate here can either be a signed or an unsigned
     // 32-bit number. Sign extension has to be performed to ensure that Imm
     // represents the expected signed 64-bit number.
     if (!isRV64())
       Imm = SignExtend64<32>(Imm);
-    emitLoadImm(Reg, Imm, Out);
+    emitLoadImm(Reg, Imm, IDLoc, Out);
     return false;
   }
   case RISCV::PseudoLLA:
     emitLoadLocalAddress(Inst, IDLoc, Out);
     return false;
   case RISCV::PseudoLA:
     emitLoadAddress(Inst, IDLoc, Out);
     return false;