[RISCV] Remove DIVUW/REMUW patterns that don't seem right

[craig.topper]

Summary

These patterns are looking for DIVUW/REMUW with inputs zero extended from 32 bits to 64 and the result being zero extended from 32 bits to 64 bits. This is selected to a DIVUW/REMUW instruction.

As far as I can tell DIVUW/REMUW will sign extend bit 31 in the result. So this isel pattern would only work if the pattern guaranteed that bit 31 of the result was zero so that sign extend would produce zeros. I don't believe the input being zero extended from 32 to 64 bits guarantee that. For example won't (divuw 0xffffffff, 1) produce 0xffffffffffffffff? Similarly won't (remuw 0x80000000, 0xffffffff) produce 0xffffffff80000000?

[craig.topper]

I misread that this was producing DIVU/REMU. Nevermind.

[craig.topper]

Though it probably isn't safe that we're matching (and X, 0xffffffff) on the input due to zexti32 handling both assertzext and and X, 0xffffffff. Removing an and seems wrong.

llvm/lib/Target/RISCV/RISCVInstrInfoM.td

 let Predicates = [HasStdExtM, IsRV64] in {
 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
           (MULW GPR:$rs1, GPR:$rs2)>;
 
 def : PatGprGpr<riscv_divw, DIVW>;
 def : PatGprGpr<riscv_divuw, DIVUW>;
 def : PatGprGpr<riscv_remuw, REMUW>;
 
-// Handle the specific cases where using DIVU/REMU would be correct and result
-// in fewer instructions than emitting DIVUW/REMUW then zero-extending the
-// result.
-def : Pat<(zexti32 (riscv_divuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
-          (DIVU GPR:$rs1, GPR:$rs2)>;
-def : Pat<(zexti32 (riscv_remuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
-          (REMU GPR:$rs1, GPR:$rs2)>;
-
 // Although the sexti32 operands may not have originated from an i32 srem,
 // this pattern is safe as it is impossible for two sign extended inputs to
 // produce a result where res[63:32]=0 and res[31]=1.
 def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
           (REMW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
                             (sexti32 GPR:$rs2)), i32),
           (REMW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtM, IsRV64]

llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
 }
 
 define zeroext i32 @zext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
 ; RV64IM-LABEL: zext_divuw_zext_zext:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    divu a0, a0, a1
+; RV64IM-NEXT:    divuw a0, a0, a1
+; RV64IM-NEXT:    slli a0, a0, 32
+; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
 }
 
 define i32 @aext_divw_aext_aext(i32 %a, i32 %b) nounwind {
 ; RV64IM-LABEL: aext_divw_aext_aext:
 ; RV64IM:       # %bb.0:

 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
 }
 
 define zeroext i32 @zext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
 ; RV64IM-LABEL: zext_remuw_zext_zext:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    remu a0, a0, a1
+; RV64IM-NEXT:    remuw a0, a0, a1
+; RV64IM-NEXT:    slli a0, a0, 32
+; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
 }