[X86] Do not allow FixupSetCC to relax constraints

[hvdijk]

Summary

The build bots caught two additional pre-existing problems exposed by the test change part of my change https://reviews.llvm.org/D91339, when expensive checks are enabled. https://reviews.llvm.org/D91924 fixes one of them, this fixes the other.

FixupSetCC will change code in the form of

%setcc = SETCCr ...
%ext1 = MOVZX32rr8 %setcc

to

%zero = MOV32r0
%setcc = SETCCr ...
%ext2 = INSERT_SUBREG %zero, %setcc, %subreg.sub_8bit

and replace uses of %ext1 with %ext2.

The register class for %ext2 did not take into account any constraints on %ext1, which may have been required by its uses. This change ensures that the original constraints are honoured, by instead of creating a new %ext2 register, reusing %ext1 and further constraining it as needed. This requires a slight reorganisation to account for the fact that it is possible for the constraining to fail, in which case no changes should be made.

[hvdijk]

As requested by @RKSimon, added -verify-machineinstrs to test/CodeGen/X86/pic.ll so that the problem is visible even when expensive checks are disabled.

[hvdijk]

Fix FileCheck syntax at the same time, using CHECK-X32-DAG rather than CHECK-DAG-X32 that @pengfei noticed in D91339 after it had been committed already.

[RKSimon]

In D91933#2410379, @hvdijk wrote:

Fix FileCheck syntax at the same time, using CHECK-X32-DAG rather than CHECK-DAG-X32 that @pengfei noticed in D91339 after it had been committed already.

I pushed this fix in rG40783839e63a

[RKSimon]

llvm/lib/Target/X86/X86FixupSetCC.cpp

104–111

Add a comment for this early-out

[hvdijk]

Add a comment about skipping the optimization when constraining fails.

[hvdijk]

llvm/lib/Target/X86/X86FixupSetCC.cpp

104–111

Sure, done.

[RKSimon]

LGTM - cheers.

If possible, please commit the pic.ll fix as a separate followup.

[hvdijk]

In D91933#2421234, @RKSimon wrote:

If possible, please commit the pic.ll fix as a separate followup.

Sure, will do.

llvm/lib/Target/X86/X86FixupSetCC.cpp

for (auto &MI : MBB) {
       // We'd like to put something that clobbers eflags directly before
       // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
       // it, itself, by definition, clobbers eflags. But it may happen that
       // FlagsDefMI also *uses* eflags, in which case the transformation is
       // invalid.
       if (FlagsDefMI->readsRegister(X86::EFLAGS))
         continue;
 
-      ++NumSubstZexts;
-      Changed = true;
-
       // On 32-bit, we need to be careful to force an ABCD register.
       const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
                                           ? &X86::GR32RegClass
                                           : &X86::GR32_ABCDRegClass;
-      Register ZeroReg = MRI->createVirtualRegister(RC);
-      Register InsertReg = MRI->createVirtualRegister(RC);
+      if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {
+        // If we cannot constrain the register, we would need an additional copy
+        // and are better off keeping the MOVZX32rr8 we have now.
+        continue;
+      }
+
+      ++NumSubstZexts;
+      Changed = true;
 
       // Initialize a register with 0. This must go before the eflags def
+      Register ZeroReg = MRI->createVirtualRegister(RC);
       BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
               ZeroReg);
 
       // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
       // the setcc result into the low byte of the zeroed register.
       BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
-              TII->get(X86::INSERT_SUBREG), InsertReg)
+              TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg())
           .addReg(ZeroReg)
           .addReg(MI.getOperand(0).getReg())
           .addImm(X86::sub_8bit);
-      MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
       ToErase.push_back(ZExt);
     }
   }
 
   for (auto &I : ToErase)
     I->eraseFromParent();
 
   return Changed;
 }