Multiple preprocessor fixes for libunwind on PowerPC*.

[Bdragon28]

Summary

• Remove misnamed PPC64_HAS_VMX in preference of directly checking defined(__VSX__).

libunwind was using "VMX" to mean "VSX". "VMX" is just another name for Altivec, while "VSX" is the vector-scalar extensions first used in POWER7. Exposing a "PPC64_HAS_VMX" define was misleading and incorrect.

• Add defined(__ALTIVEC__) guards around vector register operations to fix non-altivec CPUS such as the e5500.

When compiling for certain Book-E processors such as the e5500, we want to skip vector save/restore, as the Altivec registers are illegal on non-Altivec implementations.

• Add !defined(__NO_FPRS__) guards around traditional floating-point save/restore.

When compiling for powerpcspe, we cannot access floating point registers, as there aren't any. (The SPE on e500v2 is a 64-bit extension of the GPRs, and it doesn't have the normal floating-point registers at all.)
This fixes building for powerpcspe, although no actual handling for SPE save/restore is written yet.

[Bdragon28]

libunwind/src/Registers.hpp

1522

#elif rather. Not sure why I had a typo in my local tree.

[MaskRay]

Looks good to me. (+@luporl who added PPC64_HAS_VMX)

[luporl]

Looks good to me. I guess I didn't know about __VSX__ back when I added PPC64_HAS_VMX.

[compnerd]

Thanks @Bdragon28, this definitely is a nice cleanup (and fix). Please remember to fix the #elseif to a #elif.

[Bdragon28]

Fixing typo.

[Bdragon28]

OK, patch updated with the typo fix.

The !__ALTIVEC__ case has been tested on an AmigaONE X5000. I will test the __NO_FPRS__ case on my RB800 later tonight. (Test to verify that it resolves the SIGILL, that is. The actual SPE bits will come later.)

Note: I do not have commit access.

[MaskRay]

In D91906#2412809, @Bdragon28 wrote:

OK, patch updated with the typo fix.

The !__ALTIVEC__ case has been tested on an AmigaONE X5000. I will test the __NO_FPRS__ case on my RB800 later tonight. (Test to verify that it resolves the SIGILL, that is. The actual SPE bits will come later.)

Note: I do not have commit access.

I'll do it:)

libunwind/src/Registers.hpp

 }
 
 inline void Registers_ppc64::setFloatRegister(int regNum, double value) {
   assert(validFloatRegister(regNum));
   _vectorScalarRegisters[regNum - UNW_PPC64_F0].asfloat.f = value;
 }
 
 inline bool Registers_ppc64::validVectorRegister(int regNum) const {
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
   if (regNum >= UNW_PPC64_VS0 && regNum <= UNW_PPC64_VS31)
     return true;
   if (regNum >= UNW_PPC64_VS32 && regNum <= UNW_PPC64_VS63)
     return true;
-#else
+#elif defined(__ALTIVEC__)
   if (regNum >= UNW_PPC64_V0 && regNum <= UNW_PPC64_V31)
     return true;
 #endif
   return false;
 }
 
 inline int Registers_ppc64::getVectorRegNum(int num)
 {

libunwind/src/UnwindRegistersRestore.S

#define PPC64_LR(n) \
   PPC64_LR(25)
   PPC64_LR(26)
   PPC64_LR(27)
   PPC64_LR(28)
   PPC64_LR(29)
   PPC64_LR(30)
   PPC64_LR(31)
 
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
 
   // restore VS registers
   // (note that this also restores floating point registers and V registers,
   // because part of VS is mapped to these registers)
 
   addi  %r4, %r3, PPC64_OFFS_FP
 
 // load VS register
#define PPC64_LF(n) \
   PPC64_LF(25)
   PPC64_LF(26)
   PPC64_LF(27)
   PPC64_LF(28)
   PPC64_LF(29)
   PPC64_LF(30)
   PPC64_LF(31)
 
+#if defined(__ALTIVEC__)
   // restore vector registers if any are in use
   ld    %r5, PPC64_OFFS_VRSAVE(%r3)   // test VRsave
   cmpwi %r5, 0
   beq   Lnovec
 
   subi  %r4, %r1, 16
   // r4 is now a 16-byte aligned pointer into the red zone
   // the _vectorScalarRegisters may not be 16-byte aligned
PPC64_CLV_UNALIGNED_BOTTOM(n)
   PPC64_CLV_UNALIGNEDh(26)
   PPC64_CLV_UNALIGNEDh(27)
   PPC64_CLV_UNALIGNEDh(28)
   PPC64_CLV_UNALIGNEDh(29)
   PPC64_CLV_UNALIGNEDh(30)
   PPC64_CLV_UNALIGNEDh(31)
 
 #endif
+#endif
 
 Lnovec:
   ld    %r0, PPC64_OFFS_CR(%r3)
   mtcr  %r0
   ld    %r0, PPC64_OFFS_SRR0(%r3)
   mtctr %r0
 
   PPC64_LR(0)
//
   lwz     %r25,108(%r3)
   lwz     %r26,112(%r3)
   lwz     %r27,116(%r3)
   lwz     %r28,120(%r3)
   lwz     %r29,124(%r3)
   lwz     %r30,128(%r3)
   lwz     %r31,132(%r3)
 
+#ifndef __NO_FPRS__
   // restore float registers
   lfd     %f0, 160(%r3)
   lfd     %f1, 168(%r3)
   lfd     %f2, 176(%r3)
   lfd     %f3, 184(%r3)
   lfd     %f4, 192(%r3)
   lfd     %f5, 200(%r3)
   lfd     %f6, 208(%r3)
#ifndef __NO_FPRS__
   lfd     %f24,352(%r3)
   lfd     %f25,360(%r3)
   lfd     %f26,368(%r3)
   lfd     %f27,376(%r3)
   lfd     %f28,384(%r3)
   lfd     %f29,392(%r3)
   lfd     %f30,400(%r3)
   lfd     %f31,408(%r3)
+#endif
 
+#if defined(__ALTIVEC__)
   // restore vector registers if any are in use
   lwz     %r5, 156(%r3)       // test VRsave
   cmpwi   %r5, 0
   beq     Lnovec
 
   subi    %r4, %r1, 16
   rlwinm  %r4, %r4, 0, 0, 27  // mask low 4-bits
   // r4 is now a 16-byte aligned pointer into the red zone
#define LOAD_VECTOR_UNALIGNEDh(_index) \
   LOAD_VECTOR_UNALIGNEDh(24)
   LOAD_VECTOR_UNALIGNEDh(25)
   LOAD_VECTOR_UNALIGNEDh(26)
   LOAD_VECTOR_UNALIGNEDh(27)
   LOAD_VECTOR_UNALIGNEDh(28)
   LOAD_VECTOR_UNALIGNEDh(29)
   LOAD_VECTOR_UNALIGNEDh(30)
   LOAD_VECTOR_UNALIGNEDh(31)
+#endif
 
 Lnovec:
   lwz     %r0, 136(%r3)   // __cr
   mtcr    %r0
   lwz     %r0, 148(%r3)   // __ctr
   mtctr   %r0
   lwz     %r0,   0(%r3)   // __ssr0
   mtctr   %r0

libunwind/src/UnwindRegistersSave.S

#define PPC64_STR(n) \
   std   %r0,  PPC64_OFFS_XER(%r3)
   mflr  %r0
   std   %r0,  PPC64_OFFS_LR(%r3)
   mfctr %r0
   std   %r0,  PPC64_OFFS_CTR(%r3)
   mfvrsave    %r0
   std   %r0,  PPC64_OFFS_VRSAVE(%r3)
 
-#ifdef PPC64_HAS_VMX
+#if defined(__VSX__)
   // save VS registers
   // (note that this also saves floating point registers and V registers,
   // because part of VS is mapped to these registers)
 
   addi  %r4, %r3, PPC64_OFFS_FP
 
 // store VS register
 #define PPC64_STVS(n)      \
#define PPC64_STF(n) \
   PPC64_STF(25)
   PPC64_STF(26)
   PPC64_STF(27)
   PPC64_STF(28)
   PPC64_STF(29)
   PPC64_STF(30)
   PPC64_STF(31)
 
+#if defined(__ALTIVEC__)
   // save vector registers
 
   // Use 16-bytes below the stack pointer as an
   // aligned buffer to save each vector register.
   // Note that the stack pointer is always 16-byte aligned.
   subi  %r4, %r1, 16
 
 #define PPC64_STV_UNALIGNED(n)                 \
#define PPC64_STV_UNALIGNED(n)                 \
   PPC64_STV_UNALIGNED(26)
   PPC64_STV_UNALIGNED(27)
   PPC64_STV_UNALIGNED(28)
   PPC64_STV_UNALIGNED(29)
   PPC64_STV_UNALIGNED(30)
   PPC64_STV_UNALIGNED(31)
 
 #endif
+#endif
 
   li    %r3,  0   // return UNW_ESUCCESS
   blr
 
 
 #elif defined(__ppc__)
 
 //
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   stw     %r0, 156(%r3)
   // save CR registers
   mfcr    %r0
   stw     %r0, 136(%r3)
   // save CTR register
   mfctr   %r0
   stw     %r0, 148(%r3)
 
+#if !defined(__NO_FPRS__)
   // save float registers
   stfd    %f0, 160(%r3)
   stfd    %f1, 168(%r3)
   stfd    %f2, 176(%r3)
   stfd    %f3, 184(%r3)
   stfd    %f4, 192(%r3)
   stfd    %f5, 200(%r3)
   stfd    %f6, 208(%r3)
#if !defined(__NO_FPRS__)
   stfd    %f24,352(%r3)
   stfd    %f25,360(%r3)
   stfd    %f26,368(%r3)
   stfd    %f27,376(%r3)
   stfd    %f28,384(%r3)
   stfd    %f29,392(%r3)
   stfd    %f30,400(%r3)
   stfd    %f31,408(%r3)
+#endif
 
-
+#if defined(__ALTIVEC__)
   // save vector registers
 
   subi    %r4, %r1, 16
   rlwinm  %r4, %r4, 0, 0, 27  // mask low 4-bits
   // r4 is now a 16-byte aligned pointer into the red zone
 
 #define SAVE_VECTOR_UNALIGNED(_vec, _offset) \
   stvx    _vec, 0, %r4          SEPARATOR \
#define SAVE_VECTOR_UNALIGNED(_vec, _offset) \
   SAVE_VECTOR_UNALIGNED(%v24, 424+0x180)
   SAVE_VECTOR_UNALIGNED(%v25, 424+0x190)
   SAVE_VECTOR_UNALIGNED(%v26, 424+0x1A0)
   SAVE_VECTOR_UNALIGNED(%v27, 424+0x1B0)
   SAVE_VECTOR_UNALIGNED(%v28, 424+0x1C0)
   SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
   SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
   SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
+#endif
 
   li      %r3, 0  // return UNW_ESUCCESS
   blr
 
 
 #elif defined(__aarch64__)
 
 //

libunwind/src/assembly.h

 #define PPC64_OFFS_SRR0   0
 #define PPC64_OFFS_CR     272
 #define PPC64_OFFS_XER    280
 #define PPC64_OFFS_LR     288
 #define PPC64_OFFS_CTR    296
 #define PPC64_OFFS_VRSAVE 304
 #define PPC64_OFFS_FP     312
 #define PPC64_OFFS_V      824
-#ifdef _ARCH_PWR8
-#define PPC64_HAS_VMX
-#endif
 #elif defined(__APPLE__) && defined(__aarch64__)
 #define SEPARATOR %%
 #else
 #define SEPARATOR ;
 #endif
 
 #if defined(__powerpc64__) && (!defined(_CALL_ELF) || _CALL_ELF == 1)
 #define PPC64_OPD1 .section .opd,"aw",@progbits SEPARATOR

libunwind/src/config.h

#if defined(__i386__) || defined(__x86_64__) ||                                \
     defined(__mips__) ||                                                       \
     defined(__riscv) ||                                                        \
     defined(__hexagon__)
 #if !defined(_LIBUNWIND_BUILD_SJLJ_APIS)
 #define _LIBUNWIND_BUILD_ZERO_COST_APIS
 #endif
 #endif
 
-#if defined(__powerpc64__) && defined(_ARCH_PWR8)
-#define PPC64_HAS_VMX
-#endif
-
 #ifndef _LIBUNWIND_REMEMBER_HEAP_ALLOC
 #if defined(_LIBUNWIND_REMEMBER_STACK_ALLOC) || defined(__APPLE__) ||          \
     defined(__linux__) || defined(__ANDROID__) || defined(__MINGW32__) ||      \
     defined(_LIBUNWIND_IS_BAREMETAL)
 #define _LIBUNWIND_REMEMBER_ALLOC(_size) alloca(_size)
 #define _LIBUNWIND_REMEMBER_FREE(_ptr)                                         \
   do {                                                                         \
   } while (0)