[AMDGPU] Enable multi-dword flat scratch load/stores

[arsenm]

The GlobalISel legalization is going to need work to support this.

I think this also misses the wide register spill case handling

[rampitec]

In D91384#2392394, @arsenm wrote:

The GlobalISel legalization is going to need work to support this.

I think this also misses the wide register spill case handling

GlobalISel does not work with flat scratch at all yet, this is TODO.
Spilling is a different beast and going to be a separate patch.

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Out.compute_pgm_resource_registers =
       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
   Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
 
   if (CurrentProgramInfo.DynamicCallStack)
     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
 
   AMD_HSA_BITS_SET(Out.code_properties,
                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
-                   getElementByteSizeValue(STM.getMaxPrivateElementSize()));
+                   getElementByteSizeValue(STM.getMaxPrivateElementSize(true)));
 
   if (MFI->hasPrivateSegmentBuffer()) {
     Out.code_properties |=
       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
   }
 
   if (MFI->hasDispatchPtr())
     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   unsigned getKnownHighZeroBitsForFrameIndex() const {
     return countLeadingZeros(MaxWaveScratchSize) + getWavefrontSizeLog2();
   }
 
   int getLDSBankCount() const {
     return LDSBankCount;
   }
 
-  unsigned getMaxPrivateElementSize() const {
-    return MaxPrivateElementSize;
+  unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
+    return (ForBufferRSrc || !enableFlatScratch()) ? MaxPrivateElementSize : 16;
   }
 
   unsigned getConstantBusLimit(unsigned Opcode) const;
 
   bool hasIntClamp() const {
     return HasIntClamp;
   }
 

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if (AS == AMDGPUAS::GLOBAL_ADDRESS ||
     switch (Subtarget->getMaxPrivateElementSize()) {
     case 4:
       return scalarizeVectorStore(Store, DAG);
     case 8:
       if (NumElements > 2)
         return SplitVectorStore(Op, DAG);
       return SDValue();
     case 16:
-      if (NumElements > 4 || NumElements == 3)
+      if (NumElements > 4 ||
+          (NumElements == 3 && !Subtarget->enableFlatScratch()))
         return SplitVectorStore(Op, DAG);
       return SDValue();
     default:
       llvm_unreachable("unsupported private_element_size");
     }
   } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
     // Use ds_write_b128 or ds_write_b96 when possible.
     if (Subtarget->hasDS96AndDS128() &&

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 
 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
   uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
                     AMDGPU::RSRC_TID_ENABLE |
                     0xffffffff; // Size;
 
   // GFX9 doesn't have ELEMENT_SIZE.
   if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
-    uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize()) - 1;
+    uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize(true)) - 1;
     Rsrc23 |= EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT;
   }
 
   // IndexStride = 64 / 32.
   uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2;
   Rsrc23 |= IndexStride << AMDGPU::RSRC_INDEX_STRIDE_SHIFT;
 
   // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
 
 define amdgpu_kernel void @zero_init_kernel() {
 ; GFX9-LABEL: zero_init_kernel:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
+; GFX9-NEXT:    s_mov_b32 s0, 0
 ; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:76
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:64
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:72
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:68
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:64
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:60
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:56
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:52
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:48
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:44
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:40
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:36
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:32
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:28
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:24
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:20
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:16
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: zero_init_kernel:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_add_u32 s0, s0, s3
 ; GFX10-NEXT:    s_addc_u32 s1, s1, 0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:76
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:72
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:68
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:64
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:60
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:56
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:52
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:48
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:44
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:40
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:36
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:32
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:28
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:24
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:20
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:16
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:64
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:48
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:32
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:16
 ; GFX10-NEXT:    s_endpgm
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
   ret void
 }
 
 define void @zero_init_foo() {
 ; GFX9-LABEL: zero_init_foo:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:60
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:56
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:52
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:48
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:44
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:40
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:36
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:32
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:28
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:24
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:20
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:16
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:12
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:8
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:4
-; GFX9-NEXT:    scratch_store_dword off, v0, s32
+; GFX9-NEXT:    s_mov_b32 s0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:48
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:32
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:16
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: zero_init_foo:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:60
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:56
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:52
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:48
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:44
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:40
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:36
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:32
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:28
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:24
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:20
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:16
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:12
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:8
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:4
-; GFX10-NEXT:    scratch_store_dword off, v0, s32
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:48
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:32
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:16
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
   ret void
 }
 

 
 define amdgpu_kernel void @zero_init_small_offset_kernel() {
 ; GFX9-LABEL: zero_init_small_offset_kernel:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
 ; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
 ; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:4
+; GFX9-NEXT:    s_mov_b32 s0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:284
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:280
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:276
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:272
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:300
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:296
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:292
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:288
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:316
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:312
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:308
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:304
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:332
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:328
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:324
-; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:320
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: zero_init_small_offset_kernel:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_add_u32 s0, s0, s3
 ; GFX10-NEXT:    s_addc_u32 s1, s1, 0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
 ; GFX10-NEXT:    scratch_load_dword v0, off, off offset:4
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:284
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:280
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:276
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:272
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:300
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:296
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:292
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:288
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:316
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:312
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:308
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:304
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:332
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:328
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:324
-; GFX10-NEXT:    scratch_store_dword off, v0, off offset:320
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:272
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:288
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:304
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], off offset:320
 ; GFX10-NEXT:    s_endpgm
   %padding = alloca [64 x i32], align 4, addrspace(5)
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
   ret void
 }
 
 define void @zero_init_small_offset_foo() {
 ; GFX9-LABEL: zero_init_small_offset_foo:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    scratch_load_dword v0, off, s32
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:268
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:264
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:260
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:256
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:284
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:280
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:276
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:272
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:300
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:296
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:292
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:288
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:316
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:312
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:308
-; GFX9-NEXT:    scratch_store_dword off, v0, s32 offset:304
+; GFX9-NEXT:    s_mov_b32 s0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:256
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:272
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:288
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:304
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: zero_init_small_offset_foo:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    scratch_load_dword v0, off, s32
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:268
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:264
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:260
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:256
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:284
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:280
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:276
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:272
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:300
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:296
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:292
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:288
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:316
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:312
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:308
-; GFX10-NEXT:    scratch_store_dword off, v0, s32 offset:304
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:256
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:272
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:288
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], s32 offset:304
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %padding = alloca [64 x i32], align 4, addrspace(5)
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)

 
 define amdgpu_kernel void @zero_init_large_offset_kernel() {
 ; GFX9-LABEL: zero_init_large_offset_kernel:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
 ; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
 ; GFX9-NEXT:    s_mov_b32 vcc_hi, 0
 ; GFX9-NEXT:    scratch_load_dword v0, off, vcc_hi offset:4
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:12
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:8
+; GFX9-NEXT:    s_mov_b32 s0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:28
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:24
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:20
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:16
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:44
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:40
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:36
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi
 ; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:32
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
 ; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:60
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
 ; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:56
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:52
-; GFX9-NEXT:    s_movk_i32 vcc_hi, 0x4010
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:48
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: zero_init_large_offset_kernel:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_add_u32 s0, s0, s3
 ; GFX10-NEXT:    s_addc_u32 s1, s1, 0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
 ; GFX10-NEXT:    scratch_load_dword v0, off, off offset:4
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:12
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:8
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:4
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:28
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo
 ; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:24
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
 ; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:20
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
 ; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:16
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:44
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:40
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:36
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:32
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:60
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:56
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:52
-; GFX10-NEXT:    s_movk_i32 vcc_lo, 0x4010
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:48
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
 ; GFX10-NEXT:    s_endpgm
   %padding = alloca [4096 x i32], align 4, addrspace(5)
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
   ret void
 }
 
 define void @zero_init_large_offset_foo() {
 ; GFX9-LABEL: zero_init_large_offset_foo:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    scratch_load_dword v0, off, s32
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:12
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:8
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:4
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:28
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:24
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:20
+; GFX9-NEXT:    s_mov_b32 s0, 0
+; GFX9-NEXT:    s_mov_b32 s1, s0
+; GFX9-NEXT:    s_mov_b32 s2, s0
+; GFX9-NEXT:    s_mov_b32 s3, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:16
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi
 ; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:44
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
 ; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:40
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
 ; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:36
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:32
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:60
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:56
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:52
-; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
-; GFX9-NEXT:    scratch_store_dword off, v0, vcc_hi offset:48
+; GFX9-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: zero_init_large_offset_foo:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    scratch_load_dword v0, off, s32
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_mov_b32 s0, 0
 ; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
+; GFX10-NEXT:    s_mov_b32 s1, s0
+; GFX10-NEXT:    s_mov_b32 s2, s0
+; GFX10-NEXT:    s_mov_b32 s3, s0
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s1
+; GFX10-NEXT:    v_mov_b32_e32 v2, s2
+; GFX10-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:12
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:8
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:4
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:28
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:24
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:20
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:16
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:44
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:40
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:36
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo
 ; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:32
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
 ; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:60
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
 ; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:56
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:52
-; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
-; GFX10-NEXT:    scratch_store_dword off, v0, vcc_lo offset:48
+; GFX10-NEXT:    scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %padding = alloca [4096 x i32], align 4, addrspace(5)
   %alloca = alloca [32 x i16], align 2, addrspace(5)
   %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
   %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
   %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
bb:
   %add1 = add nsw i32 %sidx, %vidx
   %add2 = add nsw i32 %add1, 256
   %gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2
   store volatile i32 15, i32 addrspace(5)* %gep, align 4
   %load = load volatile i32, i32 addrspace(5)* %gep, align 4
   ret void
 }
 
-; FIXME: Multi-DWORD scratch shall be supported
 define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
 ; GFX9-LABEL: store_load_i64_aligned:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0
-; GFX9-NEXT:    scratch_store_dword v0, v1, off offset:4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 15
-; GFX9-NEXT:    scratch_store_dword v0, v1, off
-; GFX9-NEXT:    scratch_load_dword v1, v0, off offset:4
-; GFX9-NEXT:    scratch_load_dword v0, v0, off
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX9-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: store_load_i64_aligned:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-NEXT:    v_mov_b32_e32 v2, 15
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_dword v0, v1, off offset:4
-; GFX10-NEXT:    scratch_store_dword v0, v2, off
-; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    scratch_load_dword v1, v0, off offset:4
-; GFX10-NEXT:    scratch_load_dword v0, v0, off
+; GFX10-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX10-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 bb:
   store volatile i64 15, i64 addrspace(5)* %arg, align 8
   %load = load volatile i64, i64 addrspace(5)* %arg, align 8
   ret void
 }
 
-; FIXME: Multi-DWORD unaligned scratch shall be supported
 define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
 ; GFX9-LABEL: store_load_i64_unaligned:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:7
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:6
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:5
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:4
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:3
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:2
-; GFX9-NEXT:    scratch_store_byte v0, v1, off offset:1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 15
-; GFX9-NEXT:    scratch_store_byte v0, v1, off
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:6
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:7
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:4
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:5
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:2
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off offset:3
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    scratch_load_ubyte v1, v0, off
-; GFX9-NEXT:    scratch_load_ubyte v0, v0, off offset:1
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX9-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: store_load_i64_unaligned:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-NEXT:    v_mov_b32_e32 v2, 15
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    ; implicit-def: $vcc_hi
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:7
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:6
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:5
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:4
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:3
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:2
-; GFX10-NEXT:    scratch_store_byte v0, v1, off offset:1
-; GFX10-NEXT:    scratch_store_byte v0, v2, off
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:6
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:7
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:4
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:5
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:2
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off offset:3
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    scratch_load_ubyte v1, v0, off
-; GFX10-NEXT:    scratch_load_ubyte v0, v0, off offset:1
+; GFX10-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX10-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 bb:
   store volatile i64 15, i64 addrspace(5)* %arg, align 1
   %load = load volatile i64, i64 addrspace(5)* %arg, align 1
   ret void
 }
 
+define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_v3i32_unaligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, 1
+; GFX9-NEXT:    v_mov_b32_e32 v2, 2
+; GFX9-NEXT:    v_mov_b32_e32 v3, 3
+; GFX9-NEXT:    scratch_store_dwordx3 v0, v[1:3], off
+; GFX9-NEXT:    scratch_load_dwordx3 v[0:2], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_v3i32_unaligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 1
+; GFX10-NEXT:    v_mov_b32_e32 v2, 2
+; GFX10-NEXT:    v_mov_b32_e32 v3, 3
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    scratch_store_dwordx3 v0, v[1:3], off
+; GFX10-NEXT:    scratch_load_dwordx3 v[0:2], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1
+  %load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1
+  ret void
+}
+
+define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_v4i32_unaligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, 1
+; GFX9-NEXT:    v_mov_b32_e32 v2, 2
+; GFX9-NEXT:    v_mov_b32_e32 v3, 3
+; GFX9-NEXT:    v_mov_b32_e32 v4, 4
+; GFX9-NEXT:    scratch_store_dwordx4 v0, v[1:4], off
+; GFX9-NEXT:    scratch_load_dwordx4 v[0:3], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_v4i32_unaligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 1
+; GFX10-NEXT:    v_mov_b32_e32 v2, 2
+; GFX10-NEXT:    v_mov_b32_e32 v3, 3
+; GFX10-NEXT:    v_mov_b32_e32 v4, 4
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    scratch_store_dwordx4 v0, v[1:4], off
+; GFX10-NEXT:    scratch_load_dwordx4 v[0:3], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1
+  %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1
+  ret void
+}
+
 declare void @llvm.memset.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8, i64, i1 immarg)
 declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

 ; FLATSCR-NEXT:  BB0_1: ; %loadstoreloop
 ; FLATSCR-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; FLATSCR-NEXT:    s_add_u32 s3, 0x3000, s2
 ; FLATSCR-NEXT:    s_add_i32 s2, s2, 1
 ; FLATSCR-NEXT:    s_cmpk_lt_u32 s2, 0x2120
 ; FLATSCR-NEXT:    scratch_store_byte off, v0, s3
 ; FLATSCR-NEXT:    s_cbranch_scc1 BB0_1
 ; FLATSCR-NEXT:  ; %bb.2: ; %split
-; FLATSCR-NEXT:    s_movk_i32 s2, 0x20d0
-; FLATSCR-NEXT:    s_add_u32 s2, 0x3000, s2
-; FLATSCR-NEXT:    scratch_load_dword v1, off, s2 offset:4
 ; FLATSCR-NEXT:    s_movk_i32 s2, 0x2000
 ; FLATSCR-NEXT:    s_add_u32 s2, 0x3000, s2
-; FLATSCR-NEXT:    scratch_load_dword v0, off, s2 offset:208
-; FLATSCR-NEXT:    s_movk_i32 s2, 0x3000
-; FLATSCR-NEXT:    scratch_load_dword v2, off, s2 offset:68
+; FLATSCR-NEXT:    scratch_load_dwordx2 v[0:1], off, s2 offset:208
 ; FLATSCR-NEXT:    s_movk_i32 s2, 0x3000
-; FLATSCR-NEXT:    scratch_load_dword v3, off, s2 offset:64
+; FLATSCR-NEXT:    scratch_load_dwordx2 v[2:3], off, s2 offset:64
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
-; FLATSCR-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; FLATSCR-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
+; FLATSCR-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; FLATSCR-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
 ; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLATSCR-NEXT:    v_mov_b32_e32 v3, s1
 ; FLATSCR-NEXT:    v_mov_b32_e32 v2, s0
 ; FLATSCR-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
 ; FLATSCR-NEXT:    s_endpgm
 entry:
   %pin.low = alloca i32, align 8192, addrspace(5)
   %local.area = alloca [1060 x i64], align 4096, addrspace(5)

 ; FLATSCR-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; FLATSCR-NEXT:    s_add_u32 vcc_hi, s33, 0x1000
 ; FLATSCR-NEXT:    s_add_u32 s1, vcc_hi, s0
 ; FLATSCR-NEXT:    s_add_i32 s0, s0, 1
 ; FLATSCR-NEXT:    s_cmpk_lt_u32 s0, 0x2120
 ; FLATSCR-NEXT:    scratch_store_byte off, v2, s1
 ; FLATSCR-NEXT:    s_cbranch_scc1 BB1_1
 ; FLATSCR-NEXT:  ; %bb.2: ; %split
-; FLATSCR-NEXT:    s_movk_i32 s0, 0x20d0
-; FLATSCR-NEXT:    s_add_u32 s1, s33, 0x1000
-; FLATSCR-NEXT:    s_add_u32 s0, s1, s0
-; FLATSCR-NEXT:    scratch_load_dword v3, off, s0 offset:4
 ; FLATSCR-NEXT:    s_movk_i32 s0, 0x2000
 ; FLATSCR-NEXT:    s_add_u32 s1, s33, 0x1000
 ; FLATSCR-NEXT:    s_add_u32 s0, s1, s0
-; FLATSCR-NEXT:    scratch_load_dword v2, off, s0 offset:208
-; FLATSCR-NEXT:    s_add_u32 s0, s33, 0x1000
-; FLATSCR-NEXT:    scratch_load_dword v4, off, s0 offset:68
+; FLATSCR-NEXT:    scratch_load_dwordx2 v[2:3], off, s0 offset:208
 ; FLATSCR-NEXT:    s_add_u32 s0, s33, 0x1000
-; FLATSCR-NEXT:    scratch_load_dword v5, off, s0 offset:64
+; FLATSCR-NEXT:    scratch_load_dwordx2 v[4:5], off, s0 offset:64
 ; FLATSCR-NEXT:    s_sub_u32 s32, s32, 0x6000
 ; FLATSCR-NEXT:    s_mov_b32 s33, s2
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
-; FLATSCR-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
-; FLATSCR-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
+; FLATSCR-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; FLATSCR-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
 ; FLATSCR-NEXT:    global_store_dwordx2 v[0:1], v[2:3], off
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %pin.low = alloca i32, align 8192, addrspace(5)
   %local.area = alloca [1060 x i64], align 4096, addrspace(5)
   store volatile i32 0, i32 addrspace(5)* %pin.low
   %local.area.cast = bitcast [1060 x i64] addrspace(5)* %local.area to i8 addrspace(5)*

llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll

 ; MUBUF-NEXT:    buffer_store_dword v8, off, s[0:3], s32 offset:4
 ; MUBUF-NEXT:    buffer_store_dword v7, off, s[0:3], s32
 ; MUBUF-NEXT:    s_waitcnt vmcnt(0)
 ; MUBUF-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; FLATSCR-LABEL: memcpy_fixed_align:
 ; FLATSCR:       ; %bb.0:
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; FLATSCR-NEXT:    global_load_dword v0, v[1:2], off offset:36
-; FLATSCR-NEXT:    global_load_dword v11, v[1:2], off offset:32
+; FLATSCR-NEXT:    global_load_dwordx2 v[11:12], v[1:2], off offset:32
 ; FLATSCR-NEXT:    global_load_dwordx4 v[3:6], v[1:2], off offset:16
 ; FLATSCR-NEXT:    global_load_dwordx4 v[7:10], v[1:2], off
-; FLATSCR-NEXT:    s_waitcnt vmcnt(3)
-; FLATSCR-NEXT:    scratch_store_dword off, v0, s32 offset:36
-; FLATSCR-NEXT:    s_waitcnt vmcnt(3)
-; FLATSCR-NEXT:    scratch_store_dword off, v11, s32 offset:32
-; FLATSCR-NEXT:    s_waitcnt vmcnt(3)
-; FLATSCR-NEXT:    scratch_store_dword off, v6, s32 offset:28
-; FLATSCR-NEXT:    scratch_store_dword off, v5, s32 offset:24
-; FLATSCR-NEXT:    scratch_store_dword off, v4, s32 offset:20
-; FLATSCR-NEXT:    scratch_store_dword off, v3, s32 offset:16
-; FLATSCR-NEXT:    s_waitcnt vmcnt(6)
-; FLATSCR-NEXT:    scratch_store_dword off, v10, s32 offset:12
-; FLATSCR-NEXT:    scratch_store_dword off, v9, s32 offset:8
-; FLATSCR-NEXT:    scratch_store_dword off, v8, s32 offset:4
-; FLATSCR-NEXT:    scratch_store_dword off, v7, s32
+; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
+; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[11:12], s32 offset:32
+; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
+; FLATSCR-NEXT:    scratch_store_dwordx4 off, v[3:6], s32 offset:16
+; FLATSCR-NEXT:    s_waitcnt vmcnt(2)
+; FLATSCR-NEXT:    scratch_store_dwordx4 off, v[7:10], s32
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    s_setpc_b64 s[30:31]
   %alloca = alloca [40 x i8], addrspace(5)
   %cast = bitcast [40 x i8] addrspace(5)* %alloca to i8 addrspace(5)*
   call void @llvm.memcpy.p5i8.p1i8.i64(i8 addrspace(5)* align 4 dereferenceable(40) %cast, i8 addrspace(1)* align 4 dereferenceable(40) %src, i64 40, i1 false)
   ret void
 }
 
 declare void @llvm.memcpy.p5i8.p1i8.i64(i8 addrspace(5)* noalias nocapture writeonly, i8 addrspace(1)* noalias nocapture readonly, i64, i1 immarg) #0
 
 attributes #0 = { argmemonly nounwind willreturn }

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

 ; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
 ; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
 ; FLATSCR-NEXT:    s_cmp_lg_u32 s5, 0
 ; FLATSCR-NEXT:    s_cbranch_scc1 BB0_3
 ; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
 ; FLATSCR-NEXT:    s_mov_b32 s2, s32
 ; FLATSCR-NEXT:    s_movk_i32 s3, 0x1000
 ; FLATSCR-NEXT:    s_add_i32 s4, s2, s3
-; FLATSCR-NEXT:    s_add_u32 s2, s2, s3
 ; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
-; FLATSCR-NEXT:    scratch_store_dword off, v1, s2
-; FLATSCR-NEXT:    v_mov_b32_e32 v1, 1
+; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
+; FLATSCR-NEXT:    s_add_u32 s2, s2, s3
+; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
 ; FLATSCR-NEXT:    s_lshl_b32 s2, s6, 2
 ; FLATSCR-NEXT:    s_mov_b32 s32, s4
-; FLATSCR-NEXT:    scratch_store_dword off, v1, s4 offset:4
 ; FLATSCR-NEXT:    s_add_i32 s4, s4, s2
 ; FLATSCR-NEXT:    scratch_load_dword v1, off, s4
 ; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    v_add_u32_e32 v2, v1, v0
 ; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLATSCR-NEXT:    v_mov_b32_e32 v0, s0
 ; FLATSCR-NEXT:    v_mov_b32_e32 v1, s1

 ; FLATSCR-NEXT:    s_mov_b32 s33, 0
 ; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLATSCR-NEXT:    s_cmp_lg_u32 s2, 0
 ; FLATSCR-NEXT:    s_cbranch_scc1 BB1_2
 ; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
 ; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
 ; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
 ; FLATSCR-NEXT:    v_mov_b32_e32 v1, 0
-; FLATSCR-NEXT:    scratch_store_dword off, v1, s2
-; FLATSCR-NEXT:    v_mov_b32_e32 v1, 1
+; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
 ; FLATSCR-NEXT:    s_lshl_b32 s3, s3, 2
 ; FLATSCR-NEXT:    s_mov_b32 s32, s2
-; FLATSCR-NEXT:    scratch_store_dword off, v1, s2 offset:4
+; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[1:2], s2
 ; FLATSCR-NEXT:    s_add_i32 s2, s2, s3
 ; FLATSCR-NEXT:    scratch_load_dword v1, off, s2
 ; FLATSCR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    v_add_u32_e32 v2, v1, v0
 ; FLATSCR-NEXT:    s_waitcnt lgkmcnt(0)
 ; FLATSCR-NEXT:    v_mov_b32_e32 v0, s0
 ; FLATSCR-NEXT:    v_mov_b32_e32 v1, s1

 ; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
 ; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
 ; FLATSCR-NEXT:    s_and_b64 exec, exec, vcc
 ; FLATSCR-NEXT:    s_cbranch_execz BB2_3
 ; FLATSCR-NEXT:  ; %bb.2: ; %bb.1
 ; FLATSCR-NEXT:    s_mov_b32 s2, s32
 ; FLATSCR-NEXT:    s_movk_i32 s3, 0x1000
 ; FLATSCR-NEXT:    s_add_i32 s4, s2, s3
-; FLATSCR-NEXT:    s_add_u32 s2, s2, s3
 ; FLATSCR-NEXT:    v_mov_b32_e32 v2, 0
-; FLATSCR-NEXT:    scratch_store_dword off, v2, s2
-; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
-; FLATSCR-NEXT:    scratch_store_dword off, v2, s4 offset:4
+; FLATSCR-NEXT:    v_mov_b32_e32 v3, 1
+; FLATSCR-NEXT:    s_add_u32 s2, s2, s3
+; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[2:3], s2
 ; FLATSCR-NEXT:    v_lshl_add_u32 v2, v4, 2, s4
 ; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
 ; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v5
 ; FLATSCR-NEXT:    s_mov_b32 s32, s4
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
 ; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
 ; FLATSCR-NEXT:  BB2_3: ; %bb.2

 ; FLATSCR-NEXT:    s_and_b32 s33, s0, 0xffffffc0
 ; FLATSCR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
 ; FLATSCR-NEXT:    s_add_u32 s32, s32, 0x80
 ; FLATSCR-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; FLATSCR-NEXT:    s_cbranch_execz BB3_2
 ; FLATSCR-NEXT:  ; %bb.1: ; %bb.0
 ; FLATSCR-NEXT:    s_add_i32 s2, s32, 0x1000
 ; FLATSCR-NEXT:    s_and_b32 s2, s2, 0xfffff000
-; FLATSCR-NEXT:    v_mov_b32_e32 v2, 0
-; FLATSCR-NEXT:    scratch_store_dword off, v2, s2
-; FLATSCR-NEXT:    v_mov_b32_e32 v2, 1
-; FLATSCR-NEXT:    scratch_store_dword off, v2, s2 offset:4
+; FLATSCR-NEXT:    v_mov_b32_e32 v5, 0
+; FLATSCR-NEXT:    v_mov_b32_e32 v6, 1
 ; FLATSCR-NEXT:    v_lshl_add_u32 v2, v3, 2, s2
+; FLATSCR-NEXT:    scratch_store_dwordx2 off, v[5:6], s2
 ; FLATSCR-NEXT:    scratch_load_dword v2, v2, off
 ; FLATSCR-NEXT:    v_and_b32_e32 v3, 0x3ff, v4
 ; FLATSCR-NEXT:    s_mov_b32 s32, s2
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    v_add_u32_e32 v2, v2, v3
 ; FLATSCR-NEXT:    global_store_dword v[0:1], v2, off
 ; FLATSCR-NEXT:  BB3_2: ; %bb.1
 ; FLATSCR-NEXT:    s_or_b64 exec, exec, s[0:1]

llvm/test/CodeGen/AMDGPU/scratch-simple.ll

 ; RELS: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD1 0x0
 
 ; This used to fail due to a v_add_i32 instruction with an illegal immediate
 ; operand that was created during Local Stack Slot Allocation. Test case derived
 ; from https://bugs.freedesktop.org/show_bug.cgi?id=96602
 ;
 ; GCN-LABEL: {{^}}ps_main:
 
-; GFX9-FLATSCR: s_add_u32 flat_scratch_lo, s0, s2
-; GFX9-FLATSCR: s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-FLATSCR-DAG: s_add_u32 flat_scratch_lo, s0, s2
+; GFX9-FLATSCR-DAG: s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-FLATSCR-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
 
 ; GFX10-FLATSCR: s_add_u32 s0, s0, s2
 ; GFX10-FLATSCR: s_addc_u32 s1, s1, 0
 ; GFX10-FLATSCR: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
 ; GFX10-FLATSCR: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
 
 ; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
 ; MUBUF-DAG: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
 ; MUBUF-DAG: s_mov_b32 s2, -1
 ; SI-DAG: s_mov_b32 s3, 0xe8f000
 ; VI-DAG: s_mov_b32 s3, 0xe80000
 ; GFX9-MUBUF-DAG: s_mov_b32 s3, 0xe00000
 ; GFX10_W32-MUBUF-DAG: s_mov_b32 s3, 0x31c16000
 ; GFX10_W64-MUBUF-DAG: s_mov_b32 s3, 0x31e16000
 
 ; FLATSCR-NOT: SCRATCH_RSRC_DWORD
 
 ; GFX9-FLATSCR: s_mov_b32 [[SP:[^,]+]], 0
-; GFX9-FLATSCR: scratch_store_dword off, v2, [[SP]] offset:
-; GFX9-FLATSCR: s_mov_b32 [[SP:[^,]+]], 0
-; GFX9-FLATSCR: scratch_store_dword off, v2, [[SP]] offset:
+; GFX9-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SP]] offset:
 
-; GFX10-FLATSCR: scratch_store_dword off, v2, off offset:
-; GFX10-FLATSCR: scratch_store_dword off, v2, off offset:
+; GFX10-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], off offset:
 
-; GCN-DAG: v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0
-; GCN-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, [[BYTES]]
+; MUBUF-DAG:     v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0
+; MUBUF-DAG:     v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, [[BYTES]]
+; GFX10-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
 ; GCN-NOT: s_mov_b32 s0
 
 ; GCN-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[HI_OFF:v[0-9]+]],{{.*}} 0x280, [[CLAMP_IDX]]
 ; GCN-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]]
 
 ; MUBUF: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 ; MUBUF: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 ; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[LO_OFF]], off
-; FLATSCR: scratch_load_dword {{v[0-9]+}}, [[HI_OFF]], off
 define amdgpu_ps float @ps_main(i32 %idx) {
   %v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
   %v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
   %r = fadd float %v1, %v2
   ret float %r
 }
 
 ; GCN-LABEL: {{^}}vs_main:

 ; GCN-NOT: s_mov_b32 s0
 
 ; FLATSCR-NOT: SCRATCH_RSRC_DWORD
 
 ; MUBUF: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 ; MUBUF: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen
 
 ; GFX9-FLATSCR: s_mov_b32 [[SP:[^,]+]], 0
-; GFX9-FLATSCR: scratch_store_dword off, v2, [[SP]] offset:
-; GFX9-FLATSCR: s_mov_b32 [[SP:[^,]+]], 0
-; GFX9-FLATSCR: scratch_store_dword off, v2, [[SP]] offset:
+; GFX9-FLATSCR: scratch_store_dwordx4 off, v[{{[0-9:]+}}], [[SP]] offset:
 
 ; FLATSCR: scratch_load_dword {{v[0-9]+}}, {{v[0-9]+}}, off
 ; FLATSCR: scratch_load_dword {{v[0-9]+}}, {{v[0-9]+}}, off
 
 define amdgpu_vs float @vs_main(i32 %idx) {
   %v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
   %v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
   %r = fadd float %v1, %v2

llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll

 ; FLATSCR-NEXT:    v_mov_b32_e32 v0, s2
 ; FLATSCR-NEXT:    s_swappc_b64 s[30:31], s[0:1]
 ; FLATSCR-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
 ; FLATSCR-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; FLATSCR-NEXT:    s_cbranch_execz BB0_2
 ; FLATSCR-NEXT:  ; %bb.1: ; %if.then4.i
 ; FLATSCR-NEXT:    s_movk_i32 vcc_lo, 0x4000
 ; FLATSCR-NEXT:    s_nop 1
-; FLATSCR-NEXT:    scratch_load_dword v0, off, vcc_lo offset:4
-; FLATSCR-NEXT:    s_waitcnt_depctr 0xffe3
-; FLATSCR-NEXT:    s_movk_i32 vcc_lo, 0x4000
-; FLATSCR-NEXT:    scratch_load_dword v1, off, vcc_lo offset:8
+; FLATSCR-NEXT:    scratch_load_dwordx2 v[0:1], off, vcc_lo offset:4
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    v_add_nc_u32_e32 v0, v1, v0
 ; FLATSCR-NEXT:    v_mul_lo_u32 v0, 0x41c64e6d, v0
 ; FLATSCR-NEXT:    v_add_nc_u32_e32 v0, 0x3039, v0
 ; FLATSCR-NEXT:    scratch_store_dword off, v0, s0
 ; FLATSCR-NEXT:  BB0_2: ; %shader_eval_surface.exit
 ; FLATSCR-NEXT:    s_endpgm
 entry: