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Differential D90206

[PowerPC] Skip IEEE 128-bit FP type in FastISel
ClosedPublic

Authored by qiucf on Oct 26 2020, 7:11 PM.

Details

Reviewers
nemanjai
jsji
steven.zhang
lei
Group Reviewers
Restricted Project
Commits
rGd14e51806b02: [PowerPC] Skip IEEE 128-bit FP type in FastISel
Summary

Vector types, quadword integers and f128 currently cannot be handled in FastISel. We did not skip f128 type in lowering arguments, which causes a crash.

Diff Detail

Unit TestsFailed

TimeTest
390 mslinux > HWAddressSanitizer-x86_64.TestCases::sizes.cpp

Event Timeline

qiucf created this revision.Oct 26 2020, 7:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2020, 7:11 PM
Herald added subscribers: llvm-commits, shchenz, kbarton and 2 others. · View Herald Transcript
qiucf requested review of this revision.Oct 26 2020, 7:11 PM
qiucf edited the summary of this revision. (Show Details)Oct 26 2020, 7:14 PM
qiucf added reviewers: nemanjai, jsji, steven.zhang, Restricted Project, lei.
Harbormaster completed remote builds in B76497: Diff 300857.Oct 26 2020, 7:54 PM
qiucf updated this revision to Diff 300917.Oct 27 2020, 2:07 AM
qiucf retitled this revision from [PowerPC] Fix IEEE 128-bit calling convention to [PowerPC] Skip IEEE 128-bit FP type in FastISel.
qiucf edited the summary of this revision. (Show Details)

Skip f128 in FastISel.

Harbormaster completed remote builds in B76517: Diff 300917.Oct 27 2020, 2:36 AM
qiucf updated this revision to Diff 300926.Oct 27 2020, 2:58 AM

Add comments

Harbormaster completed remote builds in B76520: Diff 300926.Oct 27 2020, 3:29 AM
steven.zhang added inline comments.Nov 1 2020, 6:40 PM
llvm/lib/Target/PowerPC/PPCFastISel.cpp
1629

So, this is a TODO ?

qiucf updated this revision to Diff 302203.Nov 1 2020, 10:20 PM

Mark as 'FIXME'

steven.zhang accepted this revision.Nov 2 2020, 5:04 PM

LGTM.

This revision is now accepted and ready to land.Nov 2 2020, 5:04 PM
Closed by commit rGd14e51806b02: [PowerPC] Skip IEEE 128-bit FP type in FastISel (authored by qiucf). · Explain WhyNov 2 2020, 7:18 PM
This revision was automatically updated to reflect the committed changes.
qiucf added a commit: rGd14e51806b02: [PowerPC] Skip IEEE 128-bit FP type in FastISel.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
2 lines
test/
CodeGen/
PowerPC/
29 lines

Diff 300917

llvm/lib/Target/PowerPC/PPCFastISel.cpp

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
return false; return false;
Value *ArgValue = CLI.OutVals[i]; Value *ArgValue = CLI.OutVals[i];
Type *ArgTy = ArgValue->getType(); Type *ArgTy = ArgValue->getType();
MVT ArgVT; MVT ArgVT;
if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8) if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
return false; return false;
if (ArgVT.isVector()) if (ArgVT.isVector() || ArgVT == MVT::f128)
steven.zhangUnsubmitted
Not Done
ReplyInline Actions

So, this is a TODO ?

steven.zhang: So, this is a TODO ?
return false; return false;
unsigned Arg = getRegForValue(ArgValue); unsigned Arg = getRegForValue(ArgValue);
if (Arg == 0) if (Arg == 0)
return false; return false;
Args.push_back(ArgValue); Args.push_back(ArgValue);
ArgRegs.push_back(Arg); ArgRegs.push_back(Arg);
▲ Show 20 Lines • Show All 844 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Linesentry:
store <4 x i32> %vec1, <4 x i32>* %vec2, align 16 store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
%0 = load fp128, fp128* %f2, align 16 %0 = load fp128, fp128* %f2, align 16
%conv = sitofp i32 %i1 to fp128 %conv = sitofp i32 %i1 to fp128
%add = fadd fp128 %0, %conv %add = fadd fp128 %0, %conv
%conv1 = fptrunc fp128 %add to double %conv1 = fptrunc fp128 %add to double
store double %conv1, double* %d1, align 8 store double %conv1, double* %d1, align 8
ret void ret void
} }
; Function Attrs: noinline optnone
define signext i32 @noopt_call_crash() #0 {
; CHECK-LABEL: noopt_call_crash:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -96(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl in
; CHECK-NEXT: nop
; CHECK-NEXT: bl out
; CHECK-NEXT: nop
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: addi r1, r1, 96
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
%call = call fp128 @in()
call void @out(fp128 %call)
ret i32 0
}
declare void @out(fp128)
declare fp128 @in()
attributes #0 = { noinline optnone }