[COFF][ARM] Fix CodeView for Windows on 32bit ARM targets.

[luqmana]

Summary

Create the LLVM / CodeView register mappings for the 32-bit ARM Window targets.

[compnerd]

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

129

I think that Triple.isOSWindows() would be nicer than the explicit check to Win32.

llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp

161

It might be nice to change this to explicitly:

case COFF::IMAGE_FILE_MACHINE_AMD64:

and add the x86 case and llvm::fatal_error in any other case.

[rnk]

Thanks, this is a frequently reported issue.

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

129

Is this conditional necessary? Can we always use ARMNT? Under what circumstances would one with to emit codeview for a non-windows OS triple?

llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp

161

For a dumper, I would prefer that the tool not report a fatal error for an unknown machine type. I think it would be best to send the code to the enumFallback<Hex16> case below, so the registers come out as numbers.

[compnerd]

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

129

The particular case that I think that this is trying to account for is WinCE vs WinNT. However, WinCE isn't currently supported by LLVM, so .... a TODO comment + ARMNT sounds like a good idea to me.

llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp

161

Um, lets pretend I never said anything ... your approach is _significantly_ better. Im blaming (lack of) coffee.

[luqmana]

Address review comments.

[luqmana]

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

129

Coment + ARMNT works for me. I just added the conditional there to not break anything existing but if there's no CE support anyways it should be fine.

[TomTan]

llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp

156

nit: probably assign CPUType in the in switch case, then all calls to getRegisterNames can be consolidated?

[luqmana]

Nit: consolidate getRegisterNames calls.

[compnerd]

Thanks for doing this!

[luqmana]

In D89622#2340812, @compnerd wrote:

Thanks for doing this!

Np, thanks for the review!

llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef CV_REGISTER
 #define CV_REGISTER(name, value)
 #endif
 
 #if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) &&                \
+    !defined(CV_REGISTERS_ARM) &&                                              \
     !defined(CV_REGISTERS_ARM64)
 #error Need include at least one register set.
 #endif
 
 // This currently only contains the "register subset shared by all processor
 // types" (ERR etc.) and the x86/arm64 registers.
 
 #if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86)

 CV_REGISTER(ARM_R11, 21)
 CV_REGISTER(ARM_R12, 22)
 CV_REGISTER(ARM_SP, 23)
 CV_REGISTER(ARM_LR, 24)
 CV_REGISTER(ARM_PC, 25)
 
 // Status register
 
-CV_REGISTER(ARM_CPSR, 25)
+CV_REGISTER(ARM_CPSR, 26)
 
 // ARM VFPv1 registers
 
 CV_REGISTER(ARM_FPSCR, 40)
 CV_REGISTER(ARM_FPEXC, 41)
 
+CV_REGISTER(ARM_FS0, 50)
+CV_REGISTER(ARM_FS1, 51)
+CV_REGISTER(ARM_FS2, 52)
+CV_REGISTER(ARM_FS3, 53)
+CV_REGISTER(ARM_FS4, 54)
+CV_REGISTER(ARM_FS5, 55)
+CV_REGISTER(ARM_FS6, 56)
+CV_REGISTER(ARM_FS7, 57)
+CV_REGISTER(ARM_FS8, 58)
+CV_REGISTER(ARM_FS9, 59)
+CV_REGISTER(ARM_FS10, 60)
+CV_REGISTER(ARM_FS11, 61)
+CV_REGISTER(ARM_FS12, 62)
+CV_REGISTER(ARM_FS13, 63)
+CV_REGISTER(ARM_FS14, 64)
+CV_REGISTER(ARM_FS15, 65)
+CV_REGISTER(ARM_FS16, 66)
+CV_REGISTER(ARM_FS17, 67)
+CV_REGISTER(ARM_FS18, 68)
+CV_REGISTER(ARM_FS19, 69)
+CV_REGISTER(ARM_FS20, 70)
+CV_REGISTER(ARM_FS21, 71)
+CV_REGISTER(ARM_FS22, 72)
+CV_REGISTER(ARM_FS23, 73)
+CV_REGISTER(ARM_FS24, 74)
+CV_REGISTER(ARM_FS25, 75)
+CV_REGISTER(ARM_FS26, 76)
+CV_REGISTER(ARM_FS27, 77)
+CV_REGISTER(ARM_FS28, 78)
+CV_REGISTER(ARM_FS29, 79)
+CV_REGISTER(ARM_FS30, 80)
+CV_REGISTER(ARM_FS31, 81)
+
 // ARM VFPv3/NEON registers
 
 CV_REGISTER(ARM_FS32, 200)
 CV_REGISTER(ARM_FS33, 201)
 CV_REGISTER(ARM_FS34, 202)
 CV_REGISTER(ARM_FS35, 203)
 CV_REGISTER(ARM_FS36, 204)
 CV_REGISTER(ARM_FS37, 205)

llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

public:
   }
 
 private:
   MCStreamer *OS = nullptr;
   TypeCollection &TypeTable;
 };
 } // namespace
 
-static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
-  switch (Type) {
+static CPUType mapArchToCVCPUType(const Triple &Triple) {
+  switch (Triple.getArch()) {
   case Triple::ArchType::x86:
     return CPUType::Pentium3;
   case Triple::ArchType::x86_64:
     return CPUType::X64;
   case Triple::ArchType::thumb:
-    return CPUType::Thumb;
+    return Triple.getOS() == Triple::Win32 ? CPUType::ARMNT : CPUType::Thumb;
   case Triple::ArchType::aarch64:
     return CPUType::ARM64;
   default:
     report_fatal_error("target architecture doesn't map to a CodeView CPUType");
   }
 }
 
 CodeViewDebug::CodeViewDebug(AsmPrinter *AP)
     : DebugHandlerBase(AP), OS(*Asm->OutStreamer), TypeTable(Allocator) {
   // If module doesn't have named metadata anchors or COFF debug section
   // is not available, skip any debug info related stuff.
   if (!MMI->getModule()->getNamedMetadata("llvm.dbg.cu") ||
       !AP->getObjFileLowering().getCOFFDebugSymbolsSection()) {
     Asm = nullptr;
     MMI->setDebugInfoAvailability(false);
     return;
   }
   // Tell MMI that we have debug info.
   MMI->setDebugInfoAvailability(true);
 
-  TheCPU =
-      mapArchToCVCPUType(Triple(MMI->getModule()->getTargetTriple()).getArch());
+  TheCPU = mapArchToCVCPUType(Triple(MMI->getModule()->getTargetTriple()));
 
   collectGlobalVariableInfo();
 
   // Check if we should emit type record hashes.
   ConstantInt *GH = mdconst::extract_or_null<ConstantInt>(
       MMI->getModule()->getModuleFlag("CodeViewGHash"));
   EmitDebugGlobalHashes = GH && !GH->isZero();
 }

llvm/lib/DebugInfo/CodeView/EnumTables.cpp

 static const EnumEntry<uint16_t> RegisterNames_X86[] = {
 #define CV_REGISTERS_X86
 #define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER
 #undef CV_REGISTERS_X86
 };
 
+static const EnumEntry<uint16_t> RegisterNames_ARM[] = {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+};
+
 static const EnumEntry<uint16_t> RegisterNames_ARM64[] = {
 #define CV_REGISTERS_ARM64
 #define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name),
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER
 #undef CV_REGISTERS_ARM64
 };
 
ArrayRef<EnumEntry<SymbolKind>> getSymbolTypeNames() {
   return makeArrayRef(SymbolTypeNames);
 }
 
 ArrayRef<EnumEntry<TypeLeafKind>> getTypeLeafNames() {
   return makeArrayRef(TypeLeafNames);
 }
 
 ArrayRef<EnumEntry<uint16_t>> getRegisterNames(CPUType Cpu) {
-  if (Cpu == CPUType::ARM64) {
+  if (Cpu == CPUType::ARMNT) {
+    return makeArrayRef(RegisterNames_ARM);
+  } else if (Cpu == CPUType::ARM64) {
     return makeArrayRef(RegisterNames_ARM64);
   }
   return makeArrayRef(RegisterNames_X86);
 }
 
 ArrayRef<EnumEntry<uint32_t>> getPublicSymFlagNames() {
   return makeArrayRef(PublicSymFlagNames);
 }

llvm/lib/DebugInfo/PDB/PDBExtras.cpp

switch (Data) {
     CASE_OUTPUT_ENUM_CLASS_STR(PDB_DataKind, StaticMember, "static member", OS)
     CASE_OUTPUT_ENUM_CLASS_STR(PDB_DataKind, Constant, "const", OS)
   }
   return OS;
 }
 
 raw_ostream &llvm::pdb::operator<<(raw_ostream &OS,
                                    const llvm::codeview::CPURegister &CpuReg) {
-  if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
+  if (CpuReg.Cpu == llvm::codeview::CPUType::ARMNT) {
+    switch (CpuReg.Reg) {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val)                                                 \
+  case codeview::RegisterId::name:                                             \
+    OS << #name;                                                               \
+    return OS;
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+
+    default:
+      break;
+    }
+  } else if (CpuReg.Cpu == llvm::codeview::CPUType::ARM64) {
     switch (CpuReg.Reg) {
 #define CV_REGISTERS_ARM64
 #define CV_REGISTER(name, val)                                                 \
   case codeview::RegisterId::name:                                             \
     OS << #name;                                                               \
     return OS;
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER

llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp

 void ScalarEnumerationTraits<CPUType>::enumeration(IO &io, CPUType &Cpu) {
   auto CpuNames = getCPUTypeNames();
   for (const auto &E : CpuNames) {
     io.enumCase(Cpu, E.Name.str().c_str(), static_cast<CPUType>(E.Value));
   }
 }
 
 void ScalarEnumerationTraits<RegisterId>::enumeration(IO &io, RegisterId &Reg) {
-  auto RegNames = getRegisterNames(CPUType::X64);
+  const auto *Header = static_cast<COFF::header *>(io.getContext());
+  assert(Header && "The IO context is not initialized");
+
+  CPUType CpuType;
+  switch (Header->Machine) {
+  case COFF::IMAGE_FILE_MACHINE_ARMNT:
+    CpuType = CPUType::ARMNT;
+    break;
+  case COFF::IMAGE_FILE_MACHINE_ARM64:
+    CpuType = CPUType::ARM64;
+    break;
+  default:
+    CpuType = CPUType::X64;
+    break;
+  }
+  auto RegNames = getRegisterNames(CpuType);
   for (const auto &E : RegNames) {
     io.enumCase(Reg, E.Name.str().c_str(), static_cast<RegisterId>(E.Value));
   }
   io.enumFallback<Hex16>(Reg);
 }
 
 void ScalarEnumerationTraits<TrampolineType>::enumeration(
     IO &io, TrampolineType &Tramp) {

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

 #define DEBUG_TYPE "arm-register-info"
 
 #define GET_REGINFO_TARGET_DESC
 #include "ARMGenRegisterInfo.inc"
 
 using namespace llvm;
 
 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
-    : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
+    : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {
+  ARM_MC::initLLVMToCVRegMapping(this);
+}
 
 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
   return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
 }
 
 const MCPhysReg*
 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();

llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

if (!UseIntegratedAssembler) {
     DwarfRegNumForCFI = true;
   }
 }
 
 void ARMCOFFMCAsmInfoMicrosoft::anchor() { }
 
 ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() {
   AlignmentIsInBytes = false;
+  SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::WinEH;
   PrivateGlobalPrefix = "$M";
   PrivateLabelPrefix = "$M";
   CommentString = ";";
 
   // Conditional Thumb 4-byte instructions can have an implicit IT.
   MaxInstLength = 6;
 }

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 namespace ARM_MC {
 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
+void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 //===----------------------------------------------------------------------===//
 
 #include "ARMMCTargetDesc.h"
 #include "ARMBaseInfo.h"
 #include "ARMInstPrinter.h"
 #include "ARMMCAsmInfo.h"
 #include "TargetInfo/ARMTargetInfo.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/DebugInfo/CodeView/CodeView.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"

 }
 
 static MCInstrInfo *createARMMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitARMMCInstrInfo(X);
   return X;
 }
 
+void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
+  // Mapping from CodeView to MC register id.
+  static const struct {
+    codeview::RegisterId CVReg;
+    MCPhysReg Reg;
+  } RegMap[] = {
+      {codeview::RegisterId::ARM_R0, ARM::R0},
+      {codeview::RegisterId::ARM_R1, ARM::R1},
+      {codeview::RegisterId::ARM_R2, ARM::R2},
+      {codeview::RegisterId::ARM_R3, ARM::R3},
+      {codeview::RegisterId::ARM_R4, ARM::R4},
+      {codeview::RegisterId::ARM_R5, ARM::R5},
+      {codeview::RegisterId::ARM_R6, ARM::R6},
+      {codeview::RegisterId::ARM_R7, ARM::R7},
+      {codeview::RegisterId::ARM_R8, ARM::R8},
+      {codeview::RegisterId::ARM_R9, ARM::R9},
+      {codeview::RegisterId::ARM_R10, ARM::R10},
+      {codeview::RegisterId::ARM_R11, ARM::R11},
+      {codeview::RegisterId::ARM_R12, ARM::R12},
+      {codeview::RegisterId::ARM_SP, ARM::SP},
+      {codeview::RegisterId::ARM_LR, ARM::LR},
+      {codeview::RegisterId::ARM_PC, ARM::PC},
+      {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
+      {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
+      {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
+      {codeview::RegisterId::ARM_FS0, ARM::S0},
+      {codeview::RegisterId::ARM_FS1, ARM::S1},
+      {codeview::RegisterId::ARM_FS2, ARM::S2},
+      {codeview::RegisterId::ARM_FS3, ARM::S3},
+      {codeview::RegisterId::ARM_FS4, ARM::S4},
+      {codeview::RegisterId::ARM_FS5, ARM::S5},
+      {codeview::RegisterId::ARM_FS6, ARM::S6},
+      {codeview::RegisterId::ARM_FS7, ARM::S7},
+      {codeview::RegisterId::ARM_FS8, ARM::S8},
+      {codeview::RegisterId::ARM_FS9, ARM::S9},
+      {codeview::RegisterId::ARM_FS10, ARM::S10},
+      {codeview::RegisterId::ARM_FS11, ARM::S11},
+      {codeview::RegisterId::ARM_FS12, ARM::S12},
+      {codeview::RegisterId::ARM_FS13, ARM::S13},
+      {codeview::RegisterId::ARM_FS14, ARM::S14},
+      {codeview::RegisterId::ARM_FS15, ARM::S15},
+      {codeview::RegisterId::ARM_FS16, ARM::S16},
+      {codeview::RegisterId::ARM_FS17, ARM::S17},
+      {codeview::RegisterId::ARM_FS18, ARM::S18},
+      {codeview::RegisterId::ARM_FS19, ARM::S19},
+      {codeview::RegisterId::ARM_FS20, ARM::S20},
+      {codeview::RegisterId::ARM_FS21, ARM::S21},
+      {codeview::RegisterId::ARM_FS22, ARM::S22},
+      {codeview::RegisterId::ARM_FS23, ARM::S23},
+      {codeview::RegisterId::ARM_FS24, ARM::S24},
+      {codeview::RegisterId::ARM_FS25, ARM::S25},
+      {codeview::RegisterId::ARM_FS26, ARM::S26},
+      {codeview::RegisterId::ARM_FS27, ARM::S27},
+      {codeview::RegisterId::ARM_FS28, ARM::S28},
+      {codeview::RegisterId::ARM_FS29, ARM::S29},
+      {codeview::RegisterId::ARM_FS30, ARM::S30},
+      {codeview::RegisterId::ARM_FS31, ARM::S31},
+      {codeview::RegisterId::ARM_ND0, ARM::D0},
+      {codeview::RegisterId::ARM_ND1, ARM::D1},
+      {codeview::RegisterId::ARM_ND2, ARM::D2},
+      {codeview::RegisterId::ARM_ND3, ARM::D3},
+      {codeview::RegisterId::ARM_ND4, ARM::D4},
+      {codeview::RegisterId::ARM_ND5, ARM::D5},
+      {codeview::RegisterId::ARM_ND6, ARM::D6},
+      {codeview::RegisterId::ARM_ND7, ARM::D7},
+      {codeview::RegisterId::ARM_ND8, ARM::D8},
+      {codeview::RegisterId::ARM_ND9, ARM::D9},
+      {codeview::RegisterId::ARM_ND10, ARM::D10},
+      {codeview::RegisterId::ARM_ND11, ARM::D11},
+      {codeview::RegisterId::ARM_ND12, ARM::D12},
+      {codeview::RegisterId::ARM_ND13, ARM::D13},
+      {codeview::RegisterId::ARM_ND14, ARM::D14},
+      {codeview::RegisterId::ARM_ND15, ARM::D15},
+      {codeview::RegisterId::ARM_ND16, ARM::D16},
+      {codeview::RegisterId::ARM_ND17, ARM::D17},
+      {codeview::RegisterId::ARM_ND18, ARM::D18},
+      {codeview::RegisterId::ARM_ND19, ARM::D19},
+      {codeview::RegisterId::ARM_ND20, ARM::D20},
+      {codeview::RegisterId::ARM_ND21, ARM::D21},
+      {codeview::RegisterId::ARM_ND22, ARM::D22},
+      {codeview::RegisterId::ARM_ND23, ARM::D23},
+      {codeview::RegisterId::ARM_ND24, ARM::D24},
+      {codeview::RegisterId::ARM_ND25, ARM::D25},
+      {codeview::RegisterId::ARM_ND26, ARM::D26},
+      {codeview::RegisterId::ARM_ND27, ARM::D27},
+      {codeview::RegisterId::ARM_ND28, ARM::D28},
+      {codeview::RegisterId::ARM_ND29, ARM::D29},
+      {codeview::RegisterId::ARM_ND30, ARM::D30},
+      {codeview::RegisterId::ARM_ND31, ARM::D31},
+      {codeview::RegisterId::ARM_NQ0, ARM::Q0},
+      {codeview::RegisterId::ARM_NQ1, ARM::Q1},
+      {codeview::RegisterId::ARM_NQ2, ARM::Q2},
+      {codeview::RegisterId::ARM_NQ3, ARM::Q3},
+      {codeview::RegisterId::ARM_NQ4, ARM::Q4},
+      {codeview::RegisterId::ARM_NQ5, ARM::Q5},
+      {codeview::RegisterId::ARM_NQ6, ARM::Q6},
+      {codeview::RegisterId::ARM_NQ7, ARM::Q7},
+      {codeview::RegisterId::ARM_NQ8, ARM::Q8},
+      {codeview::RegisterId::ARM_NQ9, ARM::Q9},
+      {codeview::RegisterId::ARM_NQ10, ARM::Q10},
+      {codeview::RegisterId::ARM_NQ11, ARM::Q11},
+      {codeview::RegisterId::ARM_NQ12, ARM::Q12},
+      {codeview::RegisterId::ARM_NQ13, ARM::Q13},
+      {codeview::RegisterId::ARM_NQ14, ARM::Q14},
+      {codeview::RegisterId::ARM_NQ15, ARM::Q15},
+  };
+  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
+    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
+}
+
 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
+  ARM_MC::initLLVMToCVRegMapping(X);
   return X;
 }
 
 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
                                      const Triple &TheTriple,
                                      const MCTargetOptions &Options) {
   MCAsmInfo *MAI;
   if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())

llvm/test/DebugInfo/COFF/ARMNT/arm-register-variables.ll

+; RUN: llc < %s -filetype=obj | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ
+
+; Generated from:
+
+; volatile int x;
+; int getint(void);
+; void putint(int);
+; static inline int inlineinc(int a) {
+;   int b = a + 1;
+;   ++x;
+;   return b;
+; }
+; void f(int p) {
+;   if (p) {
+;     int a = getint();
+;     int b = inlineinc(a);
+;     putint(b);
+;   } else {
+;     int c = getint();
+;     putint(c);
+;   }
+; }
+
+;      OBJ:   Compile3Sym {
+; OBJ-NEXT:     Kind: S_COMPILE3 (0x113C)
+; OBJ-NEXT:     Language: C (0x0)
+; OBJ-NEXT:     Flags [ (0x0)
+; OBJ-NEXT:     ]
+; OBJ-NEXT:     Machine: ARMNT (0xF4)
+
+;      OBJ: LocalSym {
+; OBJ-NEXT:   Kind: S_LOCAL (0x113E)
+; OBJ-NEXT:   Type: int (0x74)
+; OBJ-NEXT:   Flags [ (0x1)
+; OBJ-NEXT:     IsParameter (0x1)
+; OBJ-NEXT:   ]
+; OBJ-NEXT:   VarName: p
+; OBJ-NEXT: }
+; OBJ-NEXT: DefRangeRegisterRelSym {
+; OBJ-NEXT:   Kind: S_DEFRANGE_REGISTER_REL (0x1145)
+; OBJ-NEXT:   BaseRegister: ARM_SP (0x17)
+; OBJ-NEXT:   HasSpilledUDTMember: No
+; OBJ-NEXT:   OffsetInParent: 0
+; OBJ-NEXT:   BasePointerOffset: 12
+; OBJ-NEXT:   LocalVariableAddrRange {
+; OBJ-NEXT:     OffsetStart: .text+0x8
+; OBJ-NEXT:     ISectStart: 0x0
+; OBJ-NEXT:     Range: 0x1A
+; OBJ-NEXT:   }
+; OBJ-NEXT: }
+
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:w-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv7-pc-windows-msvc19.11.0"
+
+@x = dso_local global i32 0, align 4, !dbg !0
+
+; Function Attrs: noinline nounwind optnone
+define dso_local arm_aapcs_vfpcc void @f(i32 %p) !dbg !14 {
+entry:
+  %p.addr = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 %p, i32* %p.addr, align 4
+  call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !17, metadata !DIExpression()), !dbg !18
+  %0 = load i32, i32* %p.addr, align 4, !dbg !19
+  %tobool = icmp ne i32 %0, 0, !dbg !19
+  br i1 %tobool, label %if.then, label %if.else, !dbg !19
+
+if.then:                                          ; preds = %entry
+  call void @llvm.dbg.declare(metadata i32* %a, metadata !20, metadata !DIExpression()), !dbg !23
+  %call = call arm_aapcs_vfpcc i32 @getint(), !dbg !23
+  store i32 %call, i32* %a, align 4, !dbg !23
+  call void @llvm.dbg.declare(metadata i32* %b, metadata !24, metadata !DIExpression()), !dbg !25
+  %1 = load i32, i32* %a, align 4, !dbg !25
+  %call1 = call arm_aapcs_vfpcc i32 @inlineinc(i32 %1), !dbg !25
+  store i32 %call1, i32* %b, align 4, !dbg !25
+  %2 = load i32, i32* %b, align 4, !dbg !26
+  call arm_aapcs_vfpcc void @putint(i32 %2), !dbg !26
+  br label %if.end, !dbg !27
+
+if.else:                                          ; preds = %entry
+  call void @llvm.dbg.declare(metadata i32* %c, metadata !28, metadata !DIExpression()), !dbg !30
+  %call2 = call arm_aapcs_vfpcc i32 @getint(), !dbg !30
+  store i32 %call2, i32* %c, align 4, !dbg !30
+  %3 = load i32, i32* %c, align 4, !dbg !31
+  call arm_aapcs_vfpcc void @putint(i32 %3), !dbg !31
+  br label %if.end, !dbg !32
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void, !dbg !33
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+declare dso_local arm_aapcs_vfpcc i32 @getint()
+
+; Function Attrs: noinline nounwind optnone
+define internal arm_aapcs_vfpcc i32 @inlineinc(i32 %a) !dbg !34 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !37, metadata !DIExpression()), !dbg !38
+  call void @llvm.dbg.declare(metadata i32* %b, metadata !39, metadata !DIExpression()), !dbg !40
+  %0 = load i32, i32* %a.addr, align 4, !dbg !40
+  %add = add nsw i32 %0, 1, !dbg !40
+  store i32 %add, i32* %b, align 4, !dbg !40
+  %1 = load volatile i32, i32* @x, align 4, !dbg !41
+  %inc = add nsw i32 %1, 1, !dbg !41
+  store volatile i32 %inc, i32* @x, align 4, !dbg !41
+  %2 = load i32, i32* %b, align 4, !dbg !42
+  ret i32 %2, !dbg !42
+}
+
+declare dso_local arm_aapcs_vfpcc void @putint(i32)
+
+!llvm.dbg.cu = !{!2}
+!llvm.module.flags = !{!9, !10, !11, !12}
+!llvm.ident = !{!13}
+
+!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
+!1 = distinct !DIGlobalVariable(name: "x", scope: !2, file: !6, line: 1, type: !7, isLocal: false, isDefinition: true)
+!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, nameTableKind: None)
+!3 = !DIFile(filename: "F:\\tmp\\test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
+!4 = !{}
+!5 = !{!0}
+!6 = !DIFile(filename: "test.c", directory: "F:\\tmp", checksumkind: CSK_MD5, checksum: "5fbd15e58dd6931fc3081de308d52889")
+!7 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !8)
+!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!9 = !{i32 2, !"CodeView", i32 1}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
+!11 = !{i32 1, !"wchar_size", i32 2}
+!12 = !{i32 1, !"min_enum_size", i32 4}
+!13 = !{!"clang version 12.0.0 (https://github.com/llvm/llvm-project.git fc031d29bea856f2b91a250fd81c5f9fb79dbe07)"}
+!14 = distinct !DISubprogram(name: "f", scope: !6, file: !6, line: 9, type: !15, scopeLine: 9, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!15 = !DISubroutineType(types: !16)
+!16 = !{null, !8}
+!17 = !DILocalVariable(name: "p", arg: 1, scope: !14, file: !6, line: 9, type: !8)
+!18 = !DILocation(line: 9, scope: !14)
+!19 = !DILocation(line: 10, scope: !14)
+!20 = !DILocalVariable(name: "a", scope: !21, file: !6, line: 11, type: !8)
+!21 = distinct !DILexicalBlock(scope: !22, file: !6, line: 10)
+!22 = distinct !DILexicalBlock(scope: !14, file: !6, line: 10)
+!23 = !DILocation(line: 11, scope: !21)
+!24 = !DILocalVariable(name: "b", scope: !21, file: !6, line: 12, type: !8)
+!25 = !DILocation(line: 12, scope: !21)
+!26 = !DILocation(line: 13, scope: !21)
+!27 = !DILocation(line: 14, scope: !21)
+!28 = !DILocalVariable(name: "c", scope: !29, file: !6, line: 15, type: !8)
+!29 = distinct !DILexicalBlock(scope: !22, file: !6, line: 14)
+!30 = !DILocation(line: 15, scope: !29)
+!31 = !DILocation(line: 16, scope: !29)
+!32 = !DILocation(line: 17, scope: !29)
+!33 = !DILocation(line: 18, scope: !14)
+!34 = distinct !DISubprogram(name: "inlineinc", scope: !6, file: !6, line: 4, type: !35, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !4)
+!35 = !DISubroutineType(types: !36)
+!36 = !{!8, !8}
+!37 = !DILocalVariable(name: "a", arg: 1, scope: !34, file: !6, line: 4, type: !8)
+!38 = !DILocation(line: 4, scope: !34)
+!39 = !DILocalVariable(name: "b", scope: !34, file: !6, line: 5, type: !8)
+!40 = !DILocation(line: 5, scope: !34)
+!41 = !DILocation(line: 6, scope: !34)
+!42 = !DILocation(line: 7, scope: !34)

llvm/test/DebugInfo/COFF/ARMNT/lit.local.cfg

+if not 'ARM' in config.root.targets:
+    config.unsupported = True
+

llvm/tools/llvm-pdbutil/MinimalSymbolDumper.cpp

switch (Kind) {
     RETURN_CASE(FrameCookieKind, XorStackPointer, "xor stack ptr");
     RETURN_CASE(FrameCookieKind, XorFramePointer, "xor frame ptr");
     RETURN_CASE(FrameCookieKind, XorR13, "xor rot13");
   }
   return formatUnknownEnum(Kind);
 }
 
 static std::string formatRegisterId(RegisterId Id, CPUType Cpu) {
-  if (Cpu == CPUType::ARM64) {
+  if (Cpu == CPUType::ARMNT) {
+    switch (Id) {
+#define CV_REGISTERS_ARM
+#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
+#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
+#undef CV_REGISTER
+#undef CV_REGISTERS_ARM
+
+    default:
+      break;
+    }
+  } else if (Cpu == CPUType::ARM64) {
     switch (Id) {
 #define CV_REGISTERS_ARM64
 #define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name)
 #include "llvm/DebugInfo/CodeView/CodeViewRegisters.def"
 #undef CV_REGISTER
 #undef CV_REGISTERS_ARM64
 
     default: