[AArch64] [TableGen] Clean up boolean tests

[Paul-C-Anagnostopoulos]

Summary

Inspired by the new TableGen !not operator, I'm making a pass over the .td files to clean up boolean tests. Examples:

!if(!eq(bool, 1), ...) => !if(bool, ...)
!if(!eq(bool, 0), ...) => !if(!not(bool), ...)

I'm doing this one target at a time.

[Paul-C-Anagnostopoulos]

I will push this revision later today if there are no objections.

[dmgreen]

Sure, LGTM if they work the same way.

[Paul-C-Anagnostopoulos]

Yes, !if takes a boolean, so there is no need for things like !eq(s, 1). I'm finding these in one target at a time, while looking for places to use !not.

[dmgreen]

Brilliant, Thanks for the cleanup!

[Paul-C-Anagnostopoulos]

My pleasure.

[lattner]

Cool, please do

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
   bits<4> Pg;
   let Inst{31-23} = 0b001001010;
   let Inst{22}    = s;
   let Inst{21-9}  = 0b0110001111000;
   let Inst{8-5}   = Pg;
   let Inst{4}     = 0;
   let Inst{3-0}   = Pd;
 
-  let Defs = !if(!eq (s, 1), [NZCV], []);
+  let Defs = !if(s, [NZCV], []);
   let Uses = [FFR];
 }
 
 multiclass sve_int_rdffr_pred<bit s, string asm, SDPatternOperator op> {
   def _REAL : sve_int_rdffr_pred<s, asm>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   let Inst{20}    = nf;
   let Inst{19-16} = imm4;
   let Inst{15-13} = 0b101;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
-  let Uses = !if(!eq(nf, 1), [FFR], []);
-  let Defs = !if(!eq(nf, 1), [FFR], []);
+  let Uses = !if(nf, [FFR], []);
+  let Defs = !if(nf, [FFR], []);
 }
 
 multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
                                RegisterOperand listty, ZPRRegOp zprty> {
   def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
                   (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
: I<(outs VecList:$Zt), iops,
   let Inst{20-16} = Rm;
   let Inst{15-14} = 0b01;
   let Inst{13}    = ff;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Zt;
 
   let mayLoad = 1;
-  let Uses = !if(!eq(ff, 1), [FFR], []);
-  let Defs = !if(!eq(ff, 1), [FFR], []);
+  let Uses = !if(ff, [FFR], []);
+  let Defs = !if(ff, [FFR], []);
 }
 
 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
                           ZPRRegOp zprty, RegisterOperand gprty> {
   def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
                                asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
: I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm),
   let Inst{21-14} = 0b01100001;
   let Inst{13-10} = Pg;
   let Inst{9}     = 0b0;
   let Inst{8-5}   = Pn;
   let Inst{4}     = 0b0;
   let Inst{3-0}   = Pdm;
 
   let Constraints = "$Pdm = $_Pdm";
-  let Defs = !if(!eq (S, 0b1), [NZCV], []);
+  let Defs = !if(S, [NZCV], []);
 }
 
 multiclass sve_int_brkn<bits<1> opc, string asm, SDPatternOperator op> {
   def NAME : sve_int_brkn<opc, asm>;
 
   def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, nxv16i1, !cast<Instruction>(NAME)>;
 }