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[AMDGPU] Set rsrc1 flags for graphics shaders

Authored by Flakebi on Oct 14 2020, 9:02 AM.



Before they were only set for compute kernels and compute shaders but
not for other shaders.

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Flakebi created this revision.Oct 14 2020, 9:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 14 2020, 9:02 AM
Flakebi requested review of this revision.Oct 14 2020, 9:02 AM
nhaehnle added inline comments.Oct 14 2020, 4:25 PM

All shader types have MEM_ORDERED, and GS and HS also have WGP_MODE.

Annoyingly, the bits aren't always in the same place.

What I would suggest is:

  • Remove SIProgramInfo::ComputePGMRsrc1 because it's fully redundant
  • Add a getPgmRsrc1 helper function which computes the correct register value based on the calling convention
Flakebi updated this revision to Diff 300617.Oct 26 2020, 3:21 AM
Flakebi marked an inline comment as done.

Also set MEM_ORDERED and WGP_MODE for supported PGMRSrc1 registers.

Add helper function to get PGMRSrc1 from SIProgramInfo for all calling conventions.

arsenm added inline comments.Nov 2 2020, 9:20 AM


sebastian-ne added a subscriber: sebastian-ne.

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arsenm accepted this revision.Nov 3 2020, 6:49 AM
This revision is now accepted and ready to land.Nov 3 2020, 6:49 AM
This revision was landed with ongoing or failed builds.Nov 4 2020, 3:27 AM
This revision was automatically updated to reflect the committed changes.