Atm this doesn't work:
def MyWriteV : SchedWriteVariant<...>; def : SchedAlias<WriteV, MyWriteV>;
One problem with statements above is that assertion is triggered when inferFromTransitions tries to add empty write sequence which triggers assertion in findOrInsertRW.
Another problem is that transition is always added for given scheduling class, even though that class already has InstRW for a same processor.
Patch attempts to fix both of them
You may need REQUIRES: asserts too, to get dbg output.